1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5 ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
9 @glob = local_unnamed_addr global i32 0, align 4
11 ; Function Attrs: norecurse nounwind readnone
12 define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
13 ; CHECK-LABEL: test_llgtui:
14 ; CHECK: # %bb.0: # %entry
15 ; CHECK-NEXT: sub r3, r4, r3
16 ; CHECK-NEXT: rldicl r3, r3, 1, 63
19 %cmp = icmp ugt i32 %a, %b
20 %conv1 = zext i1 %cmp to i64
24 ; Function Attrs: norecurse nounwind readnone
25 define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
26 ; CHECK-LABEL: test_llgtui_sext:
27 ; CHECK: # %bb.0: # %entry
28 ; CHECK-NEXT: sub r3, r4, r3
29 ; CHECK-NEXT: sradi r3, r3, 63
32 %cmp = icmp ugt i32 %a, %b
33 %conv1 = sext i1 %cmp to i64
37 ; Function Attrs: norecurse nounwind readnone
38 define i64 @test_llgtui_z(i32 zeroext %a) {
39 ; CHECK-LABEL: test_llgtui_z:
40 ; CHECK: # %bb.0: # %entry
41 ; CHECK-NEXT: cntlzw r3, r3
42 ; CHECK-NEXT: srwi r3, r3, 5
43 ; CHECK-NEXT: xori r3, r3, 1
46 %cmp = icmp ne i32 %a, 0
47 %conv1 = zext i1 %cmp to i64
51 ; Function Attrs: norecurse nounwind readnone
52 define i64 @test_llgtui_sext_z(i32 zeroext %a) {
53 ; CHECK-LABEL: test_llgtui_sext_z:
54 ; CHECK: # %bb.0: # %entry
55 ; CHECK-NEXT: cntlzw r3, r3
56 ; CHECK-NEXT: srwi r3, r3, 5
57 ; CHECK-NEXT: xori r3, r3, 1
58 ; CHECK-NEXT: neg r3, r3
61 %cmp = icmp ne i32 %a, 0
62 %conv1 = sext i1 %cmp to i64
66 ; Function Attrs: norecurse nounwind
67 define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
68 ; CHECK-LABEL: test_llgtui_store:
69 ; CHECK: # %bb.0: # %entry
70 ; CHECK-NEXT: sub r3, r4, r3
71 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
73 ; CHECK-NEXT: rldicl r3, r3, 1, 63
74 ; CHECK-NEXT: stw r3, 0(r4)
77 %cmp = icmp ugt i32 %a, %b
78 %conv = zext i1 %cmp to i32
79 store i32 %conv, ptr @glob, align 4
83 ; Function Attrs: norecurse nounwind
84 define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
85 ; CHECK-LABEL: test_llgtui_sext_store:
86 ; CHECK: # %bb.0: # %entry
87 ; CHECK-NEXT: sub r3, r4, r3
88 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
89 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
90 ; CHECK-NEXT: sradi r3, r3, 63
91 ; CHECK-NEXT: stw r3, 0(r4)
94 %cmp = icmp ugt i32 %a, %b
95 %sub = sext i1 %cmp to i32
96 store i32 %sub, ptr @glob, align 4
100 ; Function Attrs: norecurse nounwind
101 define void @test_llgtui_z_store(i32 zeroext %a) {
102 ; CHECK-LABEL: test_llgtui_z_store:
103 ; CHECK: # %bb.0: # %entry
104 ; CHECK-NEXT: cntlzw r3, r3
105 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
106 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
107 ; CHECK-NEXT: srwi r3, r3, 5
108 ; CHECK-NEXT: xori r3, r3, 1
109 ; CHECK-NEXT: stw r3, 0(r4)
112 %cmp = icmp ne i32 %a, 0
113 %conv = zext i1 %cmp to i32
114 store i32 %conv, ptr @glob, align 4
118 ; Function Attrs: norecurse nounwind
119 define void @test_llgtui_sext_z_store(i32 zeroext %a) {
120 ; CHECK-LABEL: test_llgtui_sext_z_store:
121 ; CHECK: # %bb.0: # %entry
122 ; CHECK-NEXT: cntlzw r3, r3
123 ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
124 ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
125 ; CHECK-NEXT: srwi r3, r3, 5
126 ; CHECK-NEXT: xori r3, r3, 1
127 ; CHECK-NEXT: neg r3, r3
128 ; CHECK-NEXT: stw r3, 0(r4)
131 %cmp = icmp ne i32 %a, 0
132 %sub = sext i1 %cmp to i32
133 store i32 %sub, ptr @glob, align 4