| blob | af3132f88f001a86ddd3228f83041ec16dee8ed4 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4 ; RUN: FileCheck %s --check-prefix=CHECK-P8
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-P9
8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
9 ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
10 ; RUN: FileCheck %s --check-prefix=CHECK-BE
12 define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
13 ; CHECK-P8-LABEL: test2elt:
14 ; CHECK-P8: # %bb.0: # %entry
15 ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
16 ; CHECK-P8-NEXT: mtvsrd v3, r3
17 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
18 ; CHECK-P8-NEXT: addi r4, r4, .LCPI0_0@toc@l
19 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
20 ; CHECK-P8-NEXT: xxswapd v2, vs0
21 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
22 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
23 ; CHECK-P8-NEXT: blr
24 ;
25 ; CHECK-P9-LABEL: test2elt:
26 ; CHECK-P9: # %bb.0: # %entry
27 ; CHECK-P9-NEXT: mtfprd f0, r3
28 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha
29 ; CHECK-P9-NEXT: xxlxor vs2, vs2, vs2
30 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l
31 ; CHECK-P9-NEXT: lxv vs1, 0(r3)
32 ; CHECK-P9-NEXT: xxperm vs0, vs2, vs1
33 ; CHECK-P9-NEXT: xvcvuxddp v2, vs0
34 ; CHECK-P9-NEXT: blr
35 ;
36 ; CHECK-BE-LABEL: test2elt:
37 ; CHECK-BE: # %bb.0: # %entry
38 ; CHECK-BE-NEXT: mtfprwz f0, r3
39 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
40 ; CHECK-BE-NEXT: xxlxor vs2, vs2, vs2
41 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
42 ; CHECK-BE-NEXT: lxv vs1, 0(r3)
43 ; CHECK-BE-NEXT: xxperm vs0, vs2, vs1
44 ; CHECK-BE-NEXT: xvcvuxddp v2, vs0
45 ; CHECK-BE-NEXT: blr
46 entry:
47 %0 = bitcast i16 %a.coerce to <2 x i8>
48 %1 = uitofp <2 x i8> %0 to <2 x double>
49 ret <2 x double> %1
50 }
52 define void @test4elt(ptr noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
53 ; CHECK-P8-LABEL: test4elt:
54 ; CHECK-P8: # %bb.0: # %entry
55 ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
56 ; CHECK-P8-NEXT: mtvsrwz v4, r4
57 ; CHECK-P8-NEXT: xxlxor v5, v5, v5
58 ; CHECK-P8-NEXT: li r4, 16
59 ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
60 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
61 ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_1@toc@ha
62 ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_1@toc@l
63 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
64 ; CHECK-P8-NEXT: xxswapd v2, vs0
65 ; CHECK-P8-NEXT: vperm v2, v5, v4, v2
66 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
67 ; CHECK-P8-NEXT: xxswapd v3, vs1
68 ; CHECK-P8-NEXT: vperm v3, v5, v4, v3
69 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3
70 ; CHECK-P8-NEXT: xxswapd vs0, vs0
71 ; CHECK-P8-NEXT: xxswapd vs1, vs1
72 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
73 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
74 ; CHECK-P8-NEXT: blr
75 ;
76 ; CHECK-P9-LABEL: test4elt:
77 ; CHECK-P9: # %bb.0: # %entry
78 ; CHECK-P9-NEXT: mtvsrwz v2, r4
79 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
80 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
81 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
82 ; CHECK-P9-NEXT: lxv v3, 0(r4)
83 ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
84 ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
85 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
86 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
87 ; CHECK-P9-NEXT: lxv v3, 0(r4)
88 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
89 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
90 ; CHECK-P9-NEXT: xvcvuxddp vs1, v2
91 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
92 ; CHECK-P9-NEXT: blr
93 ;
94 ; CHECK-BE-LABEL: test4elt:
95 ; CHECK-BE: # %bb.0: # %entry
96 ; CHECK-BE-NEXT: mtvsrwz v2, r4
97 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_0@toc@ha
98 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
99 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_0@toc@l
100 ; CHECK-BE-NEXT: lxv v3, 0(r4)
101 ; CHECK-BE-NEXT: addis r4, r2, .LCPI1_1@toc@ha
102 ; CHECK-BE-NEXT: addi r4, r4, .LCPI1_1@toc@l
103 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
104 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
105 ; CHECK-BE-NEXT: lxv v3, 0(r4)
106 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
107 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
108 ; CHECK-BE-NEXT: xvcvuxddp vs1, v2
109 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
110 ; CHECK-BE-NEXT: blr
111 entry:
112 %0 = bitcast i32 %a.coerce to <4 x i8>
113 %1 = uitofp <4 x i8> %0 to <4 x double>
114 store <4 x double> %1, ptr %agg.result, align 32
115 ret void
116 }
118 define void @test8elt(ptr noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
119 ; CHECK-P8-LABEL: test8elt:
120 ; CHECK-P8: # %bb.0: # %entry
121 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
122 ; CHECK-P8-NEXT: mtvsrd v0, r4
123 ; CHECK-P8-NEXT: xxlxor v1, v1, v1
124 ; CHECK-P8-NEXT: li r4, 48
125 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
126 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
127 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_1@toc@ha
128 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_1@toc@l
129 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
130 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_3@toc@ha
131 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_3@toc@l
132 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
133 ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_2@toc@ha
134 ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_2@toc@l
135 ; CHECK-P8-NEXT: xxswapd v3, vs0
136 ; CHECK-P8-NEXT: vperm v3, v1, v0, v3
137 ; CHECK-P8-NEXT: xvcvuxddp vs0, v3
138 ; CHECK-P8-NEXT: xxswapd v4, vs1
139 ; CHECK-P8-NEXT: vperm v4, v1, v0, v4
140 ; CHECK-P8-NEXT: xvcvuxddp vs1, v4
141 ; CHECK-P8-NEXT: xxswapd v2, vs2
142 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
143 ; CHECK-P8-NEXT: vperm v2, v1, v0, v2
144 ; CHECK-P8-NEXT: xxswapd vs0, vs0
145 ; CHECK-P8-NEXT: xxswapd v5, vs2
146 ; CHECK-P8-NEXT: xvcvuxddp vs2, v2
147 ; CHECK-P8-NEXT: xxswapd vs1, vs1
148 ; CHECK-P8-NEXT: vperm v5, v1, v0, v5
149 ; CHECK-P8-NEXT: xvcvuxddp vs3, v5
150 ; CHECK-P8-NEXT: xxswapd vs2, vs2
151 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
152 ; CHECK-P8-NEXT: li r4, 32
153 ; CHECK-P8-NEXT: xxswapd vs3, vs3
154 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
155 ; CHECK-P8-NEXT: li r4, 16
156 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
157 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
158 ; CHECK-P8-NEXT: blr
159 ;
160 ; CHECK-P9-LABEL: test8elt:
161 ; CHECK-P9: # %bb.0: # %entry
162 ; CHECK-P9-NEXT: mtvsrd v2, r4
163 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
164 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
165 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
166 ; CHECK-P9-NEXT: lxv v3, 0(r4)
167 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
168 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
169 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
170 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
171 ; CHECK-P9-NEXT: lxv v3, 0(r4)
172 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_2@toc@ha
173 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_2@toc@l
174 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
175 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
176 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
177 ; CHECK-P9-NEXT: lxv v3, 0(r4)
178 ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_3@toc@ha
179 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_3@toc@l
180 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
181 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
182 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
183 ; CHECK-P9-NEXT: lxv v3, 0(r4)
184 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
185 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
186 ; CHECK-P9-NEXT: xvcvuxddp vs3, v2
187 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
188 ; CHECK-P9-NEXT: blr
189 ;
190 ; CHECK-BE-LABEL: test8elt:
191 ; CHECK-BE: # %bb.0: # %entry
192 ; CHECK-BE-NEXT: mtvsrd v2, r4
193 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_0@toc@ha
194 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
195 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_0@toc@l
196 ; CHECK-BE-NEXT: lxv v3, 0(r4)
197 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_1@toc@ha
198 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_1@toc@l
199 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
200 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
201 ; CHECK-BE-NEXT: lxv v3, 0(r4)
202 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_2@toc@ha
203 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_2@toc@l
204 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
205 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
206 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
207 ; CHECK-BE-NEXT: lxv v3, 0(r4)
208 ; CHECK-BE-NEXT: addis r4, r2, .LCPI2_3@toc@ha
209 ; CHECK-BE-NEXT: addi r4, r4, .LCPI2_3@toc@l
210 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
211 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
212 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
213 ; CHECK-BE-NEXT: lxv v3, 0(r4)
214 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
215 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
216 ; CHECK-BE-NEXT: xvcvuxddp vs3, v2
217 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
218 ; CHECK-BE-NEXT: blr
219 entry:
220 %0 = bitcast i64 %a.coerce to <8 x i8>
221 %1 = uitofp <8 x i8> %0 to <8 x double>
222 store <8 x double> %1, ptr %agg.result, align 64
223 ret void
224 }
226 define void @test16elt(ptr noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
227 ; CHECK-P8-LABEL: test16elt:
228 ; CHECK-P8: # %bb.0: # %entry
229 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha
230 ; CHECK-P8-NEXT: xxlxor v0, v0, v0
231 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_0@toc@l
232 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
233 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_1@toc@ha
234 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_1@toc@l
235 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
236 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_3@toc@ha
237 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_3@toc@l
238 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
239 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_4@toc@ha
240 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_4@toc@l
241 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
242 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_6@toc@ha
243 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_6@toc@l
244 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
245 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_7@toc@ha
246 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_7@toc@l
247 ; CHECK-P8-NEXT: lxvd2x vs5, 0, r4
248 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_5@toc@ha
249 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_5@toc@l
250 ; CHECK-P8-NEXT: xxswapd v7, vs0
251 ; CHECK-P8-NEXT: vperm v7, v0, v2, v7
252 ; CHECK-P8-NEXT: xvcvuxddp vs0, v7
253 ; CHECK-P8-NEXT: xxswapd v8, vs1
254 ; CHECK-P8-NEXT: vperm v8, v0, v2, v8
255 ; CHECK-P8-NEXT: xvcvuxddp vs1, v8
256 ; CHECK-P8-NEXT: xxswapd v1, vs2
257 ; CHECK-P8-NEXT: vperm v1, v0, v2, v1
258 ; CHECK-P8-NEXT: xxswapd vs0, vs0
259 ; CHECK-P8-NEXT: xxswapd v6, vs3
260 ; CHECK-P8-NEXT: vperm v6, v0, v2, v6
261 ; CHECK-P8-NEXT: xvcvuxddp vs6, v6
262 ; CHECK-P8-NEXT: xxswapd vs1, vs1
263 ; CHECK-P8-NEXT: xxswapd v3, vs4
264 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
265 ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_2@toc@ha
266 ; CHECK-P8-NEXT: addi r4, r4, .LCPI3_2@toc@l
267 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
268 ; CHECK-P8-NEXT: li r4, 112
269 ; CHECK-P8-NEXT: vperm v3, v0, v2, v3
270 ; CHECK-P8-NEXT: xvcvuxddp vs3, v3
271 ; CHECK-P8-NEXT: xxswapd v4, vs5
272 ; CHECK-P8-NEXT: xvcvuxddp vs5, v1
273 ; CHECK-P8-NEXT: vperm v4, v0, v2, v4
274 ; CHECK-P8-NEXT: xxswapd v5, vs4
275 ; CHECK-P8-NEXT: xvcvuxddp vs4, v4
276 ; CHECK-P8-NEXT: vperm v5, v0, v2, v5
277 ; CHECK-P8-NEXT: xxswapd vs3, vs3
278 ; CHECK-P8-NEXT: xvcvuxddp vs7, v5
279 ; CHECK-P8-NEXT: xxswapd v9, vs2
280 ; CHECK-P8-NEXT: xxswapd vs4, vs4
281 ; CHECK-P8-NEXT: vperm v2, v0, v2, v9
282 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
283 ; CHECK-P8-NEXT: li r4, 96
284 ; CHECK-P8-NEXT: xvcvuxddp vs2, v2
285 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
286 ; CHECK-P8-NEXT: li r4, 80
287 ; CHECK-P8-NEXT: xxswapd vs4, vs5
288 ; CHECK-P8-NEXT: xxswapd vs7, vs7
289 ; CHECK-P8-NEXT: xxswapd vs3, vs6
290 ; CHECK-P8-NEXT: stxvd2x vs7, r3, r4
291 ; CHECK-P8-NEXT: li r4, 64
292 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
293 ; CHECK-P8-NEXT: li r4, 48
294 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
295 ; CHECK-P8-NEXT: li r4, 32
296 ; CHECK-P8-NEXT: xxswapd vs2, vs2
297 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
298 ; CHECK-P8-NEXT: li r4, 16
299 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
300 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
301 ; CHECK-P8-NEXT: blr
302 ;
303 ; CHECK-P9-LABEL: test16elt:
304 ; CHECK-P9: # %bb.0: # %entry
305 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_0@toc@ha
306 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
307 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_0@toc@l
308 ; CHECK-P9-NEXT: lxv v3, 0(r4)
309 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_1@toc@ha
310 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_1@toc@l
311 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
312 ; CHECK-P9-NEXT: xvcvuxddp vs0, v3
313 ; CHECK-P9-NEXT: lxv v3, 0(r4)
314 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_2@toc@ha
315 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_2@toc@l
316 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
317 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
318 ; CHECK-P9-NEXT: xvcvuxddp vs1, v3
319 ; CHECK-P9-NEXT: lxv v3, 0(r4)
320 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_3@toc@ha
321 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_3@toc@l
322 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
323 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
324 ; CHECK-P9-NEXT: xvcvuxddp vs2, v3
325 ; CHECK-P9-NEXT: lxv v3, 0(r4)
326 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_4@toc@ha
327 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_4@toc@l
328 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
329 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
330 ; CHECK-P9-NEXT: xvcvuxddp vs3, v3
331 ; CHECK-P9-NEXT: lxv v3, 0(r4)
332 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_5@toc@ha
333 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_5@toc@l
334 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
335 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
336 ; CHECK-P9-NEXT: xvcvuxddp vs4, v3
337 ; CHECK-P9-NEXT: lxv v3, 0(r4)
338 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_6@toc@ha
339 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_6@toc@l
340 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
341 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
342 ; CHECK-P9-NEXT: xvcvuxddp vs5, v3
343 ; CHECK-P9-NEXT: lxv v3, 0(r4)
344 ; CHECK-P9-NEXT: addis r4, r2, .LCPI3_7@toc@ha
345 ; CHECK-P9-NEXT: addi r4, r4, .LCPI3_7@toc@l
346 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
347 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
348 ; CHECK-P9-NEXT: xvcvuxddp vs6, v3
349 ; CHECK-P9-NEXT: lxv v3, 0(r4)
350 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
351 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
352 ; CHECK-P9-NEXT: xvcvuxddp vs7, v2
353 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
354 ; CHECK-P9-NEXT: blr
355 ;
356 ; CHECK-BE-LABEL: test16elt:
357 ; CHECK-BE: # %bb.0: # %entry
358 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
359 ; CHECK-BE-NEXT: xxlxor v4, v4, v4
360 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
361 ; CHECK-BE-NEXT: lxv v3, 0(r4)
362 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
363 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
364 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
365 ; CHECK-BE-NEXT: xvcvuxddp vs0, v3
366 ; CHECK-BE-NEXT: lxv v3, 0(r4)
367 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
368 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
369 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
370 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
371 ; CHECK-BE-NEXT: xvcvuxddp vs1, v3
372 ; CHECK-BE-NEXT: lxv v3, 0(r4)
373 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
374 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
375 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
376 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
377 ; CHECK-BE-NEXT: xvcvuxddp vs2, v3
378 ; CHECK-BE-NEXT: lxv v3, 0(r4)
379 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_4@toc@ha
380 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_4@toc@l
381 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
382 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
383 ; CHECK-BE-NEXT: xvcvuxddp vs3, v3
384 ; CHECK-BE-NEXT: lxv v3, 0(r4)
385 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_5@toc@ha
386 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_5@toc@l
387 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
388 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
389 ; CHECK-BE-NEXT: xvcvuxddp vs4, v3
390 ; CHECK-BE-NEXT: lxv v3, 0(r4)
391 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_6@toc@ha
392 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_6@toc@l
393 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
394 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
395 ; CHECK-BE-NEXT: xvcvuxddp vs5, v3
396 ; CHECK-BE-NEXT: lxv v3, 0(r4)
397 ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_7@toc@ha
398 ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_7@toc@l
399 ; CHECK-BE-NEXT: vperm v3, v4, v2, v3
400 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
401 ; CHECK-BE-NEXT: xvcvuxddp vs6, v3
402 ; CHECK-BE-NEXT: lxv v3, 0(r4)
403 ; CHECK-BE-NEXT: vperm v2, v4, v2, v3
404 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
405 ; CHECK-BE-NEXT: xvcvuxddp vs7, v2
406 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
407 ; CHECK-BE-NEXT: blr
408 entry:
409 %0 = uitofp <16 x i8> %a to <16 x double>
410 store <16 x double> %0, ptr %agg.result, align 128
411 ret void
412 }
414 define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
415 ; CHECK-P8-LABEL: test2elt_signed:
416 ; CHECK-P8: # %bb.0: # %entry
417 ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
418 ; CHECK-P8-NEXT: mtvsrd v3, r3
419 ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
420 ; CHECK-P8-NEXT: addi r4, r4, .LCPI4_0@toc@l
421 ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
422 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
423 ; CHECK-P8-NEXT: xxswapd v2, vs0
424 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
425 ; CHECK-P8-NEXT: lxvd2x v3, 0, r3
426 ; CHECK-P8-NEXT: vsld v2, v2, v3
427 ; CHECK-P8-NEXT: vsrad v2, v2, v3
428 ; CHECK-P8-NEXT: xvcvsxddp v2, v2
429 ; CHECK-P8-NEXT: blr
430 ;
431 ; CHECK-P9-LABEL: test2elt_signed:
432 ; CHECK-P9: # %bb.0: # %entry
433 ; CHECK-P9-NEXT: mtvsrd v2, r3
434 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha
435 ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l
436 ; CHECK-P9-NEXT: lxv vs0, 0(r3)
437 ; CHECK-P9-NEXT: xxperm v2, v2, vs0
438 ; CHECK-P9-NEXT: vextsb2d v2, v2
439 ; CHECK-P9-NEXT: xvcvsxddp v2, v2
440 ; CHECK-P9-NEXT: blr
441 ;
442 ; CHECK-BE-LABEL: test2elt_signed:
443 ; CHECK-BE: # %bb.0: # %entry
444 ; CHECK-BE-NEXT: mtvsrwz v2, r3
445 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha
446 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l
447 ; CHECK-BE-NEXT: lxv vs0, 0(r3)
448 ; CHECK-BE-NEXT: xxperm v2, v2, vs0
449 ; CHECK-BE-NEXT: vextsb2d v2, v2
450 ; CHECK-BE-NEXT: xvcvsxddp v2, v2
451 ; CHECK-BE-NEXT: blr
452 entry:
453 %0 = bitcast i16 %a.coerce to <2 x i8>
454 %1 = sitofp <2 x i8> %0 to <2 x double>
455 ret <2 x double> %1
456 }
458 define void @test4elt_signed(ptr noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
459 ; CHECK-P8-LABEL: test4elt_signed:
460 ; CHECK-P8: # %bb.0: # %entry
461 ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
462 ; CHECK-P8-NEXT: mtvsrwz v4, r4
463 ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
464 ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
465 ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
466 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
467 ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_2@toc@ha
468 ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_2@toc@l
469 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
470 ; CHECK-P8-NEXT: xxswapd v2, vs0
471 ; CHECK-P8-NEXT: vperm v2, v4, v4, v2
472 ; CHECK-P8-NEXT: xxswapd v3, vs1
473 ; CHECK-P8-NEXT: vperm v3, v4, v4, v3
474 ; CHECK-P8-NEXT: lxvd2x v4, 0, r4
475 ; CHECK-P8-NEXT: li r4, 16
476 ; CHECK-P8-NEXT: vsld v2, v2, v4
477 ; CHECK-P8-NEXT: vsrad v2, v2, v4
478 ; CHECK-P8-NEXT: xvcvsxddp vs0, v2
479 ; CHECK-P8-NEXT: vsld v2, v3, v4
480 ; CHECK-P8-NEXT: vsrad v2, v2, v4
481 ; CHECK-P8-NEXT: xvcvsxddp vs1, v2
482 ; CHECK-P8-NEXT: xxswapd vs0, vs0
483 ; CHECK-P8-NEXT: xxswapd vs1, vs1
484 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
485 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
486 ; CHECK-P8-NEXT: blr
487 ;
488 ; CHECK-P9-LABEL: test4elt_signed:
489 ; CHECK-P9: # %bb.0: # %entry
490 ; CHECK-P9-NEXT: mtvsrwz v2, r4
491 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
492 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
493 ; CHECK-P9-NEXT: lxv v3, 0(r4)
494 ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
495 ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
496 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
497 ; CHECK-P9-NEXT: vextsb2d v3, v3
498 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
499 ; CHECK-P9-NEXT: lxv v3, 0(r4)
500 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
501 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
502 ; CHECK-P9-NEXT: vextsb2d v2, v2
503 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
504 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
505 ; CHECK-P9-NEXT: blr
506 ;
507 ; CHECK-BE-LABEL: test4elt_signed:
508 ; CHECK-BE: # %bb.0: # %entry
509 ; CHECK-BE-NEXT: mtvsrwz v2, r4
510 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
511 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
512 ; CHECK-BE-NEXT: lxv v3, 0(r4)
513 ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
514 ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
515 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
516 ; CHECK-BE-NEXT: vextsb2d v3, v3
517 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
518 ; CHECK-BE-NEXT: lxv v3, 0(r4)
519 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
520 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
521 ; CHECK-BE-NEXT: vextsb2d v2, v2
522 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
523 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
524 ; CHECK-BE-NEXT: blr
525 entry:
526 %0 = bitcast i32 %a.coerce to <4 x i8>
527 %1 = sitofp <4 x i8> %0 to <4 x double>
528 store <4 x double> %1, ptr %agg.result, align 32
529 ret void
530 }
532 define void @test8elt_signed(ptr noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
533 ; CHECK-P8-LABEL: test8elt_signed:
534 ; CHECK-P8: # %bb.0: # %entry
535 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
536 ; CHECK-P8-NEXT: mtvsrd v0, r4
537 ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
538 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
539 ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l
540 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r5
541 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha
542 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_2@toc@l
543 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r5
544 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_4@toc@ha
545 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_4@toc@l
546 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
547 ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_3@toc@ha
548 ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_3@toc@l
549 ; CHECK-P8-NEXT: xxswapd v3, vs0
550 ; CHECK-P8-NEXT: vperm v3, v0, v0, v3
551 ; CHECK-P8-NEXT: xxswapd v4, vs1
552 ; CHECK-P8-NEXT: vperm v4, v0, v0, v4
553 ; CHECK-P8-NEXT: xxswapd v2, vs2
554 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r5
555 ; CHECK-P8-NEXT: vperm v2, v0, v0, v2
556 ; CHECK-P8-NEXT: xxswapd v5, vs2
557 ; CHECK-P8-NEXT: vperm v5, v0, v0, v5
558 ; CHECK-P8-NEXT: lxvd2x v0, 0, r4
559 ; CHECK-P8-NEXT: li r4, 48
560 ; CHECK-P8-NEXT: vsld v2, v2, v0
561 ; CHECK-P8-NEXT: vsld v5, v5, v0
562 ; CHECK-P8-NEXT: vsld v3, v3, v0
563 ; CHECK-P8-NEXT: vsld v4, v4, v0
564 ; CHECK-P8-NEXT: vsrad v2, v2, v0
565 ; CHECK-P8-NEXT: vsrad v5, v5, v0
566 ; CHECK-P8-NEXT: vsrad v3, v3, v0
567 ; CHECK-P8-NEXT: vsrad v4, v4, v0
568 ; CHECK-P8-NEXT: xvcvsxddp vs2, v2
569 ; CHECK-P8-NEXT: xvcvsxddp vs3, v5
570 ; CHECK-P8-NEXT: xvcvsxddp vs0, v3
571 ; CHECK-P8-NEXT: xvcvsxddp vs1, v4
572 ; CHECK-P8-NEXT: xxswapd vs2, vs2
573 ; CHECK-P8-NEXT: xxswapd vs3, vs3
574 ; CHECK-P8-NEXT: xxswapd vs1, vs1
575 ; CHECK-P8-NEXT: xxswapd vs0, vs0
576 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
577 ; CHECK-P8-NEXT: li r4, 32
578 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
579 ; CHECK-P8-NEXT: li r4, 16
580 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
581 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
582 ; CHECK-P8-NEXT: blr
583 ;
584 ; CHECK-P9-LABEL: test8elt_signed:
585 ; CHECK-P9: # %bb.0: # %entry
586 ; CHECK-P9-NEXT: mtvsrd v2, r4
587 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
588 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
589 ; CHECK-P9-NEXT: lxv v3, 0(r4)
590 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
591 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
592 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
593 ; CHECK-P9-NEXT: vextsb2d v3, v3
594 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
595 ; CHECK-P9-NEXT: lxv v3, 0(r4)
596 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_2@toc@ha
597 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_2@toc@l
598 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
599 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
600 ; CHECK-P9-NEXT: vextsb2d v3, v3
601 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
602 ; CHECK-P9-NEXT: lxv v3, 0(r4)
603 ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_3@toc@ha
604 ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_3@toc@l
605 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
606 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
607 ; CHECK-P9-NEXT: vextsb2d v3, v3
608 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
609 ; CHECK-P9-NEXT: lxv v3, 0(r4)
610 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
611 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
612 ; CHECK-P9-NEXT: vextsb2d v2, v2
613 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
614 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
615 ; CHECK-P9-NEXT: blr
616 ;
617 ; CHECK-BE-LABEL: test8elt_signed:
618 ; CHECK-BE: # %bb.0: # %entry
619 ; CHECK-BE-NEXT: mtvsrd v2, r4
620 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
621 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
622 ; CHECK-BE-NEXT: lxv v3, 0(r4)
623 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
624 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
625 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
626 ; CHECK-BE-NEXT: vextsb2d v3, v3
627 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
628 ; CHECK-BE-NEXT: lxv v3, 0(r4)
629 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
630 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
631 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
632 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
633 ; CHECK-BE-NEXT: vextsb2d v3, v3
634 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
635 ; CHECK-BE-NEXT: lxv v3, 0(r4)
636 ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
637 ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
638 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
639 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
640 ; CHECK-BE-NEXT: vextsb2d v3, v3
641 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
642 ; CHECK-BE-NEXT: lxv v3, 0(r4)
643 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
644 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
645 ; CHECK-BE-NEXT: vextsb2d v2, v2
646 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
647 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
648 ; CHECK-BE-NEXT: blr
649 entry:
650 %0 = bitcast i64 %a.coerce to <8 x i8>
651 %1 = sitofp <8 x i8> %0 to <8 x double>
652 store <8 x double> %1, ptr %agg.result, align 64
653 ret void
654 }
656 define void @test16elt_signed(ptr noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 {
657 ; CHECK-P8-LABEL: test16elt_signed:
658 ; CHECK-P8: # %bb.0: # %entry
659 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha
660 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_0@toc@l
661 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r4
662 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_2@toc@ha
663 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_2@toc@l
664 ; CHECK-P8-NEXT: lxvd2x vs1, 0, r4
665 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_4@toc@ha
666 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_4@toc@l
667 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
668 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_7@toc@ha
669 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_7@toc@l
670 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
671 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_8@toc@ha
672 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_8@toc@l
673 ; CHECK-P8-NEXT: lxvd2x vs4, 0, r4
674 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_6@toc@ha
675 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_6@toc@l
676 ; CHECK-P8-NEXT: xxswapd v6, vs0
677 ; CHECK-P8-NEXT: vperm v6, v2, v2, v6
678 ; CHECK-P8-NEXT: xxswapd v7, vs1
679 ; CHECK-P8-NEXT: vperm v7, v2, v2, v7
680 ; CHECK-P8-NEXT: xxswapd v0, vs2
681 ; CHECK-P8-NEXT: vperm v0, v2, v2, v0
682 ; CHECK-P8-NEXT: xxswapd v3, vs3
683 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
684 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_5@toc@ha
685 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_5@toc@l
686 ; CHECK-P8-NEXT: vperm v3, v2, v2, v3
687 ; CHECK-P8-NEXT: xxswapd v4, vs4
688 ; CHECK-P8-NEXT: vperm v4, v2, v2, v4
689 ; CHECK-P8-NEXT: xxswapd v5, vs3
690 ; CHECK-P8-NEXT: lxvd2x vs3, 0, r4
691 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_3@toc@ha
692 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_3@toc@l
693 ; CHECK-P8-NEXT: lxvd2x vs2, 0, r4
694 ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_1@toc@ha
695 ; CHECK-P8-NEXT: addi r4, r4, .LCPI7_1@toc@l
696 ; CHECK-P8-NEXT: vperm v5, v2, v2, v5
697 ; CHECK-P8-NEXT: xxswapd v1, vs3
698 ; CHECK-P8-NEXT: vperm v1, v2, v2, v1
699 ; CHECK-P8-NEXT: xxswapd v8, vs2
700 ; CHECK-P8-NEXT: vperm v2, v2, v2, v8
701 ; CHECK-P8-NEXT: lxvd2x v8, 0, r4
702 ; CHECK-P8-NEXT: li r4, 112
703 ; CHECK-P8-NEXT: vsld v4, v4, v8
704 ; CHECK-P8-NEXT: vsld v3, v3, v8
705 ; CHECK-P8-NEXT: vsld v5, v5, v8
706 ; CHECK-P8-NEXT: vsld v1, v1, v8
707 ; CHECK-P8-NEXT: vsld v0, v0, v8
708 ; CHECK-P8-NEXT: vsld v2, v2, v8
709 ; CHECK-P8-NEXT: vsld v6, v6, v8
710 ; CHECK-P8-NEXT: vsld v7, v7, v8
711 ; CHECK-P8-NEXT: vsrad v4, v4, v8
712 ; CHECK-P8-NEXT: vsrad v3, v3, v8
713 ; CHECK-P8-NEXT: vsrad v5, v5, v8
714 ; CHECK-P8-NEXT: vsrad v1, v1, v8
715 ; CHECK-P8-NEXT: vsrad v0, v0, v8
716 ; CHECK-P8-NEXT: vsrad v2, v2, v8
717 ; CHECK-P8-NEXT: vsrad v6, v6, v8
718 ; CHECK-P8-NEXT: vsrad v7, v7, v8
719 ; CHECK-P8-NEXT: xvcvsxddp vs4, v4
720 ; CHECK-P8-NEXT: xvcvsxddp vs3, v3
721 ; CHECK-P8-NEXT: xvcvsxddp vs7, v5
722 ; CHECK-P8-NEXT: xvcvsxddp vs6, v1
723 ; CHECK-P8-NEXT: xvcvsxddp vs5, v0
724 ; CHECK-P8-NEXT: xvcvsxddp vs2, v2
725 ; CHECK-P8-NEXT: xvcvsxddp vs0, v6
726 ; CHECK-P8-NEXT: xvcvsxddp vs1, v7
727 ; CHECK-P8-NEXT: xxswapd vs4, vs4
728 ; CHECK-P8-NEXT: xxswapd vs3, vs3
729 ; CHECK-P8-NEXT: xxswapd vs7, vs7
730 ; CHECK-P8-NEXT: xxswapd vs2, vs2
731 ; CHECK-P8-NEXT: xxswapd vs1, vs1
732 ; CHECK-P8-NEXT: xxswapd vs0, vs0
733 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
734 ; CHECK-P8-NEXT: li r4, 96
735 ; CHECK-P8-NEXT: xxswapd vs4, vs5
736 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
737 ; CHECK-P8-NEXT: li r4, 80
738 ; CHECK-P8-NEXT: stxvd2x vs7, r3, r4
739 ; CHECK-P8-NEXT: li r4, 64
740 ; CHECK-P8-NEXT: xxswapd vs3, vs6
741 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
742 ; CHECK-P8-NEXT: li r4, 48
743 ; CHECK-P8-NEXT: stxvd2x vs4, r3, r4
744 ; CHECK-P8-NEXT: li r4, 32
745 ; CHECK-P8-NEXT: stxvd2x vs2, r3, r4
746 ; CHECK-P8-NEXT: li r4, 16
747 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
748 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
749 ; CHECK-P8-NEXT: blr
750 ;
751 ; CHECK-P9-LABEL: test16elt_signed:
752 ; CHECK-P9: # %bb.0: # %entry
753 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_0@toc@ha
754 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_0@toc@l
755 ; CHECK-P9-NEXT: lxv v3, 0(r4)
756 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_1@toc@ha
757 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_1@toc@l
758 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
759 ; CHECK-P9-NEXT: vextsb2d v3, v3
760 ; CHECK-P9-NEXT: xvcvsxddp vs0, v3
761 ; CHECK-P9-NEXT: lxv v3, 0(r4)
762 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_2@toc@ha
763 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_2@toc@l
764 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
765 ; CHECK-P9-NEXT: stxv vs0, 0(r3)
766 ; CHECK-P9-NEXT: vextsb2d v3, v3
767 ; CHECK-P9-NEXT: xvcvsxddp vs1, v3
768 ; CHECK-P9-NEXT: lxv v3, 0(r4)
769 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_3@toc@ha
770 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_3@toc@l
771 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
772 ; CHECK-P9-NEXT: stxv vs1, 16(r3)
773 ; CHECK-P9-NEXT: vextsb2d v3, v3
774 ; CHECK-P9-NEXT: xvcvsxddp vs2, v3
775 ; CHECK-P9-NEXT: lxv v3, 0(r4)
776 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_4@toc@ha
777 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_4@toc@l
778 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
779 ; CHECK-P9-NEXT: stxv vs2, 32(r3)
780 ; CHECK-P9-NEXT: vextsb2d v3, v3
781 ; CHECK-P9-NEXT: xvcvsxddp vs3, v3
782 ; CHECK-P9-NEXT: lxv v3, 0(r4)
783 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_5@toc@ha
784 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_5@toc@l
785 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
786 ; CHECK-P9-NEXT: stxv vs3, 48(r3)
787 ; CHECK-P9-NEXT: vextsb2d v3, v3
788 ; CHECK-P9-NEXT: xvcvsxddp vs4, v3
789 ; CHECK-P9-NEXT: lxv v3, 0(r4)
790 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_6@toc@ha
791 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_6@toc@l
792 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
793 ; CHECK-P9-NEXT: stxv vs4, 64(r3)
794 ; CHECK-P9-NEXT: vextsb2d v3, v3
795 ; CHECK-P9-NEXT: xvcvsxddp vs5, v3
796 ; CHECK-P9-NEXT: lxv v3, 0(r4)
797 ; CHECK-P9-NEXT: addis r4, r2, .LCPI7_7@toc@ha
798 ; CHECK-P9-NEXT: addi r4, r4, .LCPI7_7@toc@l
799 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
800 ; CHECK-P9-NEXT: stxv vs5, 80(r3)
801 ; CHECK-P9-NEXT: vextsb2d v3, v3
802 ; CHECK-P9-NEXT: xvcvsxddp vs6, v3
803 ; CHECK-P9-NEXT: lxv v3, 0(r4)
804 ; CHECK-P9-NEXT: vperm v2, v2, v2, v3
805 ; CHECK-P9-NEXT: stxv vs6, 96(r3)
806 ; CHECK-P9-NEXT: vextsb2d v2, v2
807 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
808 ; CHECK-P9-NEXT: stxv vs7, 112(r3)
809 ; CHECK-P9-NEXT: blr
810 ;
811 ; CHECK-BE-LABEL: test16elt_signed:
812 ; CHECK-BE: # %bb.0: # %entry
813 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
814 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
815 ; CHECK-BE-NEXT: lxv v3, 0(r4)
816 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
817 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
818 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
819 ; CHECK-BE-NEXT: vextsb2d v3, v3
820 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
821 ; CHECK-BE-NEXT: lxv v3, 0(r4)
822 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
823 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
824 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
825 ; CHECK-BE-NEXT: stxv vs0, 0(r3)
826 ; CHECK-BE-NEXT: vextsb2d v3, v3
827 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
828 ; CHECK-BE-NEXT: lxv v3, 0(r4)
829 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
830 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
831 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
832 ; CHECK-BE-NEXT: stxv vs1, 16(r3)
833 ; CHECK-BE-NEXT: vextsb2d v3, v3
834 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
835 ; CHECK-BE-NEXT: lxv v3, 0(r4)
836 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha
837 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l
838 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
839 ; CHECK-BE-NEXT: stxv vs2, 32(r3)
840 ; CHECK-BE-NEXT: vextsb2d v3, v3
841 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3
842 ; CHECK-BE-NEXT: lxv v3, 0(r4)
843 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha
844 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l
845 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
846 ; CHECK-BE-NEXT: stxv vs3, 48(r3)
847 ; CHECK-BE-NEXT: vextsb2d v3, v3
848 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
849 ; CHECK-BE-NEXT: lxv v3, 0(r4)
850 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha
851 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l
852 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
853 ; CHECK-BE-NEXT: stxv vs4, 64(r3)
854 ; CHECK-BE-NEXT: vextsb2d v3, v3
855 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3
856 ; CHECK-BE-NEXT: lxv v3, 0(r4)
857 ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha
858 ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l
859 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
860 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
861 ; CHECK-BE-NEXT: vextsb2d v3, v3
862 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
863 ; CHECK-BE-NEXT: lxv v3, 0(r4)
864 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
865 ; CHECK-BE-NEXT: stxv vs6, 96(r3)
866 ; CHECK-BE-NEXT: vextsb2d v2, v2
867 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
868 ; CHECK-BE-NEXT: stxv vs7, 112(r3)
869 ; CHECK-BE-NEXT: blr
870 entry:
871 %0 = sitofp <16 x i8> %a to <16 x double>
872 store <16 x double> %0, ptr %agg.result, align 128
873 ret void
874 }