llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td

   1 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
   2
   3 include "llvm/Target/Target.td"
   4 include "GlobalISelEmitterCommon.td"
   5
   6 // Verify that patterns will add temp registers if NumDstDef > NumSrcDef when NumSrcDef >= 1
   7 // and that these temp registers are marked as dead
   8 // Note: This is an extension of the test GlobalISelEmitter-output-discard.td
   9
  10 def THREE_OUTS : I<(outs GPR32:$out1, GPR32:$out2, GPR32:$out3), (ins GPR32:$in1), []>;
  11
  12 def SDTTwoOut : SDTypeProfile<2, 1, [
  13   SDTCisInt<0>, SDTCisInt<1>
  14 ]>;
  15 def two_out : SDNode<"MyTgt::ONE_OUT", SDTTwoOut, []>;
  16 def G_TWO_OUT : MyTargetGenericInstruction{
  17   let OutOperandList = (outs type0:$out1, type0:$out2);
  18   let InOperandList = (ins type0:$in);
  19 }
  20 def : GINodeEquiv<G_TWO_OUT, two_out>;
  21
  22 def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>;
  23
  24 // CHECK:      GIM_CheckOpcode, /*MI*/0, MyTarget::G_TWO_OUT,
  25 // CHECK-NEXT: // MIs[0] out1
  26 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
  27 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
  28 // CHECK-NEXT: // MIs[0] out2
  29 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
  30 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
  31 // CHECK-NEXT: // MIs[0] val
  32 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
  33 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
  34 // CHECK-NEXT: // (two_out:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val)  =>  (THREE_OUTS:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val)
  35 // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
  36 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::THREE_OUTS,
  37 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // out1
  38 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // out2
  39 // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
  40 // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val
  41 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
  42 // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,