| blob | 39c79f4104e6e64af99f1c2ebca5cadf81d8a7e2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3 ; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
4 ; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
5 ; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
7 declare i4 @llvm.uadd.sat.i4(i4, i4)
8 declare i8 @llvm.uadd.sat.i8(i8, i8)
9 declare i16 @llvm.uadd.sat.i16(i16, i16)
10 declare i32 @llvm.uadd.sat.i32(i32, i32)
11 declare i64 @llvm.uadd.sat.i64(i64, i64)
13 define i32 @func(i32 %x, i32 %y) nounwind {
14 ; CHECK-T1-LABEL: func:
15 ; CHECK-T1: @ %bb.0:
16 ; CHECK-T1-NEXT: adds r0, r0, r1
17 ; CHECK-T1-NEXT: blo .LBB0_2
18 ; CHECK-T1-NEXT: @ %bb.1:
19 ; CHECK-T1-NEXT: movs r0, #0
20 ; CHECK-T1-NEXT: mvns r0, r0
21 ; CHECK-T1-NEXT: .LBB0_2:
22 ; CHECK-T1-NEXT: bx lr
23 ;
24 ; CHECK-T2-LABEL: func:
25 ; CHECK-T2: @ %bb.0:
26 ; CHECK-T2-NEXT: adds r0, r0, r1
27 ; CHECK-T2-NEXT: it hs
28 ; CHECK-T2-NEXT: movhs.w r0, #-1
29 ; CHECK-T2-NEXT: bx lr
30 ;
31 ; CHECK-ARM-LABEL: func:
32 ; CHECK-ARM: @ %bb.0:
33 ; CHECK-ARM-NEXT: adds r0, r0, r1
34 ; CHECK-ARM-NEXT: mvnhs r0, #0
35 ; CHECK-ARM-NEXT: bx lr
36 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y)
37 ret i32 %tmp
38 }
40 define i64 @func2(i64 %x, i64 %y) nounwind {
41 ; CHECK-T1-LABEL: func2:
42 ; CHECK-T1: @ %bb.0:
43 ; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
44 ; CHECK-T1-NEXT: push {r4, r5, r7, lr}
45 ; CHECK-T1-NEXT: movs r5, #0
46 ; CHECK-T1-NEXT: adds r4, r0, r2
47 ; CHECK-T1-NEXT: adcs r1, r3
48 ; CHECK-T1-NEXT: mov r3, r5
49 ; CHECK-T1-NEXT: adcs r3, r5
50 ; CHECK-T1-NEXT: mvns r2, r5
51 ; CHECK-T1-NEXT: cmp r3, #0
52 ; CHECK-T1-NEXT: mov r0, r2
53 ; CHECK-T1-NEXT: beq .LBB1_3
54 ; CHECK-T1-NEXT: @ %bb.1:
55 ; CHECK-T1-NEXT: cmp r3, #0
56 ; CHECK-T1-NEXT: beq .LBB1_4
57 ; CHECK-T1-NEXT: .LBB1_2:
58 ; CHECK-T1-NEXT: mov r1, r2
59 ; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
60 ; CHECK-T1-NEXT: .LBB1_3:
61 ; CHECK-T1-NEXT: mov r0, r4
62 ; CHECK-T1-NEXT: cmp r3, #0
63 ; CHECK-T1-NEXT: bne .LBB1_2
64 ; CHECK-T1-NEXT: .LBB1_4:
65 ; CHECK-T1-NEXT: mov r2, r1
66 ; CHECK-T1-NEXT: mov r1, r2
67 ; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
68 ;
69 ; CHECK-T2-LABEL: func2:
70 ; CHECK-T2: @ %bb.0:
71 ; CHECK-T2-NEXT: adds r0, r0, r2
72 ; CHECK-T2-NEXT: mov.w r12, #0
73 ; CHECK-T2-NEXT: adcs r1, r3
74 ; CHECK-T2-NEXT: adcs r2, r12, #0
75 ; CHECK-T2-NEXT: itt ne
76 ; CHECK-T2-NEXT: movne.w r0, #-1
77 ; CHECK-T2-NEXT: movne.w r1, #-1
78 ; CHECK-T2-NEXT: bx lr
79 ;
80 ; CHECK-ARM-LABEL: func2:
81 ; CHECK-ARM: @ %bb.0:
82 ; CHECK-ARM-NEXT: adds r0, r0, r2
83 ; CHECK-ARM-NEXT: mov r12, #0
84 ; CHECK-ARM-NEXT: adcs r1, r1, r3
85 ; CHECK-ARM-NEXT: adcs r2, r12, #0
86 ; CHECK-ARM-NEXT: mvnne r0, #0
87 ; CHECK-ARM-NEXT: mvnne r1, #0
88 ; CHECK-ARM-NEXT: bx lr
89 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y)
90 ret i64 %tmp
91 }
93 define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
94 ; CHECK-T1-LABEL: func16:
95 ; CHECK-T1: @ %bb.0:
96 ; CHECK-T1-NEXT: adds r0, r0, r1
97 ; CHECK-T1-NEXT: ldr r1, .LCPI2_0
98 ; CHECK-T1-NEXT: cmp r0, r1
99 ; CHECK-T1-NEXT: blo .LBB2_2
100 ; CHECK-T1-NEXT: @ %bb.1:
101 ; CHECK-T1-NEXT: mov r0, r1
102 ; CHECK-T1-NEXT: .LBB2_2:
103 ; CHECK-T1-NEXT: bx lr
104 ; CHECK-T1-NEXT: .p2align 2
105 ; CHECK-T1-NEXT: @ %bb.3:
106 ; CHECK-T1-NEXT: .LCPI2_0:
107 ; CHECK-T1-NEXT: .long 65535 @ 0xffff
108 ;
109 ; CHECK-T2NODSP-LABEL: func16:
110 ; CHECK-T2NODSP: @ %bb.0:
111 ; CHECK-T2NODSP-NEXT: add r1, r0
112 ; CHECK-T2NODSP-NEXT: movw r0, #65535
113 ; CHECK-T2NODSP-NEXT: cmp r1, r0
114 ; CHECK-T2NODSP-NEXT: it lo
115 ; CHECK-T2NODSP-NEXT: movlo r0, r1
116 ; CHECK-T2NODSP-NEXT: bx lr
117 ;
118 ; CHECK-T2DSP-LABEL: func16:
119 ; CHECK-T2DSP: @ %bb.0:
120 ; CHECK-T2DSP-NEXT: uqadd16 r0, r0, r1
121 ; CHECK-T2DSP-NEXT: uxth r0, r0
122 ; CHECK-T2DSP-NEXT: bx lr
123 ;
124 ; CHECK-ARM-LABEL: func16:
125 ; CHECK-ARM: @ %bb.0:
126 ; CHECK-ARM-NEXT: uqadd16 r0, r0, r1
127 ; CHECK-ARM-NEXT: uxth r0, r0
128 ; CHECK-ARM-NEXT: bx lr
129 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %y)
130 ret i16 %tmp
131 }
133 define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
134 ; CHECK-T1-LABEL: func8:
135 ; CHECK-T1: @ %bb.0:
136 ; CHECK-T1-NEXT: adds r0, r0, r1
137 ; CHECK-T1-NEXT: cmp r0, #255
138 ; CHECK-T1-NEXT: blo .LBB3_2
139 ; CHECK-T1-NEXT: @ %bb.1:
140 ; CHECK-T1-NEXT: movs r0, #255
141 ; CHECK-T1-NEXT: .LBB3_2:
142 ; CHECK-T1-NEXT: bx lr
143 ;
144 ; CHECK-T2NODSP-LABEL: func8:
145 ; CHECK-T2NODSP: @ %bb.0:
146 ; CHECK-T2NODSP-NEXT: add r0, r1
147 ; CHECK-T2NODSP-NEXT: cmp r0, #255
148 ; CHECK-T2NODSP-NEXT: it hs
149 ; CHECK-T2NODSP-NEXT: movhs r0, #255
150 ; CHECK-T2NODSP-NEXT: bx lr
151 ;
152 ; CHECK-T2DSP-LABEL: func8:
153 ; CHECK-T2DSP: @ %bb.0:
154 ; CHECK-T2DSP-NEXT: uqadd8 r0, r0, r1
155 ; CHECK-T2DSP-NEXT: uxtb r0, r0
156 ; CHECK-T2DSP-NEXT: bx lr
157 ;
158 ; CHECK-ARM-LABEL: func8:
159 ; CHECK-ARM: @ %bb.0:
160 ; CHECK-ARM-NEXT: uqadd8 r0, r0, r1
161 ; CHECK-ARM-NEXT: uxtb r0, r0
162 ; CHECK-ARM-NEXT: bx lr
163 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %y)
164 ret i8 %tmp
165 }
167 define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
168 ; CHECK-T1-LABEL: func3:
169 ; CHECK-T1: @ %bb.0:
170 ; CHECK-T1-NEXT: adds r0, r0, r1
171 ; CHECK-T1-NEXT: cmp r0, #15
172 ; CHECK-T1-NEXT: blo .LBB4_2
173 ; CHECK-T1-NEXT: @ %bb.1:
174 ; CHECK-T1-NEXT: movs r0, #15
175 ; CHECK-T1-NEXT: .LBB4_2:
176 ; CHECK-T1-NEXT: bx lr
177 ;
178 ; CHECK-T2-LABEL: func3:
179 ; CHECK-T2: @ %bb.0:
180 ; CHECK-T2-NEXT: add r0, r1
181 ; CHECK-T2-NEXT: cmp r0, #15
182 ; CHECK-T2-NEXT: it hs
183 ; CHECK-T2-NEXT: movhs r0, #15
184 ; CHECK-T2-NEXT: bx lr
185 ;
186 ; CHECK-ARM-LABEL: func3:
187 ; CHECK-ARM: @ %bb.0:
188 ; CHECK-ARM-NEXT: add r0, r0, r1
189 ; CHECK-ARM-NEXT: cmp r0, #15
190 ; CHECK-ARM-NEXT: movhs r0, #15
191 ; CHECK-ARM-NEXT: bx lr
192 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y)
193 ret i4 %tmp
194 }