clang/test/CodeGen/attr-target-clones-riscv.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
   2 // RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o - %s | FileCheck %s
   3
   4 __attribute__((target_clones("default", "arch=+m"))) int foo1(void) {
   5   return 1;
   6 }
   7 __attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; }
   8 __attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; }
   9 __attribute__((target_clones("default", "arch=+zbb,+v"))) int
  10 foo4(void) {
  11   return 4;
  12 }
  13 __attribute__((target_clones("default"))) int foo5(void) { return 5; }
  14 __attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; }
  15
  16 __attribute__((target_clones("default", "arch=+zbb", "arch=+zba", "arch=+zbb,+zba"))) int foo7(void) { return 2; }
  17 __attribute__((target_clones("default", "arch=+zbb;priority=2", "arch=+zba;priority=1", "arch=+zbb,+zba;priority=3"))) int foo8(void) { return 2; }
  18 __attribute__((target_clones("default", "arch=+zbb;priority=1", "priority=2;arch=+zba", "priority=3;arch=+zbb,+zba"))) int foo9(void) { return 2; }
  19
  20
  21 int bar() { return foo1() + foo2() + foo3() + foo4() + foo5() + foo6() + foo7() + foo8() + foo9(); }
  22
  23 //.
  24 // CHECK: @__riscv_feature_bits = external dso_local global { i32, [2 x i64] }
  25 // CHECK: @foo1.ifunc = weak_odr alias i32 (), ptr @foo1
  26 // CHECK: @foo2.ifunc = weak_odr alias i32 (), ptr @foo2
  27 // CHECK: @foo3.ifunc = weak_odr alias i32 (), ptr @foo3
  28 // CHECK: @foo4.ifunc = weak_odr alias i32 (), ptr @foo4
  29 // CHECK: @foo5.ifunc = weak_odr alias i32 (), ptr @foo5
  30 // CHECK: @foo6.ifunc = weak_odr alias i32 (), ptr @foo6
  31 // CHECK: @foo7.ifunc = weak_odr alias i32 (), ptr @foo7
  32 // CHECK: @foo8.ifunc = weak_odr alias i32 (), ptr @foo8
  33 // CHECK: @foo9.ifunc = weak_odr alias i32 (), ptr @foo9
  34 // CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
  35 // CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
  36 // CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
  37 // CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver
  38 // CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
  39 // CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver
  40 // CHECK: @foo7 = weak_odr ifunc i32 (), ptr @foo7.resolver
  41 // CHECK: @foo8 = weak_odr ifunc i32 (), ptr @foo8.resolver
  42 // CHECK: @foo9 = weak_odr ifunc i32 (), ptr @foo9.resolver
  43 //.
  44 // CHECK-LABEL: define dso_local signext i32 @foo1.default(
  45 // CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
  46 // CHECK-NEXT:  entry:
  47 // CHECK-NEXT:    ret i32 1
  48 //
  49 //
  50 // CHECK-LABEL: define dso_local signext i32 @foo1._m(
  51 // CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
  52 // CHECK-NEXT:  entry:
  53 // CHECK-NEXT:    ret i32 1
  54 //
  55 //
  56 // CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
  57 // CHECK-NEXT:  resolver_entry:
  58 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
  59 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  60 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 4096
  61 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
  62 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  63 // CHECK:       resolver_return:
  64 // CHECK-NEXT:    ret ptr @foo1._m
  65 // CHECK:       resolver_else:
  66 // CHECK-NEXT:    ret ptr @foo1.default
  67 //
  68 //
  69 // CHECK-LABEL: define dso_local signext i32 @foo2.default(
  70 // CHECK-SAME: ) #[[ATTR0]] {
  71 // CHECK-NEXT:  entry:
  72 // CHECK-NEXT:    ret i32 2
  73 //
  74 //
  75 // CHECK-LABEL: define dso_local signext i32 @foo2._zbb(
  76 // CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
  77 // CHECK-NEXT:  entry:
  78 // CHECK-NEXT:    ret i32 2
  79 //
  80 //
  81 // CHECK-LABEL: define dso_local signext i32 @foo2._m(
  82 // CHECK-SAME: ) #[[ATTR1]] {
  83 // CHECK-NEXT:  entry:
  84 // CHECK-NEXT:    ret i32 2
  85 //
  86 //
  87 // CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
  88 // CHECK-NEXT:  resolver_entry:
  89 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
  90 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  91 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
  92 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
  93 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
  94 // CHECK:       resolver_return:
  95 // CHECK-NEXT:    ret ptr @foo2._zbb
  96 // CHECK:       resolver_else:
  97 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
  98 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 4096
  99 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 4096
 100 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 101 // CHECK:       resolver_return1:
 102 // CHECK-NEXT:    ret ptr @foo2._m
 103 // CHECK:       resolver_else2:
 104 // CHECK-NEXT:    ret ptr @foo2.default
 105 //
 106 //
 107 // CHECK-LABEL: define dso_local signext i32 @foo3.default(
 108 // CHECK-SAME: ) #[[ATTR0]] {
 109 // CHECK-NEXT:  entry:
 110 // CHECK-NEXT:    ret i32 3
 111 //
 112 //
 113 // CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb(
 114 // CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
 115 // CHECK-NEXT:  entry:
 116 // CHECK-NEXT:    ret i32 3
 117 //
 118 //
 119 // CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
 120 // CHECK-NEXT:  resolver_entry:
 121 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 122 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 123 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
 124 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
 125 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 126 // CHECK:       resolver_return:
 127 // CHECK-NEXT:    ret ptr @foo3._c_zbb
 128 // CHECK:       resolver_else:
 129 // CHECK-NEXT:    ret ptr @foo3.default
 130 //
 131 //
 132 // CHECK-LABEL: define dso_local signext i32 @foo4.default(
 133 // CHECK-SAME: ) #[[ATTR0]] {
 134 // CHECK-NEXT:  entry:
 135 // CHECK-NEXT:    ret i32 4
 136 //
 137 //
 138 // CHECK-LABEL: define dso_local signext i32 @foo4._v_zbb(
 139 // CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
 140 // CHECK-NEXT:  entry:
 141 // CHECK-NEXT:    ret i32 4
 142 //
 143 //
 144 // CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
 145 // CHECK-NEXT:  resolver_entry:
 146 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 147 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 148 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 270532608
 149 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608
 150 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 151 // CHECK:       resolver_return:
 152 // CHECK-NEXT:    ret ptr @foo4._v_zbb
 153 // CHECK:       resolver_else:
 154 // CHECK-NEXT:    ret ptr @foo4.default
 155 //
 156 //
 157 // CHECK-LABEL: define dso_local signext i32 @foo5.default(
 158 // CHECK-SAME: ) #[[ATTR0]] {
 159 // CHECK-NEXT:  entry:
 160 // CHECK-NEXT:    ret i32 5
 161 //
 162 //
 163 // CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat {
 164 // CHECK-NEXT:  resolver_entry:
 165 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 166 // CHECK-NEXT:    ret ptr @foo5.default
 167 //
 168 //
 169 // CHECK-LABEL: define dso_local signext i32 @foo6.default(
 170 // CHECK-SAME: ) #[[ATTR0]] {
 171 // CHECK-NEXT:  entry:
 172 // CHECK-NEXT:    ret i32 2
 173 //
 174 //
 175 // CHECK-LABEL: define dso_local signext i32 @foo6._zvkt(
 176 // CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
 177 // CHECK-NEXT:  entry:
 178 // CHECK-NEXT:    ret i32 2
 179 //
 180 //
 181 // CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
 182 // CHECK-NEXT:  resolver_entry:
 183 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 184 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 185 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488
 186 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488
 187 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 188 // CHECK:       resolver_return:
 189 // CHECK-NEXT:    ret ptr @foo6._zvkt
 190 // CHECK:       resolver_else:
 191 // CHECK-NEXT:    ret ptr @foo6.default
 192 //
 193 //
 194 // CHECK-LABEL: define dso_local signext i32 @foo7.default(
 195 // CHECK-SAME: ) #[[ATTR0]] {
 196 // CHECK-NEXT:  entry:
 197 // CHECK-NEXT:    ret i32 2
 198 //
 199 //
 200 // CHECK-LABEL: define dso_local signext i32 @foo7._zbb(
 201 // CHECK-SAME: ) #[[ATTR2]] {
 202 // CHECK-NEXT:  entry:
 203 // CHECK-NEXT:    ret i32 2
 204 //
 205 //
 206 // CHECK-LABEL: define dso_local signext i32 @foo7._zba(
 207 // CHECK-SAME: ) #[[ATTR6:[0-9]+]] {
 208 // CHECK-NEXT:  entry:
 209 // CHECK-NEXT:    ret i32 2
 210 //
 211 //
 212 // CHECK-LABEL: define dso_local signext i32 @foo7._zba_zbb(
 213 // CHECK-SAME: ) #[[ATTR7:[0-9]+]] {
 214 // CHECK-NEXT:  entry:
 215 // CHECK-NEXT:    ret i32 2
 216 //
 217 //
 218 // CHECK-LABEL: define weak_odr ptr @foo7.resolver() comdat {
 219 // CHECK-NEXT:  resolver_entry:
 220 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 221 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 222 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
 223 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
 224 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 225 // CHECK:       resolver_return:
 226 // CHECK-NEXT:    ret ptr @foo7._zbb
 227 // CHECK:       resolver_else:
 228 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 229 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
 230 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
 231 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 232 // CHECK:       resolver_return1:
 233 // CHECK-NEXT:    ret ptr @foo7._zba
 234 // CHECK:       resolver_else2:
 235 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 236 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 402653184
 237 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 402653184
 238 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 239 // CHECK:       resolver_return3:
 240 // CHECK-NEXT:    ret ptr @foo7._zba_zbb
 241 // CHECK:       resolver_else4:
 242 // CHECK-NEXT:    ret ptr @foo7.default
 243 //
 244 //
 245 // CHECK-LABEL: define dso_local signext i32 @foo8.default(
 246 // CHECK-SAME: ) #[[ATTR0]] {
 247 // CHECK-NEXT:  entry:
 248 // CHECK-NEXT:    ret i32 2
 249 //
 250 //
 251 // CHECK-LABEL: define dso_local signext i32 @foo8._zbb(
 252 // CHECK-SAME: ) #[[ATTR2]] {
 253 // CHECK-NEXT:  entry:
 254 // CHECK-NEXT:    ret i32 2
 255 //
 256 //
 257 // CHECK-LABEL: define dso_local signext i32 @foo8._zba(
 258 // CHECK-SAME: ) #[[ATTR6]] {
 259 // CHECK-NEXT:  entry:
 260 // CHECK-NEXT:    ret i32 2
 261 //
 262 //
 263 // CHECK-LABEL: define dso_local signext i32 @foo8._zba_zbb(
 264 // CHECK-SAME: ) #[[ATTR7]] {
 265 // CHECK-NEXT:  entry:
 266 // CHECK-NEXT:    ret i32 2
 267 //
 268 //
 269 // CHECK-LABEL: define weak_odr ptr @foo8.resolver() comdat {
 270 // CHECK-NEXT:  resolver_entry:
 271 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 272 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 273 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 274 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 275 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 276 // CHECK:       resolver_return:
 277 // CHECK-NEXT:    ret ptr @foo8._zba_zbb
 278 // CHECK:       resolver_else:
 279 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 280 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 268435456
 281 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 268435456
 282 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 283 // CHECK:       resolver_return1:
 284 // CHECK-NEXT:    ret ptr @foo8._zbb
 285 // CHECK:       resolver_else2:
 286 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 287 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 134217728
 288 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 134217728
 289 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 290 // CHECK:       resolver_return3:
 291 // CHECK-NEXT:    ret ptr @foo8._zba
 292 // CHECK:       resolver_else4:
 293 // CHECK-NEXT:    ret ptr @foo8.default
 294 //
 295 //
 296 // CHECK-LABEL: define dso_local signext i32 @foo9.default(
 297 // CHECK-SAME: ) #[[ATTR0]] {
 298 // CHECK-NEXT:  entry:
 299 // CHECK-NEXT:    ret i32 2
 300 //
 301 //
 302 // CHECK-LABEL: define dso_local signext i32 @foo9._zbb(
 303 // CHECK-SAME: ) #[[ATTR2]] {
 304 // CHECK-NEXT:  entry:
 305 // CHECK-NEXT:    ret i32 2
 306 //
 307 //
 308 // CHECK-LABEL: define dso_local signext i32 @foo9._zba(
 309 // CHECK-SAME: ) #[[ATTR6]] {
 310 // CHECK-NEXT:  entry:
 311 // CHECK-NEXT:    ret i32 2
 312 //
 313 //
 314 // CHECK-LABEL: define dso_local signext i32 @foo9._zba_zbb(
 315 // CHECK-SAME: ) #[[ATTR7]] {
 316 // CHECK-NEXT:  entry:
 317 // CHECK-NEXT:    ret i32 2
 318 //
 319 //
 320 // CHECK-LABEL: define weak_odr ptr @foo9.resolver() comdat {
 321 // CHECK-NEXT:  resolver_entry:
 322 // CHECK-NEXT:    call void @__init_riscv_feature_bits(ptr null)
 323 // CHECK-NEXT:    [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 324 // CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[TMP0]], 402653184
 325 // CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 402653184
 326 // CHECK-NEXT:    br i1 [[TMP2]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
 327 // CHECK:       resolver_return:
 328 // CHECK-NEXT:    ret ptr @foo9._zba_zbb
 329 // CHECK:       resolver_else:
 330 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 331 // CHECK-NEXT:    [[TMP4:%.*]] = and i64 [[TMP3]], 134217728
 332 // CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i64 [[TMP4]], 134217728
 333 // CHECK-NEXT:    br i1 [[TMP5]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
 334 // CHECK:       resolver_return1:
 335 // CHECK-NEXT:    ret ptr @foo9._zba
 336 // CHECK:       resolver_else2:
 337 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [2 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
 338 // CHECK-NEXT:    [[TMP7:%.*]] = and i64 [[TMP6]], 268435456
 339 // CHECK-NEXT:    [[TMP8:%.*]] = icmp eq i64 [[TMP7]], 268435456
 340 // CHECK-NEXT:    br i1 [[TMP8]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]]
 341 // CHECK:       resolver_return3:
 342 // CHECK-NEXT:    ret ptr @foo9._zbb
 343 // CHECK:       resolver_else4:
 344 // CHECK-NEXT:    ret ptr @foo9.default
 345 //
 346 //
 347 // CHECK-LABEL: define dso_local signext i32 @bar(
 348 // CHECK-SAME: ) #[[ATTR0]] {
 349 // CHECK-NEXT:  entry:
 350 // CHECK-NEXT:    [[CALL:%.*]] = call signext i32 @foo1()
 351 // CHECK-NEXT:    [[CALL1:%.*]] = call signext i32 @foo2()
 352 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
 353 // CHECK-NEXT:    [[CALL2:%.*]] = call signext i32 @foo3()
 354 // CHECK-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
 355 // CHECK-NEXT:    [[CALL4:%.*]] = call signext i32 @foo4()
 356 // CHECK-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
 357 // CHECK-NEXT:    [[CALL6:%.*]] = call signext i32 @foo5()
 358 // CHECK-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
 359 // CHECK-NEXT:    [[CALL8:%.*]] = call signext i32 @foo6()
 360 // CHECK-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CALL8]]
 361 // CHECK-NEXT:    [[CALL10:%.*]] = call signext i32 @foo7()
 362 // CHECK-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CALL10]]
 363 // CHECK-NEXT:    [[CALL12:%.*]] = call signext i32 @foo8()
 364 // CHECK-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CALL12]]
 365 // CHECK-NEXT:    [[CALL14:%.*]] = call signext i32 @foo9()
 366 // CHECK-NEXT:    [[ADD15:%.*]] = add nsw i32 [[ADD13]], [[CALL14]]
 367 // CHECK-NEXT:    ret i32 [[ADD15]]
 368 //
 369 //.
 370 // CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
 371 // CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
 372 // CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" }
 373 // CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb" }
 374 // CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zbb,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
 375 // CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zvkt" }
 376 // CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba" }
 377 // CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zba,+zbb" }
 378 //.
 379 // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
 380 // CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
 381 // CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
 382 // CHECK: [[META3]] = !{!"rv64i2p1"}
 383 // CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
 384 // CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
 385 //.