[DAGCombiner] Add target hook function to decide folding (mul (add x, c1), c2)
[llvm-project.git] / llvm / test / MC / AMDGPU / misaligned-vgpr-tuples-err.s
blobd2cd4383bb4171f53ab8f382b0b45169b5cc5ec8
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx90a %s 2>&1 | FileCheck --check-prefixes=GFX90A --implicit-check-not=error: %s
3 v_add_f64 v[1:2], v[1:2], v[1:2]
4 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
6 global_load_dwordx3 v[1:3], v[0:1], off
7 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
9 global_load_dwordx4 v[1:4], v[0:1], off
10 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
12 image_load v[1:5], v2, s[0:7] dmask:0xf unorm
13 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
15 v_mfma_f32_32x32x8f16 a[0:15], a[1:2], v[0:1], a[0:15]
16 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
18 v_mfma_i32_4x4x4i8 a[1:4], a0, v1, 2
19 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
21 v_mfma_f32_16x16x1f32 a[0:15], a0, v1, a[1:16]
22 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned
24 v_mfma_f32_32x32x1f32 a[0:31], v0, v1, a[1:32]
25 // GFX90A: error: invalid register class: vgpr tuples must be 64 bit aligned