1 // RUN
: llvm-mc
-triple amdgcn-
-amdpal
%s | FileCheck
%s
8 .entry_point: ps_amdpal
9 .scratch_memory_size: 0
12 .internal_pipeline_hash:
352 .end_amdgpu_pal_metadata
354 // CHECK
: 0x2c06 (SPI_SHADER_PGM_CHKSUM_PS
)
355 // CHECK
: 0x2c07 (SPI_SHADER_PGM_RSRC3_PS
)
356 // CHECK
: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS
)
357 // CHECK
: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS
)
358 // CHECK
: 0x2c0c (SPI_SHADER_USER_DATA_PS_0
)
359 // CHECK
: 0x2c0d (SPI_SHADER_USER_DATA_PS_1
)
360 // CHECK
: 0x2c0e (SPI_SHADER_USER_DATA_PS_2
)
361 // CHECK
: 0x2c0f (SPI_SHADER_USER_DATA_PS_3
)
362 // CHECK
: 0x2c10 (SPI_SHADER_USER_DATA_PS_4
)
363 // CHECK
: 0x2c11 (SPI_SHADER_USER_DATA_PS_5
)
364 // CHECK
: 0x2c12 (SPI_SHADER_USER_DATA_PS_6
)
365 // CHECK
: 0x2c13 (SPI_SHADER_USER_DATA_PS_7
)
366 // CHECK
: 0x2c14 (SPI_SHADER_USER_DATA_PS_8
)
367 // CHECK
: 0x2c15 (SPI_SHADER_USER_DATA_PS_9
)
368 // CHECK
: 0x2c16 (SPI_SHADER_USER_DATA_PS_10
)
369 // CHECK
: 0x2c17 (SPI_SHADER_USER_DATA_PS_11
)
370 // CHECK
: 0x2c18 (SPI_SHADER_USER_DATA_PS_12
)
371 // CHECK
: 0x2c19 (SPI_SHADER_USER_DATA_PS_13
)
372 // CHECK
: 0x2c1a (SPI_SHADER_USER_DATA_PS_14
)
373 // CHECK
: 0x2c1b (SPI_SHADER_USER_DATA_PS_15
)
374 // CHECK
: 0x2c1c (SPI_SHADER_USER_DATA_PS_16
)
375 // CHECK
: 0x2c1d (SPI_SHADER_USER_DATA_PS_17
)
376 // CHECK
: 0x2c1e (SPI_SHADER_USER_DATA_PS_18
)
377 // CHECK
: 0x2c1f (SPI_SHADER_USER_DATA_PS_19
)
378 // CHECK
: 0x2c20 (SPI_SHADER_USER_DATA_PS_20
)
379 // CHECK
: 0x2c21 (SPI_SHADER_USER_DATA_PS_21
)
380 // CHECK
: 0x2c22 (SPI_SHADER_USER_DATA_PS_22
)
381 // CHECK
: 0x2c23 (SPI_SHADER_USER_DATA_PS_23
)
382 // CHECK
: 0x2c24 (SPI_SHADER_USER_DATA_PS_24
)
383 // CHECK
: 0x2c25 (SPI_SHADER_USER_DATA_PS_25
)
384 // CHECK
: 0x2c26 (SPI_SHADER_USER_DATA_PS_26
)
385 // CHECK
: 0x2c27 (SPI_SHADER_USER_DATA_PS_27
)
386 // CHECK
: 0x2c28 (SPI_SHADER_USER_DATA_PS_28
)
387 // CHECK
: 0x2c29 (SPI_SHADER_USER_DATA_PS_29
)
388 // CHECK
: 0x2c2a (SPI_SHADER_USER_DATA_PS_30
)
389 // CHECK
: 0x2c2b (SPI_SHADER_USER_DATA_PS_31
)
390 // CHECK
: 0x2c32 (SPI_SHADER_USER_ACCUM_PS_0
)
391 // CHECK
: 0x2c33 (SPI_SHADER_USER_ACCUM_PS_1
)
392 // CHECK
: 0x2c34 (SPI_SHADER_USER_ACCUM_PS_2
)
393 // CHECK
: 0x2c35 (SPI_SHADER_USER_ACCUM_PS_3
)
394 // CHECK
: 0x2c45 (SPI_SHADER_PGM_CHKSUM_VS
)
395 // CHECK
: 0x2c46 (SPI_SHADER_PGM_RSRC3_VS
)
396 // CHECK
: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS
)
397 // CHECK
: 0x2c4b (SPI_SHADER_PGM_RSRC2_VS
)
398 // CHECK
: 0x2c4c (SPI_SHADER_USER_DATA_VS_0
)
399 // CHECK
: 0x2c4d (SPI_SHADER_USER_DATA_VS_1
)
400 // CHECK
: 0x2c4e (SPI_SHADER_USER_DATA_VS_2
)
401 // CHECK
: 0x2c4f (SPI_SHADER_USER_DATA_VS_3
)
402 // CHECK
: 0x2c50 (SPI_SHADER_USER_DATA_VS_4
)
403 // CHECK
: 0x2c51 (SPI_SHADER_USER_DATA_VS_5
)
404 // CHECK
: 0x2c52 (SPI_SHADER_USER_DATA_VS_6
)
405 // CHECK
: 0x2c53 (SPI_SHADER_USER_DATA_VS_7
)
406 // CHECK
: 0x2c54 (SPI_SHADER_USER_DATA_VS_8
)
407 // CHECK
: 0x2c55 (SPI_SHADER_USER_DATA_VS_9
)
408 // CHECK
: 0x2c56 (SPI_SHADER_USER_DATA_VS_10
)
409 // CHECK
: 0x2c57 (SPI_SHADER_USER_DATA_VS_11
)
410 // CHECK
: 0x2c58 (SPI_SHADER_USER_DATA_VS_12
)
411 // CHECK
: 0x2c59 (SPI_SHADER_USER_DATA_VS_13
)
412 // CHECK
: 0x2c5a (SPI_SHADER_USER_DATA_VS_14
)
413 // CHECK
: 0x2c5b (SPI_SHADER_USER_DATA_VS_15
)
414 // CHECK
: 0x2c5c (SPI_SHADER_USER_DATA_VS_16
)
415 // CHECK
: 0x2c5d (SPI_SHADER_USER_DATA_VS_17
)
416 // CHECK
: 0x2c5e (SPI_SHADER_USER_DATA_VS_18
)
417 // CHECK
: 0x2c5f (SPI_SHADER_USER_DATA_VS_19
)
418 // CHECK
: 0x2c60 (SPI_SHADER_USER_DATA_VS_20
)
419 // CHECK
: 0x2c61 (SPI_SHADER_USER_DATA_VS_21
)
420 // CHECK
: 0x2c62 (SPI_SHADER_USER_DATA_VS_22
)
421 // CHECK
: 0x2c63 (SPI_SHADER_USER_DATA_VS_23
)
422 // CHECK
: 0x2c64 (SPI_SHADER_USER_DATA_VS_24
)
423 // CHECK
: 0x2c65 (SPI_SHADER_USER_DATA_VS_25
)
424 // CHECK
: 0x2c66 (SPI_SHADER_USER_DATA_VS_26
)
425 // CHECK
: 0x2c67 (SPI_SHADER_USER_DATA_VS_27
)
426 // CHECK
: 0x2c68 (SPI_SHADER_USER_DATA_VS_28
)
427 // CHECK
: 0x2c69 (SPI_SHADER_USER_DATA_VS_29
)
428 // CHECK
: 0x2c6a (SPI_SHADER_USER_DATA_VS_30
)
429 // CHECK
: 0x2c6b (SPI_SHADER_USER_DATA_VS_31
)
430 // CHECK
: 0x2c72 (SPI_SHADER_USER_ACCUM_VS_0
)
431 // CHECK
: 0x2c73 (SPI_SHADER_USER_ACCUM_VS_1
)
432 // CHECK
: 0x2c74 (SPI_SHADER_USER_ACCUM_VS_2
)
433 // CHECK
: 0x2c75 (SPI_SHADER_USER_ACCUM_VS_3
)
434 // CHECK
: 0x2c80 (SPI_SHADER_PGM_CHKSUM_GS
)
435 // CHECK
: 0x2c81 (SPI_SHADER_PGM_RSRC4_GS
)
436 // CHECK
: 0x2c87 (SPI_SHADER_PGM_RSRC3_GS
)
437 // CHECK
: 0x2c88 (SPI_SHADER_PGM_LO_GS
)
438 // CHECK
: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS
)
439 // CHECK
: 0x2c8b (SPI_SHADER_PGM_RSRC2_GS
)
440 // CHECK
: 0x2c8c (SPI_SHADER_USER_DATA_GS_0
)
441 // CHECK
: 0x2c8d (SPI_SHADER_USER_DATA_GS_1
)
442 // CHECK
: 0x2c8e (SPI_SHADER_USER_DATA_GS_2
)
443 // CHECK
: 0x2c8f (SPI_SHADER_USER_DATA_GS_3
)
444 // CHECK
: 0x2c90 (SPI_SHADER_USER_DATA_GS_4
)
445 // CHECK
: 0x2c91 (SPI_SHADER_USER_DATA_GS_5
)
446 // CHECK
: 0x2c92 (SPI_SHADER_USER_DATA_GS_6
)
447 // CHECK
: 0x2c93 (SPI_SHADER_USER_DATA_GS_7
)
448 // CHECK
: 0x2c94 (SPI_SHADER_USER_DATA_GS_8
)
449 // CHECK
: 0x2c95 (SPI_SHADER_USER_DATA_GS_9
)
450 // CHECK
: 0x2c96 (SPI_SHADER_USER_DATA_GS_10
)
451 // CHECK
: 0x2c97 (SPI_SHADER_USER_DATA_GS_11
)
452 // CHECK
: 0x2c98 (SPI_SHADER_USER_DATA_GS_12
)
453 // CHECK
: 0x2c99 (SPI_SHADER_USER_DATA_GS_13
)
454 // CHECK
: 0x2c9a (SPI_SHADER_USER_DATA_GS_14
)
455 // CHECK
: 0x2c9b (SPI_SHADER_USER_DATA_GS_15
)
456 // CHECK
: 0x2c9c (SPI_SHADER_USER_DATA_GS_16
)
457 // CHECK
: 0x2c9d (SPI_SHADER_USER_DATA_GS_17
)
458 // CHECK
: 0x2c9e (SPI_SHADER_USER_DATA_GS_18
)
459 // CHECK
: 0x2c9f (SPI_SHADER_USER_DATA_GS_19
)
460 // CHECK
: 0x2ca0 (SPI_SHADER_USER_DATA_GS_20
)
461 // CHECK
: 0x2ca1 (SPI_SHADER_USER_DATA_GS_21
)
462 // CHECK
: 0x2ca2 (SPI_SHADER_USER_DATA_GS_22
)
463 // CHECK
: 0x2ca3 (SPI_SHADER_USER_DATA_GS_23
)
464 // CHECK
: 0x2ca4 (SPI_SHADER_USER_DATA_GS_24
)
465 // CHECK
: 0x2ca5 (SPI_SHADER_USER_DATA_GS_25
)
466 // CHECK
: 0x2ca6 (SPI_SHADER_USER_DATA_GS_26
)
467 // CHECK
: 0x2ca7 (SPI_SHADER_USER_DATA_GS_27
)
468 // CHECK
: 0x2ca8 (SPI_SHADER_USER_DATA_GS_28
)
469 // CHECK
: 0x2ca9 (SPI_SHADER_USER_DATA_GS_29
)
470 // CHECK
: 0x2caa (SPI_SHADER_USER_DATA_GS_30
)
471 // CHECK
: 0x2cab (SPI_SHADER_USER_DATA_GS_31
)
472 // CHECK
: 0x2cb2 (SPI_SHADER_USER_ACCUM_ESGS_0
)
473 // CHECK
: 0x2cb3 (SPI_SHADER_USER_ACCUM_ESGS_1
)
474 // CHECK
: 0x2cb4 (SPI_SHADER_USER_ACCUM_ESGS_2
)
475 // CHECK
: 0x2cb5 (SPI_SHADER_USER_ACCUM_ESGS_3
)
476 // CHECK
: 0x2cc7 (SPI_SHADER_PGM_RSRC3_ES
)
477 // CHECK
: 0x2cca (SPI_SHADER_PGM_RSRC1_ES
)
478 // CHECK
: 0x2ccb (SPI_SHADER_PGM_RSRC2_ES
)
479 // CHECK
: 0x2ccc (SPI_SHADER_USER_DATA_ES_0
)
480 // CHECK
: 0x2ccd (SPI_SHADER_USER_DATA_ES_1
)
481 // CHECK
: 0x2cce (SPI_SHADER_USER_DATA_ES_2
)
482 // CHECK
: 0x2ccf (SPI_SHADER_USER_DATA_ES_3
)
483 // CHECK
: 0x2cd0 (SPI_SHADER_USER_DATA_ES_4
)
484 // CHECK
: 0x2cd1 (SPI_SHADER_USER_DATA_ES_5
)
485 // CHECK
: 0x2cd2 (SPI_SHADER_USER_DATA_ES_6
)
486 // CHECK
: 0x2cd3 (SPI_SHADER_USER_DATA_ES_7
)
487 // CHECK
: 0x2cd4 (SPI_SHADER_USER_DATA_ES_8
)
488 // CHECK
: 0x2cd5 (SPI_SHADER_USER_DATA_ES_9
)
489 // CHECK
: 0x2cd6 (SPI_SHADER_USER_DATA_ES_10
)
490 // CHECK
: 0x2cd7 (SPI_SHADER_USER_DATA_ES_11
)
491 // CHECK
: 0x2cd8 (SPI_SHADER_USER_DATA_ES_12
)
492 // CHECK
: 0x2cd9 (SPI_SHADER_USER_DATA_ES_13
)
493 // CHECK
: 0x2cda (SPI_SHADER_USER_DATA_ES_14
)
494 // CHECK
: 0x2cdb (SPI_SHADER_USER_DATA_ES_15
)
495 // CHECK
: 0x2cdc (SPI_SHADER_USER_DATA_ES_16
)
496 // CHECK
: 0x2cdd (SPI_SHADER_USER_DATA_ES_17
)
497 // CHECK
: 0x2cde (SPI_SHADER_USER_DATA_ES_18
)
498 // CHECK
: 0x2cdf (SPI_SHADER_USER_DATA_ES_19
)
499 // CHECK
: 0x2ce0 (SPI_SHADER_USER_DATA_ES_20
)
500 // CHECK
: 0x2ce1 (SPI_SHADER_USER_DATA_ES_21
)
501 // CHECK
: 0x2ce2 (SPI_SHADER_USER_DATA_ES_22
)
502 // CHECK
: 0x2ce3 (SPI_SHADER_USER_DATA_ES_23
)
503 // CHECK
: 0x2ce4 (SPI_SHADER_USER_DATA_ES_24
)
504 // CHECK
: 0x2ce5 (SPI_SHADER_USER_DATA_ES_25
)
505 // CHECK
: 0x2ce6 (SPI_SHADER_USER_DATA_ES_26
)
506 // CHECK
: 0x2ce7 (SPI_SHADER_USER_DATA_ES_27
)
507 // CHECK
: 0x2ce8 (SPI_SHADER_USER_DATA_ES_28
)
508 // CHECK
: 0x2ce9 (SPI_SHADER_USER_DATA_ES_29
)
509 // CHECK
: 0x2cea (SPI_SHADER_USER_DATA_ES_30
)
510 // CHECK
: 0x2ceb (SPI_SHADER_USER_DATA_ES_31
)
511 // CHECK
: 0x2d00 (SPI_SHADER_PGM_CHKSUM_HS
)
512 // CHECK
: 0x2d07 (SPI_SHADER_PGM_RSRC3_HS
)
513 // CHECK
: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS
)
514 // CHECK
: 0x2d0b (SPI_SHADER_PGM_RSRC2_HS
)
515 // CHECK
: 0x2d0c (SPI_SHADER_USER_DATA_HS_0
)
516 // CHECK
: 0x2d0d (SPI_SHADER_USER_DATA_HS_1
)
517 // CHECK
: 0x2d0e (SPI_SHADER_USER_DATA_HS_2
)
518 // CHECK
: 0x2d0f (SPI_SHADER_USER_DATA_HS_3
)
519 // CHECK
: 0x2d10 (SPI_SHADER_USER_DATA_HS_4
)
520 // CHECK
: 0x2d11 (SPI_SHADER_USER_DATA_HS_5
)
521 // CHECK
: 0x2d12 (SPI_SHADER_USER_DATA_HS_6
)
522 // CHECK
: 0x2d13 (SPI_SHADER_USER_DATA_HS_7
)
523 // CHECK
: 0x2d14 (SPI_SHADER_USER_DATA_HS_8
)
524 // CHECK
: 0x2d15 (SPI_SHADER_USER_DATA_HS_9
)
525 // CHECK
: 0x2d16 (SPI_SHADER_USER_DATA_HS_10
)
526 // CHECK
: 0x2d17 (SPI_SHADER_USER_DATA_HS_11
)
527 // CHECK
: 0x2d18 (SPI_SHADER_USER_DATA_HS_12
)
528 // CHECK
: 0x2d19 (SPI_SHADER_USER_DATA_HS_13
)
529 // CHECK
: 0x2d1a (SPI_SHADER_USER_DATA_HS_14
)
530 // CHECK
: 0x2d1b (SPI_SHADER_USER_DATA_HS_15
)
531 // CHECK
: 0x2d1c (SPI_SHADER_USER_DATA_HS_16
)
532 // CHECK
: 0x2d1d (SPI_SHADER_USER_DATA_HS_17
)
533 // CHECK
: 0x2d1e (SPI_SHADER_USER_DATA_HS_18
)
534 // CHECK
: 0x2d1f (SPI_SHADER_USER_DATA_HS_19
)
535 // CHECK
: 0x2d20 (SPI_SHADER_USER_DATA_HS_20
)
536 // CHECK
: 0x2d21 (SPI_SHADER_USER_DATA_HS_21
)
537 // CHECK
: 0x2d22 (SPI_SHADER_USER_DATA_HS_22
)
538 // CHECK
: 0x2d23 (SPI_SHADER_USER_DATA_HS_23
)
539 // CHECK
: 0x2d24 (SPI_SHADER_USER_DATA_HS_24
)
540 // CHECK
: 0x2d25 (SPI_SHADER_USER_DATA_HS_25
)
541 // CHECK
: 0x2d26 (SPI_SHADER_USER_DATA_HS_26
)
542 // CHECK
: 0x2d27 (SPI_SHADER_USER_DATA_HS_27
)
543 // CHECK
: 0x2d28 (SPI_SHADER_USER_DATA_HS_28
)
544 // CHECK
: 0x2d29 (SPI_SHADER_USER_DATA_HS_29
)
545 // CHECK
: 0x2d2a (SPI_SHADER_USER_DATA_HS_30
)
546 // CHECK
: 0x2d2b (SPI_SHADER_USER_DATA_HS_31
)
547 // CHECK
: 0x2d32 (SPI_SHADER_USER_ACCUM_LSHS_0
)
548 // CHECK
: 0x2d33 (SPI_SHADER_USER_ACCUM_LSHS_1
)
549 // CHECK
: 0x2d34 (SPI_SHADER_USER_ACCUM_LSHS_2
)
550 // CHECK
: 0x2d35 (SPI_SHADER_USER_ACCUM_LSHS_3
)
551 // CHECK
: 0x2d47 (SPI_SHADER_PGM_RSRC3_LS
)
552 // CHECK
: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS
)
553 // CHECK
: 0x2d4b (SPI_SHADER_PGM_RSRC2_LS
)
554 // CHECK
: 0x2d4c (SPI_SHADER_USER_DATA_LS_0
)
555 // CHECK
: 0x2d4d (SPI_SHADER_USER_DATA_LS_1
)
556 // CHECK
: 0x2d4e (SPI_SHADER_USER_DATA_LS_2
)
557 // CHECK
: 0x2d4f (SPI_SHADER_USER_DATA_LS_3
)
558 // CHECK
: 0x2d50 (SPI_SHADER_USER_DATA_LS_4
)
559 // CHECK
: 0x2d51 (SPI_SHADER_USER_DATA_LS_5
)
560 // CHECK
: 0x2d52 (SPI_SHADER_USER_DATA_LS_6
)
561 // CHECK
: 0x2d53 (SPI_SHADER_USER_DATA_LS_7
)
562 // CHECK
: 0x2d54 (SPI_SHADER_USER_DATA_LS_8
)
563 // CHECK
: 0x2d55 (SPI_SHADER_USER_DATA_LS_9
)
564 // CHECK
: 0x2d56 (SPI_SHADER_USER_DATA_LS_10
)
565 // CHECK
: 0x2d57 (SPI_SHADER_USER_DATA_LS_11
)
566 // CHECK
: 0x2d58 (SPI_SHADER_USER_DATA_LS_12
)
567 // CHECK
: 0x2d59 (SPI_SHADER_USER_DATA_LS_13
)
568 // CHECK
: 0x2d5a (SPI_SHADER_USER_DATA_LS_14
)
569 // CHECK
: 0x2d5b (SPI_SHADER_USER_DATA_LS_15
)
570 // CHECK
: 0x2e00 (COMPUTE_DISPATCH_INITIATOR
)
571 // CHECK
: 0x2e07 (COMPUTE_NUM_THREAD_X
)
572 // CHECK
: 0x2e08 (COMPUTE_NUM_THREAD_Y
)
573 // CHECK
: 0x2e09 (COMPUTE_NUM_THREAD_Z
)
574 // CHECK
: 0x2e12 (COMPUTE_PGM_RSRC1
)
575 // CHECK
: 0x2e13 (COMPUTE_PGM_RSRC2
)
576 // CHECK
: 0x2e18 (COMPUTE_TMPRING_SIZE
)
577 // CHECK
: 0x2e24 (COMPUTE_USER_ACCUM_0
)
578 // CHECK
: 0x2e25 (COMPUTE_USER_ACCUM_1
)
579 // CHECK
: 0x2e26 (COMPUTE_USER_ACCUM_2
)
580 // CHECK
: 0x2e27 (COMPUTE_USER_ACCUM_3
)
581 // CHECK
: 0x2e28 (COMPUTE_PGM_RSRC3
)
582 // CHECK
: 0x2e2a (COMPUTE_SHADER_CHKSUM
)
583 // CHECK
: 0x2e40 (COMPUTE_USER_DATA_0
)
584 // CHECK
: 0x2e41 (COMPUTE_USER_DATA_1
)
585 // CHECK
: 0x2e42 (COMPUTE_USER_DATA_2
)
586 // CHECK
: 0x2e43 (COMPUTE_USER_DATA_3
)
587 // CHECK
: 0x2e44 (COMPUTE_USER_DATA_4
)
588 // CHECK
: 0x2e45 (COMPUTE_USER_DATA_5
)
589 // CHECK
: 0x2e46 (COMPUTE_USER_DATA_6
)
590 // CHECK
: 0x2e47 (COMPUTE_USER_DATA_7
)
591 // CHECK
: 0x2e48 (COMPUTE_USER_DATA_8
)
592 // CHECK
: 0x2e49 (COMPUTE_USER_DATA_9
)
593 // CHECK
: 0x2e4a (COMPUTE_USER_DATA_10
)
594 // CHECK
: 0x2e4b (COMPUTE_USER_DATA_11
)
595 // CHECK
: 0x2e4c (COMPUTE_USER_DATA_12
)
596 // CHECK
: 0x2e4d (COMPUTE_USER_DATA_13
)
597 // CHECK
: 0x2e4e (COMPUTE_USER_DATA_14
)
598 // CHECK
: 0x2e4f (COMPUTE_USER_DATA_15
)
599 // CHECK
: 0xa08f (CB_SHADER_MASK
)
600 // CHECK
: 0xa191 (SPI_PS_INPUT_CNTL_0
)
601 // CHECK
: 0xa192 (SPI_PS_INPUT_CNTL_1
)
602 // CHECK
: 0xa193 (SPI_PS_INPUT_CNTL_2
)
603 // CHECK
: 0xa194 (SPI_PS_INPUT_CNTL_3
)
604 // CHECK
: 0xa195 (SPI_PS_INPUT_CNTL_4
)
605 // CHECK
: 0xa196 (SPI_PS_INPUT_CNTL_5
)
606 // CHECK
: 0xa197 (SPI_PS_INPUT_CNTL_6
)
607 // CHECK
: 0xa198 (SPI_PS_INPUT_CNTL_7
)
608 // CHECK
: 0xa199 (SPI_PS_INPUT_CNTL_8
)
609 // CHECK
: 0xa19a (SPI_PS_INPUT_CNTL_9
)
610 // CHECK
: 0xa19b (SPI_PS_INPUT_CNTL_10
)
611 // CHECK
: 0xa19c (SPI_PS_INPUT_CNTL_11
)
612 // CHECK
: 0xa19d (SPI_PS_INPUT_CNTL_12
)
613 // CHECK
: 0xa19e (SPI_PS_INPUT_CNTL_13
)
614 // CHECK
: 0xa19f (SPI_PS_INPUT_CNTL_14
)
615 // CHECK
: 0xa1a0 (SPI_PS_INPUT_CNTL_15
)
616 // CHECK
: 0xa1a1 (SPI_PS_INPUT_CNTL_16
)
617 // CHECK
: 0xa1a2 (SPI_PS_INPUT_CNTL_17
)
618 // CHECK
: 0xa1a3 (SPI_PS_INPUT_CNTL_18
)
619 // CHECK
: 0xa1a4 (SPI_PS_INPUT_CNTL_19
)
620 // CHECK
: 0xa1a5 (SPI_PS_INPUT_CNTL_20
)
621 // CHECK
: 0xa1a6 (SPI_PS_INPUT_CNTL_21
)
622 // CHECK
: 0xa1a7 (SPI_PS_INPUT_CNTL_22
)
623 // CHECK
: 0xa1a8 (SPI_PS_INPUT_CNTL_23
)
624 // CHECK
: 0xa1a9 (SPI_PS_INPUT_CNTL_24
)
625 // CHECK
: 0xa1aa (SPI_PS_INPUT_CNTL_25
)
626 // CHECK
: 0xa1ab (SPI_PS_INPUT_CNTL_26
)
627 // CHECK
: 0xa1ac (SPI_PS_INPUT_CNTL_27
)
628 // CHECK
: 0xa1ad (SPI_PS_INPUT_CNTL_28
)
629 // CHECK
: 0xa1ae (SPI_PS_INPUT_CNTL_29
)
630 // CHECK
: 0xa1af (SPI_PS_INPUT_CNTL_30
)
631 // CHECK
: 0xa1b0 (SPI_PS_INPUT_CNTL_31
)
632 // CHECK
: 0xa1b1 (SPI_VS_OUT_CONFIG
)
633 // CHECK
: 0xa1b3 (SPI_PS_INPUT_ENA
)
634 // CHECK
: 0xa1b4 (SPI_PS_INPUT_ADDR
)
635 // CHECK
: 0xa1b5 (SPI_INTERP_CONTROL_0
)
636 // CHECK
: 0xa1b6 (SPI_PS_IN_CONTROL
)
637 // CHECK
: 0xa1b8 (SPI_BARYC_CNTL
)
638 // CHECK
: 0xa1ba (SPI_TMPRING_SIZE
)
639 // CHECK
: 0xa1c2 (SPI_SHADER_IDX_FORMAT
)
640 // CHECK
: 0xa1c3 (SPI_SHADER_POS_FORMAT
)
641 // CHECK
: 0xa1c4 (SPI_SHADER_Z_FORMAT
)
642 // CHECK
: 0xa1c5 (SPI_SHADER_COL_FORMAT
)
643 // CHECK
: 0xa1ff (GE_MAX_OUTPUT_PER_SUBGROUP
)
644 // CHECK
: 0xa203 (DB_SHADER_CONTROL
)
645 // CHECK
: 0xa204 (PA_CL_CLIP_CNTL
)
646 // CHECK
: 0xa206 (PA_CL_VTE_CNTL
)
647 // CHECK
: 0xa207 (PA_CL_VS_OUT_CNTL
)
648 // CHECK
: 0xa210 (PA_STEREO_CNTL
)
649 // CHECK
: 0xa286 (VGT_HOS_MAX_TESS_LEVEL
)
650 // CHECK
: 0xa287 (VGT_HOS_MIN_TESS_LEVEL
)
651 // CHECK
: 0xa290 (VGT_GS_MODE
)
652 // CHECK
: 0xa291 (VGT_GS_ONCHIP_CNTL
)
653 // CHECK
: 0xa293 (PA_SC_MODE_CNTL_1
)
654 // CHECK
: 0xa297 (VGT_GS_PER_VS
)
655 // CHECK
: 0xa298 (VGT_GSVS_RING_OFFSET_1
)
656 // CHECK
: 0xa299 (VGT_GSVS_RING_OFFSET_2
)
657 // CHECK
: 0xa29a (VGT_GSVS_RING_OFFSET_3
)
658 // CHECK
: 0xa29b (VGT_GS_OUT_PRIM_TYPE
)
659 // CHECK
: 0xa2a1 (VGT_PRIMITIVEID_EN
)
660 // CHECK
: 0xa2a5 (VGT_GS_MAX_PRIMS_PER_SUBGROUP
)
661 // CHECK
: 0xa2aa (IA_MULTI_VGT_PARAM
)
662 // CHECK
: 0xa2ab (VGT_ESGS_RING_ITEMSIZE
)
663 // CHECK
: 0xa2ac (VGT_GSVS_RING_ITEMSIZE
)
664 // CHECK
: 0xa2ad (VGT_REUSE_OFF
)
665 // CHECK
: 0xa2b5 (VGT_STRMOUT_VTX_STRIDE_0
)
666 // CHECK
: 0xa2b9 (VGT_STRMOUT_VTX_STRIDE_1
)
667 // CHECK
: 0xa2bd (VGT_STRMOUT_VTX_STRIDE_2
)
668 // CHECK
: 0xa2c1 (VGT_STRMOUT_VTX_STRIDE_3
)
669 // CHECK
: 0xa2ce (VGT_GS_MAX_VERT_OUT
)
670 // CHECK
: 0xa2d3 (GE_NGG_SUBGRP_CNTL
)
671 // CHECK
: 0xa2d5 (VGT_SHADER_STAGES_EN
)
672 // CHECK
: 0xa2d6 (VGT_LS_HS_CONFIG
)
673 // CHECK
: 0xa2d7 (VGT_GS_VERT_ITEMSIZE
)
674 // CHECK
: 0xa2d8 (VGT_GS_VERT_ITEMSIZE_1
)
675 // CHECK
: 0xa2d9 (VGT_GS_VERT_ITEMSIZE_2
)
676 // CHECK
: 0xa2da (VGT_GS_VERT_ITEMSIZE_3
)
677 // CHECK
: 0xa2db (VGT_TF_PARAM
)
678 // CHECK
: 0xa2e4 (VGT_GS_INSTANCE_CNT
)
679 // CHECK
: 0xa2e5 (VGT_STRMOUT_CONFIG
)
680 // CHECK
: 0xa2e6 (VGT_STRMOUT_BUFFER_CONFIG
)
681 // CHECK
: 0xa2f8 (PA_SC_AA_CONFIG
)
682 // CHECK
: 0xa2f9 (PA_SU_VTX_CNTL
)
683 // CHECK
: 0xa310 (PA_SC_SHADER_CONTROL
)
684 // CHECK
: 0xa313 (PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
)
685 // CHECK
: 0xa316 (VGT_VERTEX_REUSE_BLOCK_CNTL
)
686 // CHECK
: 0xc258 (IA_MULTI_VGT_PARAM_PIPED
)
687 // CHECK
: 0xc25f (GE_STEREO_CNTL
)
688 // CHECK
: 0xc262 (GE_USER_VGPR_EN
)
