llvm/test/MC/AMDGPU/sopk-err.s

   1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=SICI %s
   2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck --check-prefix=SICI %s
   3 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck --check-prefix=VI %s
   4 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
   5 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
   6
   7 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
   8 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
   9 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefixes=GCN,SICIVI-ERR --implicit-check-not=error: %s
  10 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX9-ERR --implicit-check-not=error: %s
  11 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefixes=GCN,GFX10-ERR --implicit-check-not=error: %s
  12
  13 s_setreg_b32  0x1f803, s2
  14 // GCN: error: invalid immediate: only 16-bit values are legal
  15
  16 s_setreg_b32  typo(0x40), s2
  17 // GCN: error: expected a hwreg macro or an absolute expression
  18
  19 s_setreg_b32  hwreg(0x40), s2
  20 // GCN: error: invalid code of hardware register: only 6-bit values are legal
  21
  22 s_setreg_b32  hwreg(HW_REG_WRONG), s2
  23 // GCN: error: expected a register name or an absolute expression
  24
  25 s_setreg_b32  hwreg(1 2,3), s2
  26 // GCN: error: expected a comma or a closing parenthesis
  27
  28 s_setreg_b32  hwreg(1,2 3), s2
  29 // GCN: error: expected a comma
  30
  31 s_setreg_b32  hwreg(1,2,3, s2
  32 // GCN: error: expected a closing parenthesis
  33
  34 s_setreg_b32  hwreg(3,32,32), s2
  35 // GCN: error: invalid bit offset: only 5-bit values are legal
  36
  37 s_setreg_b32  hwreg(3,0,33), s2
  38 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
  39
  40 s_setreg_imm32_b32  0x1f803, 0xff
  41 // GCN: error: invalid immediate: only 16-bit values are legal
  42
  43 s_setreg_imm32_b32  hwreg(3,0,33), 0xff
  44 // GCN: error: invalid bitfield width: only values from 1 to 32 are legal
  45
  46 s_getreg_b32  s2, hwreg(3,32,32)
  47 // GCN: error: invalid bit offset: only 5-bit values are legal
  48
  49 s_cbranch_i_fork s[2:3], 0x6
  50 // SICI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x82,0xb8]
  51 // GFX10-ERR: error: instruction not supported on this GPU
  52 // GFX9: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
  53 // VI: s_cbranch_i_fork s[2:3], 6 ; encoding: [0x06,0x00,0x02,0xb8]
  54
  55 s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
  56 // GFX10:  s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x02,0xb9]
  57 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  58 // GFX9: s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES) ; encoding: [0x0f,0xf8,0x82,0xb8]
  59
  60 s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
  61 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
  62 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  63 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  64
  65 s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
  66 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
  67 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  68 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  69
  70 s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
  71 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
  72 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  73 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  74
  75 s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
  76 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
  77 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  78 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  79
  80 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
  81 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
  82 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  83 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  84
  85 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI)
  86 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_HI) ; encoding: [0x15,0xf8,0x02,0xb9]
  87 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  88 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  89
  90 s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK)
  91 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x16,0xf8,0x02,0xb9]
  92 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  93 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  94
  95 s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER)
  96 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_POPS_PACKER) ; encoding: [0x19,0xf8,0x02,0xb9]
  97 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
  98 // GFX9-ERR: error: specified hardware register is not supported on this GPU
  99
 100 s_cmpk_le_u32 s2, -1
 101 // GCN: error: invalid operand for instruction
 102
 103 s_cmpk_le_u32 s2, 0x1ffff
 104 // GCN: error: invalid operand for instruction
 105
 106 s_cmpk_le_u32 s2, 0x10000
 107 // GCN: error: invalid operand for instruction
 108
 109 s_mulk_i32 s2, 0xFFFFFFFFFFFF0000
 110 // GCN: error: invalid operand for instruction
 111
 112 s_mulk_i32 s2, 0x10000
 113 // GCN: error: invalid operand for instruction