llvm/test/MC/AMDGPU/trap.s

   1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
   2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
   3 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
   4 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
   5
   6 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
   7 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
   8 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI --implicit-check-not=error:
   9 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck %s --check-prefix=NOGFX9 --implicit-check-not=error:
  10
  11 //===----------------------------------------------------------------------===//
  12 // Trap Handler related - 32 bit registers
  13 //===----------------------------------------------------------------------===//
  14
  15 s_add_u32     ttmp0, ttmp0, 4
  16 // SICI: s_add_u32 ttmp0, ttmp0, 4       ; encoding: [0x70,0x84,0x70,0x80]
  17 // VI:   s_add_u32 ttmp0, ttmp0, 4       ; encoding: [0x70,0x84,0x70,0x80]
  18 // GFX9: s_add_u32 ttmp0, ttmp0, 4       ; encoding: [0x6c,0x84,0x6c,0x80]
  19
  20 s_add_u32     ttmp4, 8, ttmp4
  21 // SICI: s_add_u32 ttmp4, 8, ttmp4       ; encoding: [0x88,0x74,0x74,0x80]
  22 // VI:   s_add_u32 ttmp4, 8, ttmp4       ; encoding: [0x88,0x74,0x74,0x80]
  23 // GFX9: s_add_u32 ttmp4, 8, ttmp4       ; encoding: [0x88,0x70,0x70,0x80]
  24
  25 s_add_u32     ttmp4, ttmp4, 0x00000100
  26 // SICI: s_add_u32 ttmp4, ttmp4, 0x100   ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
  27 // VI:   s_add_u32 ttmp4, ttmp4, 0x100   ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
  28 // GFX9: s_add_u32 ttmp4, ttmp4, 0x100   ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
  29
  30 s_add_u32     ttmp4, ttmp4, 4
  31 // SICI: s_add_u32 ttmp4, ttmp4, 4       ; encoding: [0x74,0x84,0x74,0x80]
  32 // VI:   s_add_u32 ttmp4, ttmp4, 4       ; encoding: [0x74,0x84,0x74,0x80]
  33 // GFX9: s_add_u32 ttmp4, ttmp4, 4       ; encoding: [0x70,0x84,0x70,0x80]
  34
  35 s_add_u32     ttmp4, ttmp8, ttmp4
  36 // SICI: s_add_u32 ttmp4, ttmp8, ttmp4   ; encoding: [0x78,0x74,0x74,0x80]
  37 // VI:   s_add_u32 ttmp4, ttmp8, ttmp4   ; encoding: [0x78,0x74,0x74,0x80]
  38 // GFX9: s_add_u32 ttmp4, ttmp8, ttmp4   ; encoding: [0x74,0x70,0x70,0x80]
  39
  40 s_and_b32     ttmp10, ttmp8, 0x00000080
  41 // SICI: s_and_b32 ttmp10, ttmp8, 0x80   ; encoding: [0x78,0xff,0x7a,0x87,0x80,0x00,0x00,0x00]
  42 // VI:   s_and_b32 ttmp10, ttmp8, 0x80   ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
  43 // GFX9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00]
  44
  45 s_and_b32     ttmp9, tma_hi, 0x0000ffff
  46 // SICI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x87,0xff,0xff,0x00,0x00]
  47 // VI:   s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
  48 // NOGFX9: error: register not available on this GPU
  49
  50 s_and_b32     ttmp9, ttmp9, 0x000001ff
  51 // SICI: s_and_b32 ttmp9, ttmp9, 0x1ff   ; encoding: [0x79,0xff,0x79,0x87,0xff,0x01,0x00,0x00]
  52 // VI:   s_and_b32 ttmp9, ttmp9, 0x1ff   ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
  53 // GFX9: s_and_b32 ttmp9, ttmp9, 0x1ff   ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
  54
  55 s_and_b32     ttmp9, tma_lo, 0xffff0000
  56 // SICI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x87,0x00,0x00,0xff,0xff]
  57 // VI:   s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
  58 // NOGFX9: error: register not available on this GPU
  59
  60 s_and_b32     ttmp9, ttmp9, ttmp8
  61 // SICI: s_and_b32 ttmp9, ttmp9, ttmp8   ; encoding: [0x79,0x78,0x79,0x87]
  62 // VI:   s_and_b32 ttmp9, ttmp9, ttmp8   ; encoding: [0x79,0x78,0x79,0x86]
  63 // GFX9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x74,0x75,0x86]
  64
  65 s_and_b32   ttmp8, ttmp1, 0x01000000
  66 // SICI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x87,0x00,0x00,0x00,0x01]
  67 // VI:   s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
  68 // GFX9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
  69
  70 s_cmp_eq_i32  ttmp8, 0
  71 // SICI: s_cmp_eq_i32 ttmp8, 0           ; encoding: [0x78,0x80,0x00,0xbf]
  72 // VI:   s_cmp_eq_i32 ttmp8, 0           ; encoding: [0x78,0x80,0x00,0xbf]
  73 // GFX9: s_cmp_eq_i32 ttmp8, 0           ; encoding: [0x74,0x80,0x00,0xbf]
  74
  75 s_cmp_eq_i32  ttmp8, 0x000000fe
  76 // SICI: s_cmp_eq_i32 ttmp8, 0xfe        ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
  77 // VI:   s_cmp_eq_i32 ttmp8, 0xfe        ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
  78 // GFX9: s_cmp_eq_i32 ttmp8, 0xfe        ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
  79
  80 s_lshr_b32    ttmp8, ttmp8, 12
  81 // SICI: s_lshr_b32 ttmp8, ttmp8, 12     ; encoding: [0x78,0x8c,0x78,0x90]
  82 // VI:   s_lshr_b32 ttmp8, ttmp8, 12     ; encoding: [0x78,0x8c,0x78,0x8f]
  83 // GFX9: s_lshr_b32 ttmp8, ttmp8, 12     ; encoding: [0x74,0x8c,0x74,0x8f]
  84
  85 v_mov_b32_e32     v1, ttmp8
  86 // SICI: v_mov_b32_e32 v1, ttmp8         ; encoding: [0x78,0x02,0x02,0x7e]
  87 // VI:   v_mov_b32_e32 v1, ttmp8         ; encoding: [0x78,0x02,0x02,0x7e]
  88 // GFX9: v_mov_b32_e32 v1, ttmp8         ; encoding: [0x74,0x02,0x02,0x7e]
  89
  90 s_mov_b32     m0, ttmp8
  91 // SICI: s_mov_b32 m0, ttmp8             ; encoding: [0x78,0x03,0xfc,0xbe]
  92 // VI:   s_mov_b32 m0, ttmp8             ; encoding: [0x78,0x00,0xfc,0xbe]
  93 // GFX9: s_mov_b32 m0, ttmp8             ; encoding: [0x74,0x00,0xfc,0xbe]
  94
  95 s_mov_b32     ttmp10, 0
  96 // SICI: s_mov_b32 ttmp10, 0             ; encoding: [0x80,0x03,0xfa,0xbe]
  97 // VI:   s_mov_b32 ttmp10, 0             ; encoding: [0x80,0x00,0xfa,0xbe]
  98 // GFX9: s_mov_b32 ttmp10, 0             ; encoding: [0x80,0x00,0xf6,0xbe]
  99
 100 s_mov_b32     ttmp11, 0x01024fac
 101 // SICI: s_mov_b32 ttmp11, 0x1024fac     ; encoding: [0xff,0x03,0xfb,0xbe,0xac,0x4f,0x02,0x01]
 102 // VI:   s_mov_b32 ttmp11, 0x1024fac     ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
 103 // GFX9: s_mov_b32 ttmp11, 0x1024fac     ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
 104
 105 s_mov_b32     ttmp8, m0
 106 // SICI: s_mov_b32 ttmp8, m0             ; encoding: [0x7c,0x03,0xf8,0xbe]
 107 // VI:   s_mov_b32 ttmp8, m0             ; encoding: [0x7c,0x00,0xf8,0xbe]
 108 // GFX9: s_mov_b32 ttmp8, m0             ; encoding: [0x7c,0x00,0xf4,0xbe]
 109
 110 s_mov_b32     ttmp8, tma_lo
 111 // SICI: s_mov_b32 ttmp8, tma_lo         ; encoding: [0x6e,0x03,0xf8,0xbe]
 112 // VI:   s_mov_b32 ttmp8, tma_lo         ; encoding: [0x6e,0x00,0xf8,0xbe]
 113 // NOGFX9: error: register not available on this GPU
 114
 115 s_mul_i32     ttmp8, 0x00000324, ttmp8
 116 // SICI: s_mul_i32 ttmp8, 0x324, ttmp8   ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
 117 // VI:   s_mul_i32 ttmp8, 0x324, ttmp8   ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
 118 // GFX9: s_mul_i32 ttmp8, 0x324, ttmp8   ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
 119
 120 s_or_b32      ttmp9, ttmp9, 0x00280000
 121 // SICI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x88,0x00,0x00,0x28,0x00]
 122 // VI:   s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
 123 // GFX9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
 124
 125 // ttmp12..ttmp15 (GFX9 only)
 126
 127 s_add_u32     ttmp0, ttmp12, 4
 128 // NOSICIVI: error: register not available on this GPU
 129 // GFX9: s_add_u32 ttmp0, ttmp12, 4       ; encoding: [0x78,0x84,0x6c,0x80]
 130
 131 s_add_u32     ttmp0, ttmp13, 4
 132 // NOSICIVI: error: register not available on this GPU
 133 // GFX9: s_add_u32 ttmp0, ttmp13, 4       ; encoding: [0x79,0x84,0x6c,0x80]
 134
 135 s_add_u32     ttmp0, ttmp14, 4
 136 // NOSICIVI: error: register not available on this GPU
 137 // GFX9: s_add_u32 ttmp0, ttmp14, 4       ; encoding: [0x7a,0x84,0x6c,0x80]
 138
 139 s_add_u32     ttmp0, ttmp15, 4
 140 // NOSICIVI: error: register not available on this GPU
 141 // GFX9: s_add_u32 ttmp0, ttmp15, 4       ; encoding: [0x7b,0x84,0x6c,0x80]
 142
 143 //===----------------------------------------------------------------------===//
 144 // Trap Handler related - Pairs and quadruples of registers
 145 //===----------------------------------------------------------------------===//
 146
 147 s_mov_b64     ttmp[4:5], exec
 148 // SICI: s_mov_b64 ttmp[4:5], exec       ; encoding: [0x7e,0x04,0xf4,0xbe]
 149 // VI:   s_mov_b64 ttmp[4:5], exec       ; encoding: [0x7e,0x01,0xf4,0xbe]
 150 // GFX9: s_mov_b64 ttmp[4:5], exec       ; encoding: [0x7e,0x01,0xf0,0xbe]
 151
 152 s_mov_b64     [ttmp4,ttmp5], exec
 153 // SICI: s_mov_b64 ttmp[4:5], exec       ; encoding: [0x7e,0x04,0xf4,0xbe]
 154 // VI:   s_mov_b64 ttmp[4:5], exec       ; encoding: [0x7e,0x01,0xf4,0xbe]
 155 // GFX9: s_mov_b64 ttmp[4:5], exec       ; encoding: [0x7e,0x01,0xf0,0xbe]
 156
 157 s_mov_b64     exec, [ttmp4,ttmp5]
 158 // SICI: s_mov_b64 exec, ttmp[4:5]       ; encoding: [0x74,0x04,0xfe,0xbe]
 159 // VI:   s_mov_b64 exec, ttmp[4:5]       ; encoding: [0x74,0x01,0xfe,0xbe]
 160 // GFX9: s_mov_b64 exec, ttmp[4:5]       ; encoding: [0x70,0x01,0xfe,0xbe]
 161
 162 s_mov_b64     tba, ttmp[4:5]
 163 // SICI: s_mov_b64 tba, ttmp[4:5]        ; encoding: [0x74,0x04,0xec,0xbe]
 164 // VI:   s_mov_b64 tba, ttmp[4:5]        ; encoding: [0x74,0x01,0xec,0xbe]
 165 // NOGFX9: error: register not available on this GPU
 166
 167 s_mov_b64     ttmp[4:5], tba
 168 // SICI: s_mov_b64 ttmp[4:5], tba        ; encoding: [0x6c,0x04,0xf4,0xbe]
 169 // VI:   s_mov_b64 ttmp[4:5], tba        ; encoding: [0x6c,0x01,0xf4,0xbe]
 170 // NOGFX9: error: register not available on this GPU
 171
 172 s_mov_b64     tma, ttmp[4:5]
 173 // SICI: s_mov_b64 tma, ttmp[4:5]        ; encoding: [0x74,0x04,0xee,0xbe]
 174 // VI:   s_mov_b64 tma, ttmp[4:5]        ; encoding: [0x74,0x01,0xee,0xbe]
 175 // NOGFX9: error: register not available on this GPU
 176
 177 s_mov_b64     ttmp[4:5], tma
 178 // SICI: s_mov_b64 ttmp[4:5], tma        ; encoding: [0x6e,0x04,0xf4,0xbe]
 179 // VI:   s_mov_b64 ttmp[4:5], tma        ; encoding: [0x6e,0x01,0xf4,0xbe]
 180 // NOGFX9: error: register not available on this GPU
 181
 182 // ttmp12..ttmp15 (GFX9 only)
 183
 184 s_mov_b64     ttmp[12:13], exec
 185 // NOSICIVI: error: register not available on this GPU
 186 // GFX9: s_mov_b64 ttmp[12:13], exec       ; encoding: [0x7e,0x01,0xf8,0xbe]
 187
 188 s_mov_b64     ttmp[14:15], exec
 189 // NOSICIVI: error: register not available on this GPU
 190 // GFX9: s_mov_b64 ttmp[14:15], exec       ; encoding: [0x7e,0x01,0xfa,0xbe]
 191
 192 //===----------------------------------------------------------------------===//
 193 // Trap Handler related - 8-dword registers
 194 // NB: gfx7 doc states that SMRD does not support trap registers for dst
 195 //===----------------------------------------------------------------------===//
 196
 197 s_buffer_load_dwordx8 ttmp[0:7], s[0:3], s0
 198 // VI:   [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
 199 // GFX9: [0x00,0x1b,0x2c,0xc0,0x00,0x00,0x00,0x00]
 200 // SICI: s_buffer_load_dwordx8 ttmp[0:7], s[0:3], s0 ; encoding: [0x00,0x00,0xf8,0xc2]
 201
 202 s_buffer_load_dwordx8 ttmp[4:11], s[0:3], s0
 203 // VI:   [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
 204 // GFX9: [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
 205 // SICI: s_buffer_load_dwordx8 ttmp[4:11], s[0:3], s0 ; encoding: [0x00,0x00,0xfa,0xc2]
 206
 207 s_buffer_load_dwordx8 ttmp[8:15], s[0:3], s0
 208 // NOSICIVI: error: register not available on this GPU
 209 // GFX9: [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
 210
 211 s_load_dwordx8 ttmp[0:7], s[0:1], s0
 212 // VI:   [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
 213 // GFX9: [0x00,0x1b,0x0c,0xc0,0x00,0x00,0x00,0x00]
 214 // SICI: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x00,0xf8,0xc0]
 215
 216 s_load_dwordx8 ttmp[4:11], s[0:1], s0
 217 // VI:   [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
 218 // GFX9: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
 219 // SICI: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x00,0xfa,0xc0]
 220
 221 s_load_dwordx8 ttmp[8:15], s[0:1], s0
 222 // NOSICIVI: error: register not available on this GPU
 223 // GFX9: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
 224
 225 //===----------------------------------------------------------------------===//
 226 // Trap Handler related - 16-dword registers
 227 // NB: gfx7 doc states that SMRD does not support trap registers for dst
 228 //===----------------------------------------------------------------------===//
 229
 230 s_buffer_load_dwordx16 ttmp[0:15], s[0:3], s0
 231 // NOSICIVI: error: register not available on this GPU
 232 // GFX9: [0x00,0x1b,0x30,0xc0,0x00,0x00,0x00,0x00]
 233
 234 s_load_dwordx16 ttmp[0:15], s[0:1], s0
 235 // NOSICIVI: error: register not available on this GPU
 236 // GFX9: [0x00,0x1b,0x10,0xc0,0x00,0x00,0x00,0x00]
 237
 238 //===----------------------------------------------------------------------===//
 239 // Trap Handler related - Some specific instructions
 240 //===----------------------------------------------------------------------===//
 241
 242 s_setpc_b64   [ttmp2,ttmp3]
 243 // SICI: s_setpc_b64 ttmp[2:3]           ; encoding: [0x72,0x20,0x80,0xbe]
 244 // VI:   s_setpc_b64 ttmp[2:3]           ; encoding: [0x72,0x1d,0x80,0xbe]
 245 // GFX9: s_setpc_b64 ttmp[2:3]           ; encoding: [0x6e,0x1d,0x80,0xbe]
 246
 247 v_readfirstlane_b32  ttmp8, v1
 248 // SICI: v_readfirstlane_b32 ttmp8, v1   ; encoding: [0x01,0x05,0xf0,0x7e]
 249 // VI:   v_readfirstlane_b32 ttmp8, v1   ; encoding: [0x01,0x05,0xf0,0x7e]
 250 // GFX9: v_readfirstlane_b32 ttmp8, v1   ; encoding: [0x01,0x05,0xe8,0x7e]
 251
 252 buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
 253 // SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
 254 // VI:   buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
 255 // GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
 256
 257 // ttmp12..ttmp15 (GFX9 only)
 258
 259 buffer_atomic_inc v1, off, ttmp[12:15], 56 glc
 260 // NOSICIVI: error: register not available on this GPU
 261 // GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]