llvm/test/MC/AMDGPU/vop2.s

   1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
   2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
   3 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
   4 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=VI
   5
   6 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
   7 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
   8 // RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
   9 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
  10
  11 //===----------------------------------------------------------------------===//
  12 // Generic Checks for floating-point instructions (These have modifiers).
  13 //===----------------------------------------------------------------------===//
  14
  15 // TODO: 64-bit encoding of instructions with modifiers
  16
  17 // _e32 suffix
  18 // SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
  19 // VI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
  20 v_add_f32_e32 v1, v2, v3
  21
  22 // src0 inline immediate
  23 // SICI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06]
  24 // VI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x02]
  25 v_add_f32 v1, 1.0, v3
  26
  27 // src0 negative inline immediate
  28 // SICI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06]
  29 // VI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x02]
  30 v_add_f32 v1, -1.0, v3
  31
  32 // src0 literal
  33 // SICI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42]
  34 // VI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x02,0x00,0x00,0xc8,0x42]
  35 v_add_f32 v1, 100.0, v3
  36
  37 // src0 negative literal
  38 // SICI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2]
  39 // VI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x02,0x00,0x00,0xc8,0xc2]
  40 v_add_f32 v1, -100.0, v3
  41
  42 //===----------------------------------------------------------------------===//
  43 // Generic Checks for integer instructions (These don't have modifiers).
  44 //===----------------------------------------------------------------------===//
  45
  46 // _e32 suffix
  47 // SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
  48 // VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
  49 v_mul_i32_i24_e32 v1, v2, v3
  50
  51 // _e64 suffix
  52 // SICI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00]
  53 // VI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x07,0x02,0x00]
  54 v_mul_i32_i24_e64 v1, v2, v3
  55
  56 // src0 inline
  57 // SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
  58 // VI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x0c]
  59 v_mul_i32_i24_e32 v1, 3, v3
  60
  61 // src0 negative inline
  62 // SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
  63 // VI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x0c]
  64 v_mul_i32_i24_e32 v1, -3, v3
  65
  66 // src1 inline
  67 // SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
  68 // VI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x07,0x01,0x00]
  69 v_mul_i32_i24_e64 v1, v2, 3
  70
  71 // src1 negative inline
  72 // SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
  73 // VI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x87,0x01,0x00]
  74 v_mul_i32_i24_e64 v1, v2, -3
  75
  76 // src0 literal
  77 // SICI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00]
  78 // VI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x0c,0x64,0x00,0x00,0x00]
  79 v_mul_i32_i24_e32 v1, 100, v3
  80
  81 // src1 negative literal
  82 // SICI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff]
  83 // VI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x0c,0x9c,0xff,0xff,0xff]
  84 v_mul_i32_i24_e32 v1, -100, v3
  85
  86 //===----------------------------------------------------------------------===//
  87 // Checks for legal operands
  88 //===----------------------------------------------------------------------===//
  89
  90 // src0 sgpr
  91 // SICI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12]
  92 // VI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x0c]
  93 v_mul_i32_i24_e32 v1, s2, v3
  94
  95 // src1 sgpr
  96 // SICI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00]
  97 // VI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x07,0x00,0x00]
  98 v_mul_i32_i24_e64 v1, v2, s3
  99
 100 // src0, src1 same sgpr
 101 // SICI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00]
 102 // VI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x04,0x00,0x00]
 103 v_mul_i32_i24_e64 v1, s2, s2
 104
 105 // src0 sgpr, src1 inline
 106 // SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
 107 // VI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x06,0x01,0x00]
 108 v_mul_i32_i24_e64 v1, s2, 3
 109
 110 // src0 inline src1 sgpr
 111 // SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
 112 // VI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x06,0xd1,0x83,0x06,0x00,0x00]
 113 v_mul_i32_i24_e64 v1, 3, s3
 114
 115 // SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a]
 116 // NOVI: error: instruction not supported on this GPU
 117 v_add_i32_e32 v0, vcc, 0.5, v0
 118
 119 // SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40]
 120 // NOVI: error: instruction not supported on this GPU
 121 v_add_i32_e32 v0, vcc, 3.125, v0
 122
 123 //===----------------------------------------------------------------------===//
 124 // Instructions
 125 //===----------------------------------------------------------------------===//
 126
 127 // GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
 128 v_cndmask_b32 v1, v2, v3, vcc
 129
 130 // GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
 131 v_cndmask_b32_e32 v1, v2, v3, vcc
 132
 133 // SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
 134 // VI:   v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
 135 v_readlane_b32 s1, v2, s3
 136
 137 // SICI: v_writelane_b32 v1, s2, 4 ; encoding: [0x02,0x08,0x03,0x04]
 138 // VI:   v_writelane_b32 v1, s2, 4 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x08,0x01,0x00]
 139 v_writelane_b32 v1, s2, 4
 140
 141 // SICI: v_writelane_b32 v2, 1, s4 ; encoding: [0x81,0x08,0x04,0x04]
 142 // VI:   v_writelane_b32 v2, 1, s4 ; encoding: [0x02,0x00,0x8a,0xd2,0x81,0x08,0x00,0x00]
 143 v_writelane_b32 v2, 1, s4
 144
 145 // SICI: v_writelane_b32 v255, 0xaf123456, 2 ; encoding: [0xff,0x04,0xff,0x05,0x56,0x34,0x12,0xaf]
 146 // NOVI: error: operands are not valid for this GPU or mode
 147 v_writelane_b32 v255, 0xaf123456, 2
 148
 149 // SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
 150 // VI:   v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
 151 v_add_f32 v1, v2, v3
 152
 153 // SICI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
 154 // VI:   v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
 155 v_sub_f32 v1, v2, v3
 156
 157 // SICI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
 158 // VI:   v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
 159 v_subrev_f32 v1, v2, v3
 160
 161 // SICI: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
 162 // NOVI: error: instruction not supported on this GPU
 163 v_mac_legacy_f32 v1, v2, v3
 164
 165 // SICI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
 166 // VI:   v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
 167 v_mul_legacy_f32_e32 v1, v2, v3
 168
 169 // SICI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
 170 // VI:   v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
 171 v_mul_f32 v1, v2, v3
 172
 173 // SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
 174 // VI:   v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
 175 v_mul_i32_i24_e32 v1, v2, v3
 176
 177 // SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
 178 // VI:   v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
 179 v_mul_hi_i32_i24_e32 v1, v2, v3
 180
 181 // SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
 182 // VI:   v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
 183 v_mul_u32_u24_e32 v1, v2, v3
 184
 185 // SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
 186 // VI:   v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
 187 v_mul_hi_u32_u24_e32 v1, v2, v3
 188
 189 // SICI: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
 190 // NOVI: error: instruction not supported on this GPU
 191 v_min_legacy_f32_e32 v1, v2, v3
 192
 193 // SICI: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
 194 // NOVI: error: instruction not supported on this GPU
 195 v_max_legacy_f32 v1, v2, v3
 196
 197 // SICI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
 198 // VI:   v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
 199 v_min_f32_e32 v1, v2, v3
 200
 201 // SICI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
 202 // VI:   v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
 203 v_max_f32 v1, v2 v3
 204
 205 // SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
 206 // VI:   v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
 207 v_min_i32_e32 v1, v2, v3
 208
 209 // SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
 210 // VI:   v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
 211 v_max_i32_e32 v1, v2, v3
 212
 213 // SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
 214 // VI:   v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
 215 v_min_u32_e32 v1, v2, v3
 216
 217 // SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
 218 // VI:   v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
 219 v_max_u32_e32 v1, v2, v3
 220
 221 // SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
 222 // NOVI: error: instruction not supported on this GPU
 223 v_lshr_b32_e32 v1, v2, v3
 224
 225 // SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
 226 // VI:   v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
 227 v_lshrrev_b32_e32 v1, v2, v3
 228
 229 // SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
 230 // NOVI: error: instruction not supported on this GPU
 231 v_ashr_i32_e32 v1, v2, v3
 232
 233 // SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
 234 // VI:   v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
 235 v_ashrrev_i32_e32 v1, v2, v3
 236
 237 // SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
 238 // NOVI: error: instruction not supported on this GPU
 239 v_lshl_b32_e32 v1, v2, v3
 240
 241 // SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
 242 // VI:   v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
 243 v_lshlrev_b32_e32 v1, v2, v3
 244
 245 // SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
 246 // VI:   v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
 247 v_and_b32_e32 v1, v2, v3
 248
 249 // SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
 250 // VI:   v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
 251 v_or_b32_e32 v1, v2, v3
 252
 253 // SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
 254 // VI:   v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
 255 v_xor_b32_e32 v1, v2, v3
 256
 257 // SICI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x3c,0xd2,0x02,0x07,0x02,0x00]
 258 // VI:   v_bfm_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
 259 v_bfm_b32_e64 v1, v2, v3
 260
 261 // SICI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
 262 // VI:   v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
 263 v_mac_f32_e32 v1, v2, v3
 264
 265 // SICI: v_madmk_f32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42]
 266 // VI:   v_madmk_f32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42]
 267 v_madmk_f32 v1, v2, 64.0, v3
 268
 269 // SICI: v_madak_f32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42]
 270 // VI:   v_madak_f32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42]
 271 v_madak_f32 v1, v2, v3, 64.0
 272
 273 // SICI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x44,0xd2,0x02,0x07,0x02,0x00]
 274 // VI:   v_bcnt_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
 275 v_bcnt_u32_b32_e64 v1, v2, v3
 276
 277 // SICI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x46,0xd2,0x02,0x07,0x02,0x00]
 278 // VI:   v_mbcnt_lo_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
 279 v_mbcnt_lo_u32_b32_e64 v1, v2, v3
 280
 281 // SICI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x48,0xd2,0x02,0x07,0x02,0x00]
 282 // VI:   v_mbcnt_hi_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
 283 v_mbcnt_hi_u32_b32_e64 v1, v2, v3
 284
 285 // SICI: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
 286 // NOVI: error: instruction not supported on this GPU
 287 v_add_i32_e32 v1, vcc, v2, v3
 288
 289 // SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
 290 // NOVI: error: instruction not supported on this GPU
 291 v_add_i32 v1, s[0:1], v2, v3
 292
 293 // SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
 294 // NOVI: error: instruction not supported on this GPU
 295 v_add_i32_e64 v1, s[0:1], v2, v3
 296
 297 // SICI: v_add_i32_e64 v1, vcc, v2, v3 ; encoding: [0x01,0x6a,0x4a,0xd2,0x02,0x07,0x02,0x00]
 298 // NOVI: error: instruction not supported on this GPU
 299 v_add_i32_e64 v1, vcc, v2, v3
 300
 301 // NOSICI: error: instruction not supported on this GPU
 302 // VI: v_add_u32_e32 v1, vcc, v2, v3   ; encoding: [0x02,0x07,0x02,0x32]
 303 v_add_u32 v1, vcc, v2, v3
 304
 305 // NOSICI: error: instruction not supported on this GPU
 306 // VI: v_add_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]
 307 v_add_u32 v1, s[0:1], v2, v3
 308
 309 // SICI: v_sub_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
 310 // NOVI: error: instruction not supported on this GPU
 311 v_sub_i32 v1, vcc, v2, v3
 312
 313 // SICI: v_sub_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4c,0xd2,0x02,0x07,0x02,0x00]
 314 // NOVI: error: instruction not supported on this GPU
 315 v_sub_i32 v1, s[0:1], v2, v3
 316
 317 // NOSICI: error: instruction not supported on this GPU
 318 // VI:   v_sub_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
 319 v_sub_u32 v1, vcc, v2, v3
 320
 321 // NOSICI: error: instruction not supported on this GPU
 322 // VI:   v_sub_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x1a,0xd1,0x02,0x07,0x02,0x00]
 323 v_sub_u32 v1, s[0:1], v2, v3
 324
 325 // SICI: v_subrev_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
 326 // NOVI: error: instruction not supported on this GPU
 327 v_subrev_i32 v1, vcc, v2, v3
 328
 329 // SICI: v_subrev_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4e,0xd2,0x02,0x07,0x02,0x00]
 330 // NOVI: error: instruction not supported on this GPU
 331 v_subrev_i32 v1, s[0:1], v2, v3
 332
 333 // NOSICI: error: instruction not supported on this GPU
 334 // VI:   v_subrev_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
 335 v_subrev_u32 v1, vcc, v2, v3
 336
 337 // NOSICI: error: instruction not supported on this GPU
 338 // VI:   v_subrev_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x1b,0xd1,0x02,0x07,0x02,0x00]
 339 v_subrev_u32 v1, s[0:1], v2, v3
 340
 341 // SICI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x50]
 342 // VI:   v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
 343 v_addc_u32 v1, vcc, v2, v3, vcc
 344
 345 // SICI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x50]
 346 // VI:   v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
 347 v_addc_u32_e32 v1, vcc, v2, v3, vcc
 348
 349
 350 // SICI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0xaa,0x01]
 351 // VI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0xaa,0x01]
 352 v_addc_u32 v1, s[0:1], v2, v3, vcc
 353
 354 // SICI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0x0a,0x00]
 355 // VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
 356 v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
 357
 358 // SICI:        v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0x0a,0x00]
 359 // VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
 360 v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3]
 361
 362 // SICI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x50,0xd2,0x02,0x07,0xaa,0x01]
 363 // VI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x1c,0xd1,0x02,0x07,0xaa,0x01]
 364 v_addc_u32_e64 v1, vcc, v2, v3, vcc
 365
 366 // SICI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x52]
 367 // VI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3a]
 368 v_subb_u32 v1, vcc, v2, v3, vcc
 369
 370 // SICI: v_subb_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x52,0xd2,0x02,0x07,0xaa,0x01]
 371 // VI: v_subb_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1d,0xd1,0x02,0x07,0xaa,0x01]
 372 v_subb_u32 v1, s[0:1], v2, v3, vcc
 373
 374 // SICI: v_subbrev_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x54]
 375 // VI:   v_subbrev_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3c]
 376 v_subbrev_u32 v1, vcc, v2, v3, vcc
 377
 378 // SICI: v_subbrev_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x54,0xd2,0x02,0x07,0xaa,0x01]
 379 // VI: v_subbrev_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1e,0xd1,0x02,0x07,0xaa,0x01]
 380 v_subbrev_u32 v1, s[0:1], v2, v3, vcc
 381
 382 // SICI: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
 383 // VI:   v_ldexp_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x88,0xd2,0x02,0x07,0x02,0x00]
 384 v_ldexp_f32 v1, v2, v3
 385
 386 // SICI: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
 387 // VI:   v_cvt_pkaccum_u8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0xf0,0xd1,0x02,0x07,0x02,0x00]
 388 v_cvt_pkaccum_u8_f32 v1, v2, v3
 389
 390 // SICI: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
 391 // VI:   v_cvt_pknorm_i16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x94,0xd2,0x02,0x07,0x02,0x00]
 392 v_cvt_pknorm_i16_f32 v1, v2, v3
 393
 394 // SICI: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
 395 // VI:   v_cvt_pknorm_u16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x95,0xd2,0x02,0x07,0x02,0x00]
 396 v_cvt_pknorm_u16_f32 v1, v2, v3
 397
 398 // SICI: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
 399 // VI:   v_cvt_pkrtz_f16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x96,0xd2,0x02,0x07,0x02,0x00]
 400 v_cvt_pkrtz_f16_f32 v1, v2, v3
 401
 402 // SICI: v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x60,0xd2,0x02,0x07,0x02,0x00]
 403 // VI:   v_cvt_pk_u16_u32 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00]
 404 v_cvt_pk_u16_u32_e64 v1, v2, v3
 405
 406 // SICI: v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x62,0xd2,0x02,0x07,0x02,0x00]
 407 // VI:   v_cvt_pk_i16_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00]
 408 v_cvt_pk_i16_i32_e64 v1, v2, v3
 409
 410 // NOSICI: error: instruction not supported on this GPU
 411 // VI:     v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
 412 v_add_f16_e32 v1, v2, v3
 413
 414 // NOSICI: error: instruction not supported on this GPU
 415 // VI:     v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40]
 416 v_sub_f16_e32 v1, v2, v3
 417
 418 // NOSICI: error: instruction not supported on this GPU
 419 // VI:     v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42]
 420 v_subrev_f16_e32 v1, v2, v3
 421
 422 // NOSICI: error: instruction not supported on this GPU
 423 // VI:     v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
 424 v_mul_f16_e32 v1, v2, v3
 425
 426 // NOSICI: error: instruction not supported on this GPU
 427 // VI:     v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
 428 v_mac_f16_e32 v1, v2, v3
 429
 430 // NOSICI: error: instruction not supported on this GPU
 431 // VI:     v_madmk_f16 v1, v2, 0x5400, v3 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x54,0x00,0x00]
 432 v_madmk_f16 v1, v2, 64.0, v3
 433
 434 // NOSICI: error: instruction not supported on this GPU
 435 // VI:     v_madak_f16 v1, v2, v3, 0x5400 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x54,0x00,0x00]
 436 v_madak_f16 v1, v2, v3, 64.0
 437
 438 // NOSICI: error: instruction not supported on this GPU
 439 // VI:     v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
 440 v_add_u16_e32 v1, v2, v3
 441
 442 // NOSICI: error: instruction not supported on this GPU
 443 // VI:     v_add_u16_e64 v1, v2, v3 clamp  ; encoding: [0x01,0x80,0x26,0xd1,0x02,0x07,0x02,0x00]
 444 v_add_u16 v1, v2, v3 clamp
 445
 446 // NOSICI: error: instruction not supported on this GPU
 447 // VI:     v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
 448 v_sub_u16_e32 v1, v2, v3
 449
 450 // NOSICI: error: instruction not supported on this GPU
 451 // VI:     v_sub_u16_e64 v1, v2, v3 clamp  ; encoding: [0x01,0x80,0x27,0xd1,0x02,0x07,0x02,0x00]
 452 v_sub_u16 v1, v2, v3 clamp
 453
 454 // NOSICI: error: instruction not supported on this GPU
 455 // VI:     v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
 456 v_subrev_u16_e32 v1, v2, v3
 457
 458 // NOSICI: error: instruction not supported on this GPU
 459 // VI:     v_subrev_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x28,0xd1,0x02,0x07,0x02,0x00]
 460 v_subrev_u16 v1, v2, v3 clamp
 461
 462 // NOSICI: error: instruction not supported on this GPU
 463 // VI:     v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
 464 v_mul_lo_u16_e32 v1, v2, v3
 465
 466 // NOSICI: error: instruction not supported on this GPU
 467 // VI:     v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
 468 v_lshlrev_b16_e32 v1, v2, v3
 469
 470 // NOSICI: error: instruction not supported on this GPU
 471 // VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
 472 v_lshrrev_b16_e32 v1, v2, v3
 473
 474 // NOSICI: error: instruction not supported on this GPU
 475 // VI:     v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
 476 v_ashrrev_i16_e32 v1, v2, v3
 477
 478 // NOSICI: error: instruction not supported on this GPU
 479 // VI:     v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
 480 v_max_f16_e32 v1, v2, v3
 481
 482 // NOSICI: error: instruction not supported on this GPU
 483 // VI:     v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
 484 v_min_f16_e32 v1, v2, v3
 485
 486 // NOSICI: error: instruction not supported on this GPU
 487 // VI:     v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
 488 v_max_u16_e32 v1, v2, v3
 489
 490 // NOSICI: error: instruction not supported on this GPU
 491 // VI:     v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
 492 v_max_i16_e32 v1, v2, v3
 493
 494 // NOSICI: error: instruction not supported on this GPU
 495 // VI:     v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
 496 v_min_u16_e32 v1, v2, v3
 497
 498 // NOSICI: error: instruction not supported on this GPU
 499 // VI:     v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64]
 500 v_min_i16_e32 v1, v2, v3
 501
 502 // NOSICI: error: instruction not supported on this GPU
 503 // VI:     v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66]
 504 v_ldexp_f16_e32 v1, v2, v3