1 // RUN
: not llvm-mc
-triple
=thumbv7
-show-encoding
< %s
2>&1 | FileCheck
--check-prefixes
=CHECK-NONARM
,CHECK-THUMBV7
%s
2 // RUN
: not llvm-mc
-triple
=thumbv8
-show-encoding
< %s
2>&1 | FileCheck
--check-prefixes
=CHECK-NONARM
,CHECK-THUMBV8
%s
3 // RUN
: llvm-mc
-triple
=armv7
-show-encoding
< %s
2>&1 | FileCheck
--check-prefix
=CHECK-ARM
%s
5 // lsl
#0 is actually mov, so here we check that it behaves the same as
6 // mov with regards to the permitted registers
8 // Using PC is invalid in thumb
16 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
17 // CHECK-NONARM-NEXT
: lsl pc
, r0, #0
18 // CHECK-NONARM
: note
: instruction requires
: arm-mode
19 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r14]
21 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
22 // CHECK-NONARM-NEXT
: lsl
r0, pc
, #0
23 // CHECK-NONARM
: note
: instruction requires
: arm-mode
24 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r14]
26 // CHECK-NONARM
: error
: instruction requires
: arm-mode
27 // CHECK-NONARM-NEXT
: lsl pc
, pc
, #0
29 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
30 // CHECK-NONARM-NEXT
: lsls pc
, r0, #0
31 // CHECK-NONARM
: note
: instruction requires
: arm-mode
32 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r14]
34 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
35 // CHECK-NONARM-NEXT
: lsls
r0, pc
, #0
36 // CHECK-NONARM
: note
: instruction requires
: arm-mode
37 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r14]
39 // CHECK-NONARM
: error
: instruction requires
: arm-mode
40 // CHECK-NONARM-NEXT
: lsls pc
, pc
, #0
42 // CHECK-ARM
: mov pc
, r0 @ encoding
: [0x00,0xf0,0xa0,0xe1]
43 // CHECK-ARM
: mov
r0, pc @ encoding
: [0x0f,0x00,0xa0,0xe1]
44 // CHECK-ARM
: mov pc
, pc @ encoding
: [0x0f,0xf0,0xa0,0xe1]
45 // CHECK-ARM
: movs pc
, r0 @ encoding
: [0x00,0xf0,0xb0,0xe1]
46 // CHECK-ARM
: movs
r0, pc @ encoding
: [0x0f,0x00,0xb0,0xe1]
47 // CHECK-ARM
: movs pc
, pc @ encoding
: [0x0f,0xf0,0xb0,0xe1]
56 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
57 // CHECK-NONARM-NEXT
: mov pc
, r0, lsl
#0
58 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r15]
59 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
60 // CHECK-THUMBV8
: note
: operand must
be a register in range
[r0, r14]
62 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
63 // CHECK-NONARM-NEXT
: mov
r0, pc
, lsl
#0
64 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r15]
65 // CHECK-NONARM
: note
: invalid operand for instruction
66 // CHECK-NONARM
: note
: invalid operand for instruction
67 // CHECK-NONARM
: note
: operand must
be an immediate in the range
[256,65535]
69 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
70 // CHECK-NONARM-NEXT
: mov pc
, pc
, lsl
#0
71 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r15]
72 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
73 // CHECK-THUMBV8
: note
: operand must
be a register in range
[r0, r14]
75 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
76 // CHECK-NONARM-NEXT
: movs pc
, r0, lsl
#0
77 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
78 // CHECK-THUMBV8
: note
: operand must
be a register in range
[r0, r14]
79 // CHECK-NONARM
: note
: invalid operand for instruction
81 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
82 // CHECK-NONARM-NEXT
: movs
r0, pc
, lsl
#0
83 // CHECK-NONARM
: note
: operand must
be a register in range
[r0, r14]
84 // CHECK-NONARM
: note
: invalid operand for instruction
85 // CHECK-NONARM
: note
: invalid operand for instruction
87 // CHECK-NONARM
: error
: invalid instruction
, any one of the following would fix this
:
88 // CHECK-NONARM-NEXT
: movs pc
, pc
, lsl
#0
89 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
90 // CHECK-THUMBV8
: note
: operand must
be a register in range
[r0, r14]
91 // CHECK-NONARM
: note
: invalid operand for instruction
93 // CHECK-ARM
: mov pc
, r0 @ encoding
: [0x00,0xf0,0xa0,0xe1]
94 // CHECK-ARM
: mov
r0, pc @ encoding
: [0x0f,0x00,0xa0,0xe1]
95 // CHECK-ARM
: mov pc
, pc @ encoding
: [0x0f,0xf0,0xa0,0xe1]
96 // CHECK-ARM
: movs pc
, r0 @ encoding
: [0x00,0xf0,0xb0,0xe1]
97 // CHECK-ARM
: movs
r0, pc @ encoding
: [0x0f,0x00,0xb0,0xe1]
98 // CHECK-ARM
: movs pc
, pc @ encoding
: [0x0f,0xf0,0xb0,0xe1]
100 // Using SP is invalid before ARMv8 in thumb unless non-flags-setting
101 // and one of the source
and destination is
not SP
107 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
108 // CHECK-THUMBV7-NEXT
: lsl sp
, sp
, #0
109 // CHECK-THUMBV7
: instruction requires
: arm-mode
110 // CHECK-THUMBV7
: instruction variant requires ARMv8
or later
111 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
112 // CHECK-THUMBV7-NEXT
: lsls sp
, sp
, #0
113 // CHECK-THUMBV7
: instruction requires
: arm-mode
114 // CHECK-THUMBV7
: instruction variant requires ARMv8
or later
115 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
116 // CHECK-THUMBV7-NEXT
: lsls
r0, sp
, #0
117 // CHECK-THUMBV7
: instruction requires
: arm-mode
118 // CHECK-THUMBV7
: instruction variant requires ARMv8
or later
119 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
120 // CHECK-THUMBV7-NEXT
: lsls sp
, r0, #0
121 // CHECK-THUMBV7
: instruction requires
: arm-mode
122 // CHECK-THUMBV7
: instruction variant requires ARMv8
or later
124 // CHECK-ARM
: mov sp
, sp @ encoding
: [0x0d,0xd0,0xa0,0xe1]
125 // CHECK-ARM
: movs sp
, sp @ encoding
: [0x0d,0xd0,0xb0,0xe1]
126 // CHECK-ARM
: movs
r0, sp @ encoding
: [0x0d,0x00,0xb0,0xe1]
127 // CHECK-ARM
: movs sp
, r0 @ encoding
: [0x00,0xd0,0xb0,0xe1]
134 // FIXME
: We should consistently have the
"requires ARMv8" error here
135 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
136 // CHECK-THUMBV7-NEXT
: mov sp
, sp
, lsl
#0
137 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r15]
138 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
140 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
141 // CHECK-THUMBV7-NEXT
: movs sp
, sp
, lsl
#0
142 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r14]
143 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
145 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
146 // CHECK-THUMBV7-NEXT
: movs
r0, sp
, lsl
#0
147 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r14]
148 // CHECK-THUMBV7
: note
: invalid operand for instruction
149 // CHECK-THUMBV7
: note
: instruction variant requires ARMv8
or later
151 // CHECK-THUMBV7
: error
: invalid instruction
, any one of the following would fix this
:
152 // CHECK-THUMBV7-NEXT
: movs sp
, r0, lsl
#0
153 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r14]
154 // CHECK-THUMBV7
: note
: operand must
be a register in range
[r0, r12] or r14
156 // CHECK-ARM
: mov sp
, sp @ encoding
: [0x0d,0xd0,0xa0,0xe1]
157 // CHECK-ARM
: movs sp
, sp @ encoding
: [0x0d,0xd0,0xb0,0xe1]
158 // CHECK-ARM
: movs
r0, sp @ encoding
: [0x0d,0x00,0xb0,0xe1]
159 // CHECK-ARM
: movs sp
, r0 @ encoding
: [0x00,0xd0,0xb0,0xe1]