1 # RUN: llvm-mc -triple armv7 %s -show-encoding | FileCheck %s
2 # RUN: not llvm-mc -triple armv7 %s -show-encoding -mattr=+no-neg-immediates 2>&1 | FileCheck %s -check-prefix=CHECK-DISABLED
6 ADC
r0, r1, #0xFFFFFF00
7 # CHECK: sbc r0, r1, #255
8 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
10 ADC
r0, r1, #0xFFFFFE03
11 # CHECK: sbc r0, r1, #508
12 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
14 ADD r0, r1, #0xFFFFFF01
15 # CHECK: sub r0, r1, #255
16 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
18 AND r0, r1, #0xFFFFFF00
19 # CHECK: bic r0, r1, #255
20 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
22 BIC
r0, r1, #0xFFFFFF00
23 # CHECK: and r0, r1, #255
24 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
28 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
32 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
36 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
40 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
42 SBC
r0, r1, #0xFFFFFF00
43 # CHECK: adc r0, r1, #255
44 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
46 SUB r0, r1, #0xFFFFFF01
47 # CHECK: add r0, r1, #255
48 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
53 ADD r0, r1, #0xFFFFFF00
54 # CHECK: sub.w r0, r1, #256
55 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
57 ADDS
r0, r1, #0xFFFFFF00
58 # CHECK: subs.w r0, r1, #256
59 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
60 # CHECK-DISABLED: ADDS
61 ADDS.W
r0, r1, #0xFFFFFF00
62 # CHECK: subs.w r0, r1, #256
63 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
64 # CHECK-DISABLED: ADDS.W
65 ADC
r0, r1, #0xFFFFFF00
66 # CHECK: sbc r0, r1, #255
67 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
69 ADC
r0, r1, #0xFFFF00FF
70 # CHECK: sbc r0, r1, #65280
71 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
73 ADC
r0, r1, #0xFFFEFFFE
74 # CHECK: sbc r0, r1, #65537 @ encoding: [0x61,0xf1,0x01,0x10]
75 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
77 ADC
r0, r1, #0xFEFFFEFF
78 # CHECK: sbc r0, r1, #16777472 @ encoding: [0x61,0xf1,0x01,0x20]
79 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
81 ADD.W
r0, r0, #0xFFFFFF01
82 # CHECK: sub.w r0, r0, #255
83 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
84 # CHECK-DISABLED: ADD.W
85 ADD.W
r0, r0, #0xFF01FF02
86 # CHECK: sub.w r0, r0, #16646398 @ encoding: [0xa0,0xf1,0xfe,0x10]
87 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
88 # CHECK-DISABLED: ADD.W
89 ADDW
r0, r1, #0xFFFFFF01
90 # CHECK: subw r0, r1, #255 @ encoding: [0xa1,0xf2,0xff,0x00]
91 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
92 # CHECK-DISABLED: ADDW
93 ADD.W
r0, r1, #0xFFFFFF01
94 # CHECK: sub.w r0, r1, #255 @ encoding: [0xa1,0xf1,0xff,0x00]
95 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
96 # CHECK-DISABLED: ADD.W
97 AND r0, r1, #0xFFFFFF00
98 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
100 # CHECK: bic r0, r1, #255
101 AND r0, r1, #0xFEFFFEFF
102 # CHECK: bic r0, r1, #16777472 @ encoding: [0x21,0xf0,0x01,0x20]
103 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
104 # CHECK-DISABLED: AND
105 AND.W
r0, r1, #0xFFFFFF00
106 # CHECK: bic r0, r1, #255
107 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
108 # CHECK-DISABLED: AND.W
109 ANDS
r0, r1, #0xFFFFFF00
110 # CHECK: bics r0, r1, #255
111 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
112 # CHECK-DISABLED: ANDS
113 BIC
r0, r1, #0xFFFFFF00
114 # CHECK: and r0, r1, #255
115 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
116 # CHECK-DISABLED: BIC
117 BIC.W
r0, r1, #0xFFFFFF00
118 # CHECK: and r0, r1, #255
119 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
120 # CHECK-DISABLED: BIC.W
121 BICS
r0, r1, #0xFFFFFF00
122 # CHECK: ands r0, r1, #255
123 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
124 # CHECK-DISABLED: BICS
125 BICS.W
r0, r1, #0xFFFFFF00
126 # CHECK: ands r0, r1, #255
127 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
128 # CHECK-DISABLED: BICS.W
129 BIC
r0, r1, #0xFEFFFEFF
130 # CHECK: and r0, r1, #16777472 @ encoding: [0x01,0xf0,0x01,0x20]
131 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
132 # CHECK-DISABLED: BIC
133 ORR
r0, r1, #0xFFFFFF00
134 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
135 # CHECK-DISABLED: ORR
136 # CHECK: orn r0, r1, #255
137 ORR
r0, r1, #0xFEFFFEFF
138 # CHECK: orn r0, r1, #16777472 @ encoding: [0x61,0xf0,0x01,0x20]
139 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
140 # CHECK-DISABLED: ORR
141 ORN
r0, r1, #0xFFFFFF00
142 # CHECK: orr r0, r1, #255
143 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
144 # CHECK-DISABLED: ORN
145 ORN
r0, r1, #0xFEFFFEFF
146 # CHECK: orr r0, r1, #16777472 @ encoding: [0x41,0xf0,0x01,0x20]
147 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
148 # CHECK-DISABLED: ORN
150 # CHECK: cmn.w r0, #255
151 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
152 # CHECK-DISABLED: CMP
154 # CHECK: cmp.w r0, #255
155 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
156 # CHECK-DISABLED: CMN
158 # CHECK: mvn r0, #255
159 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
160 # CHECK-DISABLED: MOV
162 # CHECK: mov.w r0, #255
163 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
164 # CHECK-DISABLED: MVN
165 SBC
r0, r1, #0xFFFFFF00
166 # CHECK: adc r0, r1, #255
167 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
168 # CHECK-DISABLED: SBC
169 SUBW
r0, r1, #0xFFFFFF01
170 # CHECK: addw r0, r1, #255
171 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
172 # CHECK-DISABLED: SUBW
173 SUB.W
r0, r1, #0xFFFFFF01
174 # CHECK: add.w r0, r1, #255
175 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
176 # CHECK-DISABLED: SUB.W
177 SUB r0, r1, #0xFFFFFF00
178 # CHECK: add.w r0, r1, #256
179 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
180 # CHECK-DISABLED: SUB
181 SUBS
r0, r1, #0xFFFFFF00
182 # CHECK: adds.w r0, r1, #256
183 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
184 # CHECK-DISABLED: SUBS
185 SUBS.W
r0, r1, #0xFFFFFF00
186 # CHECK: adds.w r0, r1, #256
187 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
188 # CHECK-DISABLED: SUBS.W
191 # CHECK: sub.w r0, r1, #13
192 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
193 # CHECK-DISABLED: ADD