llvm/test/MC/RISCV/rv32e-valid.s

   1 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
   2 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
   3 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
   4 # RUN:     | llvm-objdump -M no-aliases -d -r - \
   5 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
   6
   7 # This file provides a basic sanity check for RV32E, checking that the expected
   8 # set of registers and instructions are accepted.
   9
  10 # CHECK-ASM-AND-OBJ: lui zero, 1
  11 lui x0, 1
  12 # CHECK-ASM-AND-OBJ: auipc ra, 2
  13 auipc x1, 2
  14
  15 # CHECK-OBJ: jal sp, 0xc
  16 # CHECK-ASM: jal sp, 4
  17 jal x2, 4
  18 # CHECK-ASM-AND-OBJ: jalr gp, 4(gp)
  19 jalr x3, x3, 4
  20
  21 # CHECK-OBJ: beq tp, t0, 0x18
  22 # CHECK-ASM: beq tp, t0, 8
  23 beq x4, x5, 8
  24 # CHECK-OBJ: bne t1, t2, 0x20
  25 # CHECK-ASM: bne t1, t2, 12
  26 bne x6, x7, 12
  27 # CHECK-OBJ: blt s0, s1, 0x28
  28 # CHECK-ASM: blt s0, s1, 16
  29 blt x8, x9, 16
  30 # CHECK-OBJ: bge a0, a1, 0x30
  31 # CHECK-ASM: bge a0, a1, 20
  32 bge x10, x11, 20
  33 # CHECK-OBJ: bgeu a2, a3, 0x38
  34 # CHECK-ASM: bgeu a2, a3, 24
  35 bgeu x12, x13, 24
  36
  37 # CHECK-ASM-AND-OBJ: lb a4, 25(a5)
  38 lb x14, 25(x15)
  39 # CHECK-ASM-AND-OBJ: lh zero, 26(ra)
  40 lh zero, 26(ra)
  41 # CHECK-ASM-AND-OBJ: lw sp, 28(gp)
  42 lw sp, 28(gp)
  43 # CHECK-ASM-AND-OBJ: lbu tp, 29(t0)
  44 lbu tp, 29(t0)
  45 # CHECK-ASM-AND-OBJ: lhu t1, 30(t2)
  46 lhu t1, 30(t2)
  47 # CHECK-ASM-AND-OBJ: sb s0, 31(s1)
  48 sb s0, 31(s1)
  49 # CHECK-ASM-AND-OBJ: sh a0, 32(a1)
  50 sh a0, 32(a1)
  51 # CHECK-ASM-AND-OBJ: sw a2, 36(a3)
  52 sw a2, 36(a3)
  53
  54 # CHECK-ASM-AND-OBJ: addi a4, a5, 37
  55 addi a4, a5, 37
  56 # CHECK-ASM-AND-OBJ: slti a0, a2, -20
  57 slti a0, a2, -20
  58 # CHECK-ASM-AND-OBJ: xori tp, t1, -99
  59 xori tp, t1, -99
  60 # CHECK-ASM-AND-OBJ: ori a0, a1, -2048
  61 ori a0, a1, -2048
  62 # CHECK-ASM-AND-OBJ: andi ra, sp, 2047
  63 andi ra, sp, 2047
  64 # CHECK-ASM-AND-OBJ: slli t1, t1, 31
  65 slli t1, t1, 31
  66 # CHECK-ASM-AND-OBJ: srli a0, a4, 0
  67 srli a0, a4, 0
  68 # CHECK-ASM-AND-OBJ: srai a1, sp, 15
  69 srai a1, sp, 15
  70 # CHECK-ASM-AND-OBJ: slli t0, t1, 13
  71 slli t0, t1, 13
  72
  73 # CHECK-ASM-AND-OBJ: add ra, zero, zero
  74 add ra, zero, zero
  75 # CHECK-ASM-AND-OBJ: sub t0, t2, t1
  76 sub t0, t2, t1
  77 # CHECK-ASM-AND-OBJ: sll a5, a4, a3
  78 sll a5, a4, a3
  79 # CHECK-ASM-AND-OBJ: slt s0, s0, s0
  80 slt s0, s0, s0
  81 # CHECK-ASM-AND-OBJ: sltu gp, a0, a1
  82 sltu gp, a0, a1
  83 # CHECK-ASM-AND-OBJ: xor s1, s0, s1
  84 xor s1, s0, s1
  85 # CHECK-ASM-AND-OBJ: srl a0, s0, t0
  86 srl a0, s0, t0
  87 # CHECK-ASM-AND-OBJ: sra t0, a3, zero
  88 sra t0, a3, zero
  89 # CHECK-ASM-AND-OBJ: or a5, t1, ra
  90 or a5, t1, ra
  91 # CHECK-ASM-AND-OBJ: and a0, s1, a3
  92 and a0, s1, a3
  93
  94 # CHECK-ASM-AND-OBJ: fence iorw, iorw
  95 fence iorw, iorw
  96 # CHECK-ASM-AND-OBJ: fence.tso
  97 fence.tso
  98 # CHECK-ASM-AND-OBJ: fence.i
  99 fence.i
 100
 101 # CHECK-ASM-AND-OBJ: ecall
 102 ecall
 103 # CHECK-ASM-AND-OBJ: ebreak
 104 ebreak
 105 # CHECK-ASM-AND-OBJ: unimp
 106 unimp
 107
 108 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
 109 csrrw t0, 0xfff, t1
 110 # CHECK-ASM-AND-OBJ: csrrs s0, cycle, zero
 111 csrrs s0, 0xc00, x0
 112 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
 113 csrrs s0, 0x001, a5
 114 # CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
 115 csrrc sp, 0x000, ra
 116 # CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
 117 csrrwi a5, 0x000, 0
 118 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
 119 csrrsi t2, 0xfff, 31
 120 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5
 121 csrrci t1, 0x140, 5