2 ; RUN: opt -S -dfa-jump-threading -debug-only=dfa-jump-threading -disable-output %s 2>&1 | FileCheck %s
4 ; This test checks that the analysis identifies all threadable paths in a
5 ; simple CFG. A threadable path includes a list of basic blocks, the exit
6 ; state, and the block that determines the next state.
7 ; < path of BBs that form a cycle > [ state, determinator ]
8 define i32 @test1(i32 %num) {
9 ; CHECK: < for.body for.inc > [ 1, for.inc ]
10 ; CHECK-NEXT: < for.body case1 for.inc > [ 2, for.inc ]
11 ; CHECK-NEXT: < for.body case2 for.inc > [ 1, for.inc ]
12 ; CHECK-NEXT: < for.body case2 si.unfold.false for.inc > [ 2, for.inc ]
17 %count = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
18 %state = phi i32 [ 1, %entry ], [ %state.next, %for.inc ]
19 switch i32 %state, label %for.inc [
28 %cmp = icmp eq i32 %count, 50
29 %sel = select i1 %cmp, i32 1, i32 2
33 %state.next = phi i32 [ %sel, %case2 ], [ 1, %for.body ], [ 2, %case1 ]
34 %inc = add nsw i32 %count, 1
35 %cmp.exit = icmp slt i32 %inc, %num
36 br i1 %cmp.exit, label %for.body, label %for.end
42 ; This test checks that the analysis finds threadable paths in a more
43 ; complicated CFG. Here the FSM is represented as a nested loop, with
45 define i32 @test2(i32 %init) {
46 ; CHECK: < loop.3 case2 > [ 3, loop.3 ]
47 ; CHECK-NEXT: < loop.3 case2 loop.1.backedge loop.1 loop.2 > [ 1, loop.1 ]
48 ; CHECK-NEXT: < loop.3 case2 loop.1.backedge si.unfold.false loop.1 loop.2 > [ 4, loop.1.backedge ]
49 ; CHECK-NEXT: < loop.3 case3 loop.2.backedge loop.2 > [ 0, loop.2.backedge ]
50 ; CHECK-NEXT: < loop.3 case3 case4 loop.2.backedge loop.2 > [ 3, loop.2.backedge ]
51 ; CHECK-NEXT: < loop.3 case3 case4 loop.1.backedge loop.1 loop.2 > [ 1, loop.1 ]
52 ; CHECK-NEXT: < loop.3 case3 case4 loop.1.backedge si.unfold.false loop.1 loop.2 > [ 2, loop.1.backedge ]
53 ; CHECK-NEXT: < loop.3 case4 loop.2.backedge loop.2 > [ 3, loop.2.backedge ]
54 ; CHECK-NEXT: < loop.3 case4 loop.1.backedge loop.1 loop.2 > [ 1, loop.1 ]
55 ; CHECK-NEXT: < loop.3 case4 loop.1.backedge si.unfold.false loop.1 loop.2 > [ 2, loop.1.backedge ]
57 %cmp = icmp eq i32 %init, 0
58 %sel = select i1 %cmp, i32 0, i32 2
62 %state.1 = phi i32 [ %sel, %entry ], [ %state.1.be2, %loop.1.backedge ]
66 %state.2 = phi i32 [ %state.1, %loop.1 ], [ %state.2.be, %loop.2.backedge ]
70 %state = phi i32 [ %state.2, %loop.2 ], [ 3, %case2 ]
71 switch i32 %state, label %infloop.i [
80 br i1 %cmp, label %loop.3, label %loop.1.backedge
83 br i1 %cmp, label %loop.2.backedge, label %case4
86 br i1 %cmp, label %loop.2.backedge, label %loop.1.backedge
89 %state.1.be = phi i32 [ 2, %case4 ], [ 4, %case2 ]
90 %state.1.be2 = select i1 %cmp, i32 1, i32 %state.1.be
94 %state.2.be = phi i32 [ 3, %case4 ], [ 0, %case3 ]
112 ; Verify that having the switch block as a determinator is handled correctly.
114 ; CHECK: < bb43 bb59 bb3 bb31 bb41 > [ 77, bb43 ]
115 ; CHECK-NEXT: < bb43 bb49 bb59 bb3 bb31 bb41 > [ 77, bb43 ]
117 %i = alloca [420 x i8], align 1
118 %i2 = getelementptr inbounds [420 x i8], [420 x i8]* %i, i64 0, i64 390
121 bb3: ; preds = %bb59, %bb
122 %i4 = phi i8* [ %i2, %bb ], [ %i60, %bb59 ]
123 %i5 = phi i8 [ 77, %bb ], [ %i64, %bb59 ]
124 %i6 = phi i32 [ 2, %bb ], [ %i63, %bb59 ]
125 %i7 = phi i32 [ 26, %bb ], [ %i62, %bb59 ]
126 %i8 = phi i32 [ 25, %bb ], [ %i61, %bb59 ]
127 %i9 = icmp sgt i32 %i7, 2
128 %i10 = select i1 %i9, i32 %i7, i32 2
129 %i11 = add i32 %i8, 2
130 %i12 = sub i32 %i11, %i10
131 %i13 = mul nsw i32 %i12, 3
132 %i14 = add nsw i32 %i13, %i6
133 %i15 = sext i32 %i14 to i64
134 %i16 = getelementptr inbounds i8, i8* %i4, i64 %i15
135 %i17 = load i8, i8* %i16, align 1
136 %i18 = icmp sgt i8 %i17, 0
137 br i1 %i18, label %bb21, label %bb31
140 br i1 true, label %bb59, label %bb43
142 bb59: ; preds = %bb49, %bb43, %bb31, %bb21
143 %i60 = phi i8* [ %i44, %bb49 ], [ %i44, %bb43 ], [ %i34, %bb31 ], [ %i4, %bb21 ]
144 %i61 = phi i32 [ %i45, %bb49 ], [ %i45, %bb43 ], [ %i33, %bb31 ], [ %i8, %bb21 ]
145 %i62 = phi i32 [ %i47, %bb49 ], [ %i47, %bb43 ], [ %i32, %bb31 ], [ %i7, %bb21 ]
146 %i63 = phi i32 [ %i48, %bb49 ], [ %i48, %bb43 ], [ 2, %bb31 ], [ %i6, %bb21 ]
147 %i64 = phi i8 [ %i46, %bb49 ], [ %i46, %bb43 ], [ 77, %bb31 ], [ %i5, %bb21 ]
148 %i65 = icmp sgt i32 %i62, 0
149 br i1 %i65, label %bb3, label %bb66
152 %i32 = add nsw i32 %i7, -1
153 %i33 = add nsw i32 %i8, -1
154 %i34 = getelementptr inbounds i8, i8* %i4, i64 -15
155 %i35 = icmp eq i8 %i5, 77
156 br i1 %i35, label %bb59, label %bb41
158 bb41: ; preds = %bb31
159 tail call void @baz()
162 bb43: ; preds = %bb41, %bb21
163 %i44 = phi i8* [ %i34, %bb41 ], [ %i4, %bb21 ]
164 %i45 = phi i32 [ %i33, %bb41 ], [ %i8, %bb21 ]
165 %i46 = phi i8 [ 77, %bb41 ], [ %i5, %bb21 ]
166 %i47 = phi i32 [ %i32, %bb41 ], [ %i7, %bb21 ]
167 %i48 = phi i32 [ 2, %bb41 ], [ %i6, %bb21 ]
168 tail call void @baz()
169 switch i8 %i5, label %bb59 [
174 bb49: ; preds = %bb43, %bb43
175 tail call void @baz()
178 bb66: ; preds = %bb59