llvm/test/Transforms/LoopUnroll/runtime-loop-multiexit-dom-verify.ll

   1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
   2 ; RUN: opt < %s -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=false -unroll-runtime-multi-exit=true -unroll-count=4  -verify-dom-info -S | FileCheck %s
   3
   4 ; REQUIRES: asserts
   5 ; The tests below are for verifying dom tree after runtime unrolling
   6 ; with multiple exit/exiting blocks.
   7
   8 ; We explicitly set the unroll count so that expensiveTripCount computation is allowed.
   9
  10 ; mergedexit block has edges from loop exit blocks.
  11 define i64 @test1() {
  12 ; CHECK-LABEL: @test1(
  13 ; CHECK-NEXT:  entry:
  14 ; CHECK-NEXT:    br label [[PREHEADER:%.*]]
  15 ; CHECK:       preheader:
  16 ; CHECK-NEXT:    [[TRIP:%.*]] = zext i32 undef to i64
  17 ; CHECK-NEXT:    br label [[HEADER:%.*]]
  18 ; CHECK:       header:
  19 ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ]
  20 ; CHECK-NEXT:    [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
  21 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
  22 ; CHECK-NEXT:    br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
  23 ; CHECK:       latch:
  24 ; CHECK-NEXT:    [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
  25 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
  26 ; CHECK-NEXT:    br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
  27 ; CHECK:       headerexit:
  28 ; CHECK-NEXT:    [[ADDPHI:%.*]] = phi i64 [ [[ADD_IV]], [[HEADER]] ], [ [[ADD_IV_1:%.*]], [[HEADER_1]] ], [ [[ADD_IV_2:%.*]], [[HEADER_2:%.*]] ], [ [[ADD_IV_3]], [[HEADER_3:%.*]] ]
  29 ; CHECK-NEXT:    br label [[MERGEDEXIT:%.*]]
  30 ; CHECK:       latchexit:
  31 ; CHECK-NEXT:    [[SHFTPHI:%.*]] = phi i64 [ [[SHFT]], [[LATCH]] ], [ [[SHFT_1:%.*]], [[LATCH_1:%.*]] ], [ [[SHFT_2:%.*]], [[LATCH_2:%.*]] ], [ [[SHFT_3:%.*]], [[LATCH_3]] ]
  32 ; CHECK-NEXT:    br label [[MERGEDEXIT]]
  33 ; CHECK:       mergedexit:
  34 ; CHECK-NEXT:    [[RETVAL:%.*]] = phi i64 [ [[ADDPHI]], [[HEADEREXIT]] ], [ [[SHFTPHI]], [[LATCHEXIT]] ]
  35 ; CHECK-NEXT:    ret i64 [[RETVAL]]
  36 ; CHECK:       header.1:
  37 ; CHECK-NEXT:    [[ADD_IV_1]] = add nuw nsw i64 [[ADD_IV]], 2
  38 ; CHECK-NEXT:    [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
  39 ; CHECK-NEXT:    br i1 [[CMP1_1]], label [[LATCH_1]], label [[HEADEREXIT]]
  40 ; CHECK:       latch.1:
  41 ; CHECK-NEXT:    [[SHFT_1]] = ashr i64 [[ADD_IV_1]], 1
  42 ; CHECK-NEXT:    [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
  43 ; CHECK-NEXT:    br i1 [[CMP2_1]], label [[HEADER_2]], label [[LATCHEXIT]]
  44 ; CHECK:       header.2:
  45 ; CHECK-NEXT:    [[ADD_IV_2]] = add nuw nsw i64 [[ADD_IV_1]], 2
  46 ; CHECK-NEXT:    [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
  47 ; CHECK-NEXT:    br i1 [[CMP1_2]], label [[LATCH_2]], label [[HEADEREXIT]]
  48 ; CHECK:       latch.2:
  49 ; CHECK-NEXT:    [[SHFT_2]] = ashr i64 [[ADD_IV_2]], 1
  50 ; CHECK-NEXT:    [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
  51 ; CHECK-NEXT:    br i1 [[CMP2_2]], label [[HEADER_3]], label [[LATCHEXIT]]
  52 ; CHECK:       header.3:
  53 ; CHECK-NEXT:    [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2
  54 ; CHECK-NEXT:    [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
  55 ; CHECK-NEXT:    br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
  56 ; CHECK:       latch.3:
  57 ; CHECK-NEXT:    [[SHFT_3]] = ashr i64 [[ADD_IV_3]], 1
  58 ; CHECK-NEXT:    [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
  59 ; CHECK-NEXT:    br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP0:![0-9]+]]
  60 ;
  61 entry:
  62   br label %preheader
  63
  64 preheader:                                              ; preds = %bb
  65   %trip = zext i32 undef to i64
  66   br label %header
  67
  68 header:                                              ; preds = %latch, %preheader
  69   %iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ]
  70   %add.iv = add nuw nsw i64 %iv, 2
  71   %cmp1 = icmp ult i64 %add.iv, %trip
  72   br i1 %cmp1, label %latch, label %headerexit
  73
  74 latch:                                             ; preds = %header
  75   %shft = ashr i64 %add.iv, 1
  76   %cmp2 = icmp ult i64 %shft, %trip
  77   br i1 %cmp2, label %header, label %latchexit
  78
  79 headerexit:                                              ; preds = %header
  80   %addphi = phi i64 [ %add.iv, %header ]
  81   br label %mergedexit
  82
  83 latchexit:                                              ; preds = %latch
  84   %shftphi = phi i64 [ %shft, %latch ]
  85   br label %mergedexit
  86
  87 mergedexit:                                              ; preds = %latchexit, %headerexit
  88   %retval = phi i64 [ %addphi, %headerexit ], [ %shftphi, %latchexit ]
  89   ret i64 %retval
  90 }
  91
  92 ; mergedexit has edges from loop exit blocks and a block outside the loop.
  93 define  void @test2(i1 %cond, i32 %n) {
  94 ; CHECK-LABEL: @test2(
  95 ; CHECK-NEXT:  entry:
  96 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[PREHEADER:%.*]], label [[MERGEDEXIT:%.*]]
  97 ; CHECK:       preheader:
  98 ; CHECK-NEXT:    [[TRIP:%.*]] = zext i32 [[N:%.*]] to i64
  99 ; CHECK-NEXT:    br label [[HEADER:%.*]]
 100 ; CHECK:       header:
 101 ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ]
 102 ; CHECK-NEXT:    [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
 103 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
 104 ; CHECK-NEXT:    br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
 105 ; CHECK:       latch:
 106 ; CHECK-NEXT:    [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
 107 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
 108 ; CHECK-NEXT:    br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
 109 ; CHECK:       headerexit:
 110 ; CHECK-NEXT:    br label [[MERGEDEXIT]]
 111 ; CHECK:       latchexit:
 112 ; CHECK-NEXT:    br label [[MERGEDEXIT]]
 113 ; CHECK:       mergedexit:
 114 ; CHECK-NEXT:    ret void
 115 ; CHECK:       header.1:
 116 ; CHECK-NEXT:    [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2
 117 ; CHECK-NEXT:    [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
 118 ; CHECK-NEXT:    br i1 [[CMP1_1]], label [[LATCH_1:%.*]], label [[HEADEREXIT]]
 119 ; CHECK:       latch.1:
 120 ; CHECK-NEXT:    [[SHFT_1:%.*]] = ashr i64 [[ADD_IV_1]], 1
 121 ; CHECK-NEXT:    [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
 122 ; CHECK-NEXT:    br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
 123 ; CHECK:       header.2:
 124 ; CHECK-NEXT:    [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2
 125 ; CHECK-NEXT:    [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
 126 ; CHECK-NEXT:    br i1 [[CMP1_2]], label [[LATCH_2:%.*]], label [[HEADEREXIT]]
 127 ; CHECK:       latch.2:
 128 ; CHECK-NEXT:    [[SHFT_2:%.*]] = ashr i64 [[ADD_IV_2]], 1
 129 ; CHECK-NEXT:    [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
 130 ; CHECK-NEXT:    br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
 131 ; CHECK:       header.3:
 132 ; CHECK-NEXT:    [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2
 133 ; CHECK-NEXT:    [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
 134 ; CHECK-NEXT:    br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
 135 ; CHECK:       latch.3:
 136 ; CHECK-NEXT:    [[SHFT_3:%.*]] = ashr i64 [[ADD_IV_3]], 1
 137 ; CHECK-NEXT:    [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
 138 ; CHECK-NEXT:    br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP2:![0-9]+]]
 139 ;
 140 entry:
 141   br i1 %cond, label %preheader, label %mergedexit
 142
 143 preheader:                                              ; preds = %entry
 144   %trip = zext i32 %n to i64
 145   br label %header
 146
 147 header:                                              ; preds = %latch, %preheader
 148   %iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ]
 149   %add.iv = add nuw nsw i64 %iv, 2
 150   %cmp1 = icmp ult i64 %add.iv, %trip
 151   br i1 %cmp1, label %latch, label %headerexit
 152
 153 latch:                                             ; preds = %header
 154   %shft = ashr i64 %add.iv, 1
 155   %cmp2 = icmp ult i64 %shft, %trip
 156   br i1 %cmp2, label %header, label %latchexit
 157
 158 headerexit:                                              ; preds = %header
 159   br label %mergedexit
 160
 161 latchexit:                                              ; preds = %latch
 162   br label %mergedexit
 163
 164 mergedexit:                                              ; preds = %latchexit, %headerexit, %entry
 165   ret void
 166 }
 167
 168
 169 ; exitsucc is from loop exit block only.
 170 define i64 @test3(i32 %n) {
 171 ; CHECK-LABEL: @test3(
 172 ; CHECK-NEXT:  entry:
 173 ; CHECK-NEXT:    br label [[PREHEADER:%.*]]
 174 ; CHECK:       preheader:
 175 ; CHECK-NEXT:    [[TRIP:%.*]] = zext i32 [[N:%.*]] to i64
 176 ; CHECK-NEXT:    br label [[HEADER:%.*]]
 177 ; CHECK:       header:
 178 ; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 2, [[PREHEADER]] ], [ [[ADD_IV_3:%.*]], [[LATCH_3:%.*]] ]
 179 ; CHECK-NEXT:    [[ADD_IV:%.*]] = add nuw nsw i64 [[IV]], 2
 180 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ult i64 [[ADD_IV]], [[TRIP]]
 181 ; CHECK-NEXT:    br i1 [[CMP1]], label [[LATCH:%.*]], label [[HEADEREXIT:%.*]]
 182 ; CHECK:       latch:
 183 ; CHECK-NEXT:    [[SHFT:%.*]] = ashr i64 [[ADD_IV]], 1
 184 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ult i64 [[SHFT]], [[TRIP]]
 185 ; CHECK-NEXT:    br i1 [[CMP2]], label [[HEADER_1:%.*]], label [[LATCHEXIT:%.*]]
 186 ; CHECK:       headerexit:
 187 ; CHECK-NEXT:    br label [[EXITSUCC:%.*]]
 188 ; CHECK:       latchexit:
 189 ; CHECK-NEXT:    [[SHFTPHI:%.*]] = phi i64 [ [[SHFT]], [[LATCH]] ], [ [[SHFT_1:%.*]], [[LATCH_1:%.*]] ], [ [[SHFT_2:%.*]], [[LATCH_2:%.*]] ], [ [[SHFT_3:%.*]], [[LATCH_3]] ]
 190 ; CHECK-NEXT:    ret i64 [[SHFTPHI]]
 191 ; CHECK:       exitsucc:
 192 ; CHECK-NEXT:    ret i64 96
 193 ; CHECK:       header.1:
 194 ; CHECK-NEXT:    [[ADD_IV_1:%.*]] = add nuw nsw i64 [[ADD_IV]], 2
 195 ; CHECK-NEXT:    [[CMP1_1:%.*]] = icmp ult i64 [[ADD_IV_1]], [[TRIP]]
 196 ; CHECK-NEXT:    br i1 [[CMP1_1]], label [[LATCH_1]], label [[HEADEREXIT]]
 197 ; CHECK:       latch.1:
 198 ; CHECK-NEXT:    [[SHFT_1]] = ashr i64 [[ADD_IV_1]], 1
 199 ; CHECK-NEXT:    [[CMP2_1:%.*]] = icmp ult i64 [[SHFT_1]], [[TRIP]]
 200 ; CHECK-NEXT:    br i1 [[CMP2_1]], label [[HEADER_2:%.*]], label [[LATCHEXIT]]
 201 ; CHECK:       header.2:
 202 ; CHECK-NEXT:    [[ADD_IV_2:%.*]] = add nuw nsw i64 [[ADD_IV_1]], 2
 203 ; CHECK-NEXT:    [[CMP1_2:%.*]] = icmp ult i64 [[ADD_IV_2]], [[TRIP]]
 204 ; CHECK-NEXT:    br i1 [[CMP1_2]], label [[LATCH_2]], label [[HEADEREXIT]]
 205 ; CHECK:       latch.2:
 206 ; CHECK-NEXT:    [[SHFT_2]] = ashr i64 [[ADD_IV_2]], 1
 207 ; CHECK-NEXT:    [[CMP2_2:%.*]] = icmp ult i64 [[SHFT_2]], [[TRIP]]
 208 ; CHECK-NEXT:    br i1 [[CMP2_2]], label [[HEADER_3:%.*]], label [[LATCHEXIT]]
 209 ; CHECK:       header.3:
 210 ; CHECK-NEXT:    [[ADD_IV_3]] = add nuw nsw i64 [[ADD_IV_2]], 2
 211 ; CHECK-NEXT:    [[CMP1_3:%.*]] = icmp ult i64 [[ADD_IV_3]], [[TRIP]]
 212 ; CHECK-NEXT:    br i1 [[CMP1_3]], label [[LATCH_3]], label [[HEADEREXIT]]
 213 ; CHECK:       latch.3:
 214 ; CHECK-NEXT:    [[SHFT_3]] = ashr i64 [[ADD_IV_3]], 1
 215 ; CHECK-NEXT:    [[CMP2_3:%.*]] = icmp ult i64 [[SHFT_3]], [[TRIP]]
 216 ; CHECK-NEXT:    br i1 [[CMP2_3]], label [[HEADER]], label [[LATCHEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
 217 ;
 218 entry:
 219   br label %preheader
 220
 221 preheader:                                              ; preds = %bb
 222   %trip = zext i32 %n to i64
 223   br label %header
 224
 225 header:                                              ; preds = %latch, %preheader
 226   %iv = phi i64 [ 2, %preheader ], [ %add.iv, %latch ]
 227   %add.iv = add nuw nsw i64 %iv, 2
 228   %cmp1 = icmp ult i64 %add.iv, %trip
 229   br i1 %cmp1, label %latch, label %headerexit
 230
 231 latch:                                             ; preds = %header
 232   %shft = ashr i64 %add.iv, 1
 233   %cmp2 = icmp ult i64 %shft, %trip
 234   br i1 %cmp2, label %header, label %latchexit
 235
 236 headerexit:                                              ; preds = %header
 237   br label %exitsucc
 238
 239 latchexit:                                              ; preds = %latch
 240   %shftphi = phi i64 [ %shft, %latch ]
 241   ret i64 %shftphi
 242
 243 exitsucc:                                              ; preds = %headerexit
 244   ret i64 96
 245 }
 246
 247 ; exit block (%default) has an exiting block and another exit block as predecessors.
 248 define void @test4(i16 %c3) {
 249 ; CHECK-LABEL: @test4(
 250 ; CHECK-NEXT:  preheader:
 251 ; CHECK-NEXT:    [[C1:%.*]] = zext i32 undef to i64
 252 ; CHECK-NEXT:    [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[C1]], i64 1)
 253 ; CHECK-NEXT:    [[TMP0:%.*]] = add nsw i64 [[UMAX]], -1
 254 ; CHECK-NEXT:    [[XTRAITER:%.*]] = and i64 [[UMAX]], 3
 255 ; CHECK-NEXT:    [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
 256 ; CHECK-NEXT:    br i1 [[LCMP_MOD]], label [[HEADER_PROL_PREHEADER:%.*]], label [[HEADER_PROL_LOOPEXIT:%.*]]
 257 ; CHECK:       header.prol.preheader:
 258 ; CHECK-NEXT:    br label [[HEADER_PROL:%.*]]
 259 ; CHECK:       header.prol:
 260 ; CHECK-NEXT:    [[INDVARS_IV_PROL:%.*]] = phi i64 [ 0, [[HEADER_PROL_PREHEADER]] ], [ [[INDVARS_IV_NEXT_PROL:%.*]], [[LATCH_PROL:%.*]] ]
 261 ; CHECK-NEXT:    [[PROL_ITER:%.*]] = phi i64 [ [[XTRAITER]], [[HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[LATCH_PROL]] ]
 262 ; CHECK-NEXT:    br label [[EXITING_PROL:%.*]]
 263 ; CHECK:       exiting.prol:
 264 ; CHECK-NEXT:    switch i16 [[C3:%.*]], label [[DEFAULT_LOOPEXIT_LOOPEXIT1:%.*]] [
 265 ; CHECK-NEXT:    i16 45, label [[OTHEREXIT_LOOPEXIT2:%.*]]
 266 ; CHECK-NEXT:    i16 95, label [[LATCH_PROL]]
 267 ; CHECK-NEXT:    ]
 268 ; CHECK:       latch.prol:
 269 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_PROL]] = add nuw nsw i64 [[INDVARS_IV_PROL]], 1
 270 ; CHECK-NEXT:    [[C2_PROL:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_PROL]], [[C1]]
 271 ; CHECK-NEXT:    [[PROL_ITER_SUB]] = sub i64 [[PROL_ITER]], 1
 272 ; CHECK-NEXT:    [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_SUB]], 0
 273 ; CHECK-NEXT:    br i1 [[PROL_ITER_CMP]], label [[HEADER_PROL]], label [[HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP4:![0-9]+]]
 274 ; CHECK:       header.prol.loopexit.unr-lcssa:
 275 ; CHECK-NEXT:    [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[LATCH_PROL]] ]
 276 ; CHECK-NEXT:    br label [[HEADER_PROL_LOOPEXIT]]
 277 ; CHECK:       header.prol.loopexit:
 278 ; CHECK-NEXT:    [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[PREHEADER:%.*]] ], [ [[INDVARS_IV_UNR_PH]], [[HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
 279 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 3
 280 ; CHECK-NEXT:    br i1 [[TMP1]], label [[LATCHEXIT:%.*]], label [[PREHEADER_NEW:%.*]]
 281 ; CHECK:       preheader.new:
 282 ; CHECK-NEXT:    br label [[HEADER:%.*]]
 283 ; CHECK:       header:
 284 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ]
 285 ; CHECK-NEXT:    br label [[EXITING:%.*]]
 286 ; CHECK:       exiting:
 287 ; CHECK-NEXT:    switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT:%.*]] [
 288 ; CHECK-NEXT:    i16 45, label [[OTHEREXIT_LOOPEXIT:%.*]]
 289 ; CHECK-NEXT:    i16 95, label [[LATCH:%.*]]
 290 ; CHECK-NEXT:    ]
 291 ; CHECK:       latch:
 292 ; CHECK-NEXT:    [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
 293 ; CHECK-NEXT:    br label [[EXITING_1:%.*]]
 294 ; CHECK:       latchexit.unr-lcssa:
 295 ; CHECK-NEXT:    br label [[LATCHEXIT]]
 296 ; CHECK:       latchexit:
 297 ; CHECK-NEXT:    ret void
 298 ; CHECK:       default.loopexit.loopexit:
 299 ; CHECK-NEXT:    br label [[DEFAULT_LOOPEXIT:%.*]]
 300 ; CHECK:       default.loopexit.loopexit1:
 301 ; CHECK-NEXT:    br label [[DEFAULT_LOOPEXIT]]
 302 ; CHECK:       default.loopexit:
 303 ; CHECK-NEXT:    br label [[DEFAULT:%.*]]
 304 ; CHECK:       default:
 305 ; CHECK-NEXT:    ret void
 306 ; CHECK:       otherexit.loopexit:
 307 ; CHECK-NEXT:    br label [[OTHEREXIT:%.*]]
 308 ; CHECK:       otherexit.loopexit2:
 309 ; CHECK-NEXT:    br label [[OTHEREXIT]]
 310 ; CHECK:       otherexit:
 311 ; CHECK-NEXT:    br label [[DEFAULT]]
 312 ; CHECK:       exiting.1:
 313 ; CHECK-NEXT:    switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
 314 ; CHECK-NEXT:    i16 45, label [[OTHEREXIT_LOOPEXIT]]
 315 ; CHECK-NEXT:    i16 95, label [[LATCH_1:%.*]]
 316 ; CHECK-NEXT:    ]
 317 ; CHECK:       latch.1:
 318 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1
 319 ; CHECK-NEXT:    br label [[EXITING_2:%.*]]
 320 ; CHECK:       exiting.2:
 321 ; CHECK-NEXT:    switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
 322 ; CHECK-NEXT:    i16 45, label [[OTHEREXIT_LOOPEXIT]]
 323 ; CHECK-NEXT:    i16 95, label [[LATCH_2:%.*]]
 324 ; CHECK-NEXT:    ]
 325 ; CHECK:       latch.2:
 326 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1
 327 ; CHECK-NEXT:    br label [[EXITING_3:%.*]]
 328 ; CHECK:       exiting.3:
 329 ; CHECK-NEXT:    switch i16 [[C3]], label [[DEFAULT_LOOPEXIT_LOOPEXIT]] [
 330 ; CHECK-NEXT:    i16 45, label [[OTHEREXIT_LOOPEXIT]]
 331 ; CHECK-NEXT:    i16 95, label [[LATCH_3]]
 332 ; CHECK-NEXT:    ]
 333 ; CHECK:       latch.3:
 334 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1
 335 ; CHECK-NEXT:    [[C2_3:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT_3]], [[C1]]
 336 ; CHECK-NEXT:    br i1 [[C2_3]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP5:![0-9]+]]
 337 ;
 338 preheader:
 339   %c1 = zext i32 undef to i64
 340   br label %header
 341
 342 header:                                       ; preds = %latch, %preheader
 343   %indvars.iv = phi i64 [ 0, %preheader ], [ %indvars.iv.next, %latch ]
 344   br label %exiting
 345
 346 exiting:                                           ; preds = %header
 347   switch i16 %c3, label %default [
 348   i16 45, label %otherexit
 349   i16 95, label %latch
 350   ]
 351
 352 latch:                                          ; preds = %exiting
 353   %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
 354   %c2 = icmp ult i64 %indvars.iv.next, %c1
 355   br i1 %c2, label %header, label %latchexit
 356
 357 latchexit:                                          ; preds = %latch
 358   ret void
 359
 360 default:                                          ; preds = %otherexit, %exiting
 361   ret void
 362
 363 otherexit:                                           ; preds = %exiting
 364   br label %default
 365 }
 366
 367 ; exit block (%exitB) has an exiting block and another exit block as predecessors.
 368 ; exiting block comes from inner loop.
 369 define void @test5(i1 %c) {
 370 ; CHECK-LABEL: @test5(
 371 ; CHECK-NEXT:  bb:
 372 ; CHECK-NEXT:    [[TMP:%.*]] = icmp sgt i32 undef, 79
 373 ; CHECK-NEXT:    br i1 [[TMP]], label [[OUTERLATCHEXIT:%.*]], label [[BB1:%.*]]
 374 ; CHECK:       bb1:
 375 ; CHECK-NEXT:    br i1 false, label [[OUTERH_PROL_PREHEADER:%.*]], label [[OUTERH_PROL_LOOPEXIT:%.*]]
 376 ; CHECK:       outerH.prol.preheader:
 377 ; CHECK-NEXT:    br label [[OUTERH_PROL:%.*]]
 378 ; CHECK:       outerH.prol:
 379 ; CHECK-NEXT:    [[TMP4_PROL:%.*]] = phi i32 [ [[TMP6_PROL:%.*]], [[OUTERLATCH_PROL:%.*]] ], [ undef, [[OUTERH_PROL_PREHEADER]] ]
 380 ; CHECK-NEXT:    [[PROL_ITER:%.*]] = phi i32 [ 0, [[OUTERH_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[OUTERLATCH_PROL]] ]
 381 ; CHECK-NEXT:    br label [[INNERH_PROL:%.*]]
 382 ; CHECK:       innerH.prol:
 383 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[INNEREXITING_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1:%.*]]
 384 ; CHECK:       innerexiting.prol:
 385 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2:%.*]]
 386 ; CHECK:       innerLatch.prol:
 387 ; CHECK-NEXT:    br i1 false, label [[INNERH_1_PROL:%.*]], label [[OUTERLATCH_PROL]]
 388 ; CHECK:       innerH.1.prol:
 389 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_1_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]]
 390 ; CHECK:       innerexiting.1.prol:
 391 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_1_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]]
 392 ; CHECK:       innerLatch.1.prol:
 393 ; CHECK-NEXT:    br i1 false, label [[INNERH_2_PROL:%.*]], label [[OUTERLATCH_PROL]]
 394 ; CHECK:       innerH.2.prol:
 395 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_2_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]]
 396 ; CHECK:       innerexiting.2.prol:
 397 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_2_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]]
 398 ; CHECK:       innerLatch.2.prol:
 399 ; CHECK-NEXT:    br i1 false, label [[INNERH_3_PROL:%.*]], label [[OUTERLATCH_PROL]]
 400 ; CHECK:       innerH.3.prol:
 401 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_3_PROL:%.*]], label [[OTHEREXITB_LOOPEXIT1]]
 402 ; CHECK:       innerexiting.3.prol:
 403 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_3_PROL:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT2]]
 404 ; CHECK:       innerLatch.3.prol:
 405 ; CHECK-NEXT:    br i1 false, label [[INNERH_PROL]], label [[OUTERLATCH_PROL]], !llvm.loop [[LOOP6:![0-9]+]]
 406 ; CHECK:       outerLatch.prol:
 407 ; CHECK-NEXT:    [[TMP6_PROL]] = add i32 [[TMP4_PROL]], 1
 408 ; CHECK-NEXT:    [[TMP7_PROL:%.*]] = icmp sgt i32 [[TMP6_PROL]], 79
 409 ; CHECK-NEXT:    [[PROL_ITER_SUB]] = sub i32 [[PROL_ITER]], 1
 410 ; CHECK-NEXT:    [[PROL_ITER_CMP:%.*]] = icmp ne i32 [[PROL_ITER_SUB]], 0
 411 ; CHECK-NEXT:    br i1 [[PROL_ITER_CMP]], label [[OUTERH_PROL]], label [[OUTERH_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP7:![0-9]+]]
 412 ; CHECK:       outerH.prol.loopexit.unr-lcssa:
 413 ; CHECK-NEXT:    [[TMP4_UNR_PH:%.*]] = phi i32 [ [[TMP6_PROL]], [[OUTERLATCH_PROL]] ]
 414 ; CHECK-NEXT:    br label [[OUTERH_PROL_LOOPEXIT]]
 415 ; CHECK:       outerH.prol.loopexit:
 416 ; CHECK-NEXT:    [[TMP4_UNR:%.*]] = phi i32 [ undef, [[BB1]] ], [ [[TMP4_UNR_PH]], [[OUTERH_PROL_LOOPEXIT_UNR_LCSSA]] ]
 417 ; CHECK-NEXT:    br i1 false, label [[OUTERLATCHEXIT_LOOPEXIT:%.*]], label [[BB1_NEW:%.*]]
 418 ; CHECK:       bb1.new:
 419 ; CHECK-NEXT:    br label [[OUTERH:%.*]]
 420 ; CHECK:       outerH:
 421 ; CHECK-NEXT:    [[TMP4:%.*]] = phi i32 [ [[TMP4_UNR]], [[BB1_NEW]] ], [ [[TMP6_3:%.*]], [[OUTERLATCH_3:%.*]] ]
 422 ; CHECK-NEXT:    br label [[INNERH:%.*]]
 423 ; CHECK:       innerH:
 424 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT:%.*]]
 425 ; CHECK:       innerexiting:
 426 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT:%.*]]
 427 ; CHECK:       innerLatch:
 428 ; CHECK-NEXT:    br i1 false, label [[INNERH_1:%.*]], label [[OUTERLATCH:%.*]]
 429 ; CHECK:       outerLatch:
 430 ; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[TMP4]], 1
 431 ; CHECK-NEXT:    br label [[INNERH_13:%.*]]
 432 ; CHECK:       outerLatchExit.loopexit.unr-lcssa:
 433 ; CHECK-NEXT:    br label [[OUTERLATCHEXIT_LOOPEXIT]]
 434 ; CHECK:       outerLatchExit.loopexit:
 435 ; CHECK-NEXT:    br label [[OUTERLATCHEXIT]]
 436 ; CHECK:       outerLatchExit:
 437 ; CHECK-NEXT:    ret void
 438 ; CHECK:       exitB.loopexit.loopexit.loopexit:
 439 ; CHECK-NEXT:    br label [[EXITB_LOOPEXIT_LOOPEXIT:%.*]]
 440 ; CHECK:       exitB.loopexit.loopexit.loopexit13:
 441 ; CHECK-NEXT:    br label [[EXITB_LOOPEXIT_LOOPEXIT]]
 442 ; CHECK:       exitB.loopexit.loopexit.loopexit15:
 443 ; CHECK-NEXT:    br label [[EXITB_LOOPEXIT_LOOPEXIT]]
 444 ; CHECK:       exitB.loopexit.loopexit.loopexit17:
 445 ; CHECK-NEXT:    br label [[EXITB_LOOPEXIT_LOOPEXIT]]
 446 ; CHECK:       exitB.loopexit.loopexit:
 447 ; CHECK-NEXT:    br label [[EXITB_LOOPEXIT:%.*]]
 448 ; CHECK:       exitB.loopexit.loopexit2:
 449 ; CHECK-NEXT:    br label [[EXITB_LOOPEXIT]]
 450 ; CHECK:       exitB.loopexit:
 451 ; CHECK-NEXT:    br label [[EXITB:%.*]]
 452 ; CHECK:       exitB:
 453 ; CHECK-NEXT:    ret void
 454 ; CHECK:       otherexitB.loopexit.loopexit:
 455 ; CHECK-NEXT:    br label [[OTHEREXITB_LOOPEXIT:%.*]]
 456 ; CHECK:       otherexitB.loopexit.loopexit12:
 457 ; CHECK-NEXT:    br label [[OTHEREXITB_LOOPEXIT]]
 458 ; CHECK:       otherexitB.loopexit.loopexit14:
 459 ; CHECK-NEXT:    br label [[OTHEREXITB_LOOPEXIT]]
 460 ; CHECK:       otherexitB.loopexit.loopexit16:
 461 ; CHECK-NEXT:    br label [[OTHEREXITB_LOOPEXIT]]
 462 ; CHECK:       otherexitB.loopexit:
 463 ; CHECK-NEXT:    br label [[OTHEREXITB:%.*]]
 464 ; CHECK:       otherexitB.loopexit1:
 465 ; CHECK-NEXT:    br label [[OTHEREXITB]]
 466 ; CHECK:       otherexitB:
 467 ; CHECK-NEXT:    br label [[EXITB]]
 468 ; CHECK:       innerH.1:
 469 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
 470 ; CHECK:       innerexiting.1:
 471 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
 472 ; CHECK:       innerLatch.1:
 473 ; CHECK-NEXT:    br i1 false, label [[INNERH_2:%.*]], label [[OUTERLATCH]]
 474 ; CHECK:       innerH.2:
 475 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
 476 ; CHECK:       innerexiting.2:
 477 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
 478 ; CHECK:       innerLatch.2:
 479 ; CHECK-NEXT:    br i1 false, label [[INNERH_3:%.*]], label [[OUTERLATCH]]
 480 ; CHECK:       innerH.3:
 481 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT]]
 482 ; CHECK:       innerexiting.3:
 483 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT]]
 484 ; CHECK:       innerLatch.3:
 485 ; CHECK-NEXT:    br i1 false, label [[INNERH]], label [[OUTERLATCH]], !llvm.loop [[LOOP6]]
 486 ; CHECK:       innerH.13:
 487 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_14:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12:%.*]]
 488 ; CHECK:       innerexiting.14:
 489 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_15:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13:%.*]]
 490 ; CHECK:       innerLatch.15:
 491 ; CHECK-NEXT:    br i1 false, label [[INNERH_1_1:%.*]], label [[OUTERLATCH_1:%.*]]
 492 ; CHECK:       innerH.1.1:
 493 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_1_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12]]
 494 ; CHECK:       innerexiting.1.1:
 495 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_1_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13]]
 496 ; CHECK:       innerLatch.1.1:
 497 ; CHECK-NEXT:    br i1 false, label [[INNERH_2_1:%.*]], label [[OUTERLATCH_1]]
 498 ; CHECK:       innerH.2.1:
 499 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_2_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12]]
 500 ; CHECK:       innerexiting.2.1:
 501 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_2_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13]]
 502 ; CHECK:       innerLatch.2.1:
 503 ; CHECK-NEXT:    br i1 false, label [[INNERH_3_1:%.*]], label [[OUTERLATCH_1]]
 504 ; CHECK:       innerH.3.1:
 505 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_3_1:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT12]]
 506 ; CHECK:       innerexiting.3.1:
 507 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_3_1:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT13]]
 508 ; CHECK:       innerLatch.3.1:
 509 ; CHECK-NEXT:    br i1 false, label [[INNERH_13]], label [[OUTERLATCH_1]], !llvm.loop [[LOOP6]]
 510 ; CHECK:       outerLatch.1:
 511 ; CHECK-NEXT:    [[TMP6_1:%.*]] = add i32 [[TMP6]], 1
 512 ; CHECK-NEXT:    br label [[INNERH_26:%.*]]
 513 ; CHECK:       innerH.26:
 514 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_27:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14:%.*]]
 515 ; CHECK:       innerexiting.27:
 516 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_28:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15:%.*]]
 517 ; CHECK:       innerLatch.28:
 518 ; CHECK-NEXT:    br i1 false, label [[INNERH_1_2:%.*]], label [[OUTERLATCH_2:%.*]]
 519 ; CHECK:       innerH.1.2:
 520 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_1_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14]]
 521 ; CHECK:       innerexiting.1.2:
 522 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_1_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15]]
 523 ; CHECK:       innerLatch.1.2:
 524 ; CHECK-NEXT:    br i1 false, label [[INNERH_2_2:%.*]], label [[OUTERLATCH_2]]
 525 ; CHECK:       innerH.2.2:
 526 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_2_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14]]
 527 ; CHECK:       innerexiting.2.2:
 528 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_2_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15]]
 529 ; CHECK:       innerLatch.2.2:
 530 ; CHECK-NEXT:    br i1 false, label [[INNERH_3_2:%.*]], label [[OUTERLATCH_2]]
 531 ; CHECK:       innerH.3.2:
 532 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_3_2:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT14]]
 533 ; CHECK:       innerexiting.3.2:
 534 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_3_2:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT15]]
 535 ; CHECK:       innerLatch.3.2:
 536 ; CHECK-NEXT:    br i1 false, label [[INNERH_26]], label [[OUTERLATCH_2]], !llvm.loop [[LOOP6]]
 537 ; CHECK:       outerLatch.2:
 538 ; CHECK-NEXT:    [[TMP6_2:%.*]] = add i32 [[TMP6_1]], 1
 539 ; CHECK-NEXT:    br label [[INNERH_39:%.*]]
 540 ; CHECK:       innerH.39:
 541 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_310:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16:%.*]]
 542 ; CHECK:       innerexiting.310:
 543 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_311:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17:%.*]]
 544 ; CHECK:       innerLatch.311:
 545 ; CHECK-NEXT:    br i1 false, label [[INNERH_1_3:%.*]], label [[OUTERLATCH_3]]
 546 ; CHECK:       innerH.1.3:
 547 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_1_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16]]
 548 ; CHECK:       innerexiting.1.3:
 549 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_1_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17]]
 550 ; CHECK:       innerLatch.1.3:
 551 ; CHECK-NEXT:    br i1 false, label [[INNERH_2_3:%.*]], label [[OUTERLATCH_3]]
 552 ; CHECK:       innerH.2.3:
 553 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_2_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16]]
 554 ; CHECK:       innerexiting.2.3:
 555 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_2_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17]]
 556 ; CHECK:       innerLatch.2.3:
 557 ; CHECK-NEXT:    br i1 false, label [[INNERH_3_3:%.*]], label [[OUTERLATCH_3]]
 558 ; CHECK:       innerH.3.3:
 559 ; CHECK-NEXT:    br i1 [[C]], label [[INNEREXITING_3_3:%.*]], label [[OTHEREXITB_LOOPEXIT_LOOPEXIT16]]
 560 ; CHECK:       innerexiting.3.3:
 561 ; CHECK-NEXT:    br i1 [[C]], label [[INNERLATCH_3_3:%.*]], label [[EXITB_LOOPEXIT_LOOPEXIT_LOOPEXIT17]]
 562 ; CHECK:       innerLatch.3.3:
 563 ; CHECK-NEXT:    br i1 false, label [[INNERH_39]], label [[OUTERLATCH_3]], !llvm.loop [[LOOP6]]
 564 ; CHECK:       outerLatch.3:
 565 ; CHECK-NEXT:    [[TMP6_3]] = add i32 [[TMP6_2]], 1
 566 ; CHECK-NEXT:    [[TMP7_3:%.*]] = icmp sgt i32 [[TMP6_3]], 79
 567 ; CHECK-NEXT:    br i1 [[TMP7_3]], label [[OUTERLATCHEXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[OUTERH]], !llvm.loop [[LOOP8:![0-9]+]]
 568 ;
 569 bb:
 570   %tmp = icmp sgt i32 undef, 79
 571   br i1 %tmp, label %outerLatchExit, label %bb1
 572
 573 bb1:                                              ; preds = %bb
 574   br label %outerH
 575
 576 outerH:                                              ; preds = %outerLatch, %bb1
 577   %tmp4 = phi i32 [ %tmp6, %outerLatch ], [ undef, %bb1 ]
 578   br label %innerH
 579
 580 innerH:                                              ; preds = %innerLatch, %outerH
 581   br i1 %c, label %innerexiting, label %otherexitB
 582
 583 innerexiting:                                             ; preds = %innerH
 584   br i1 %c, label %innerLatch, label %exitB
 585
 586 innerLatch:                                             ; preds = %innerexiting
 587   %tmp13 = fcmp olt double undef, 2.000000e+00
 588   br i1 %tmp13, label %innerH, label %outerLatch
 589
 590 outerLatch:                                              ; preds = %innerLatch
 591   %tmp6 = add i32 %tmp4, 1
 592   %tmp7 = icmp sgt i32 %tmp6, 79
 593   br i1 %tmp7, label %outerLatchExit, label %outerH
 594
 595 outerLatchExit:                                              ; preds = %outerLatch, %bb
 596   ret void
 597
 598 exitB:                                             ; preds = %innerexiting, %otherexitB
 599   ret void
 600
 601 otherexitB:                                              ; preds = %innerH
 602   br label %exitB
 603
 604 }
 605
 606 ; Blocks reachable from exits (not_zero44) have the IDom as the block within the loop (Header).
 607 ; Update the IDom to the preheader.
 608 define void @test6(i1 %c) {
 609 ; CHECK-LABEL: @test6(
 610 ; CHECK-NEXT:  entry:
 611 ; CHECK-NEXT:    [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 undef, i64 616)
 612 ; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[SMAX]], -1
 613 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 [[TMP0]], undef
 614 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP1]], 1
 615 ; CHECK-NEXT:    [[TMP3:%.*]] = add nuw i64 [[TMP2]], 1
 616 ; CHECK-NEXT:    [[XTRAITER:%.*]] = and i64 [[TMP3]], 3
 617 ; CHECK-NEXT:    [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
 618 ; CHECK-NEXT:    br i1 [[LCMP_MOD]], label [[HEADER_PROL_PREHEADER:%.*]], label [[HEADER_PROL_LOOPEXIT:%.*]]
 619 ; CHECK:       header.prol.preheader:
 620 ; CHECK-NEXT:    br label [[HEADER_PROL:%.*]]
 621 ; CHECK:       header.prol:
 622 ; CHECK-NEXT:    [[INDVARS_IV_PROL:%.*]] = phi i64 [ undef, [[HEADER_PROL_PREHEADER]] ], [ [[INDVARS_IV_NEXT_PROL:%.*]], [[LATCH_PROL:%.*]] ]
 623 ; CHECK-NEXT:    [[PROL_ITER:%.*]] = phi i64 [ [[XTRAITER]], [[HEADER_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[LATCH_PROL]] ]
 624 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[LATCH_PROL]], label [[OTHEREXIT_LOOPEXIT1:%.*]]
 625 ; CHECK:       latch.prol:
 626 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_PROL]] = add nsw i64 [[INDVARS_IV_PROL]], 2
 627 ; CHECK-NEXT:    [[TMP4:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_PROL]], 616
 628 ; CHECK-NEXT:    [[PROL_ITER_SUB]] = sub i64 [[PROL_ITER]], 1
 629 ; CHECK-NEXT:    [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_SUB]], 0
 630 ; CHECK-NEXT:    br i1 [[PROL_ITER_CMP]], label [[HEADER_PROL]], label [[HEADER_PROL_LOOPEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP9:![0-9]+]]
 631 ; CHECK:       header.prol.loopexit.unr-lcssa:
 632 ; CHECK-NEXT:    [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[LATCH_PROL]] ]
 633 ; CHECK-NEXT:    br label [[HEADER_PROL_LOOPEXIT]]
 634 ; CHECK:       header.prol.loopexit:
 635 ; CHECK-NEXT:    [[INDVARS_IV_UNR:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[INDVARS_IV_UNR_PH]], [[HEADER_PROL_LOOPEXIT_UNR_LCSSA]] ]
 636 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp ult i64 [[TMP2]], 3
 637 ; CHECK-NEXT:    br i1 [[TMP5]], label [[LATCHEXIT:%.*]], label [[ENTRY_NEW:%.*]]
 638 ; CHECK:       entry.new:
 639 ; CHECK-NEXT:    br label [[HEADER:%.*]]
 640 ; CHECK:       header:
 641 ; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[ENTRY_NEW]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[LATCH_3:%.*]] ]
 642 ; CHECK-NEXT:    br i1 [[C]], label [[LATCH:%.*]], label [[OTHEREXIT_LOOPEXIT:%.*]]
 643 ; CHECK:       latch:
 644 ; CHECK-NEXT:    [[INDVARS_IV_NEXT:%.*]] = add nsw i64 [[INDVARS_IV]], 2
 645 ; CHECK-NEXT:    br i1 [[C]], label [[LATCH_1:%.*]], label [[OTHEREXIT_LOOPEXIT]]
 646 ; CHECK:       latchexit.unr-lcssa:
 647 ; CHECK-NEXT:    br label [[LATCHEXIT]]
 648 ; CHECK:       latchexit:
 649 ; CHECK-NEXT:    br label [[LATCHEXITSUCC:%.*]]
 650 ; CHECK:       otherexit.loopexit:
 651 ; CHECK-NEXT:    br label [[OTHEREXIT:%.*]]
 652 ; CHECK:       otherexit.loopexit1:
 653 ; CHECK-NEXT:    br label [[OTHEREXIT]]
 654 ; CHECK:       otherexit:
 655 ; CHECK-NEXT:    br label [[OTHEREXITSUCC:%.*]]
 656 ; CHECK:       otherexitsucc:
 657 ; CHECK-NEXT:    br label [[NOT_ZERO44:%.*]]
 658 ; CHECK:       not_zero44:
 659 ; CHECK-NEXT:    unreachable
 660 ; CHECK:       latchexitsucc:
 661 ; CHECK-NEXT:    br label [[NOT_ZERO44]]
 662 ; CHECK:       latch.1:
 663 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_1:%.*]] = add nsw i64 [[INDVARS_IV_NEXT]], 2
 664 ; CHECK-NEXT:    br i1 [[C]], label [[LATCH_2:%.*]], label [[OTHEREXIT_LOOPEXIT]]
 665 ; CHECK:       latch.2:
 666 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_2:%.*]] = add nsw i64 [[INDVARS_IV_NEXT_1]], 2
 667 ; CHECK-NEXT:    br i1 [[C]], label [[LATCH_3]], label [[OTHEREXIT_LOOPEXIT]]
 668 ; CHECK:       latch.3:
 669 ; CHECK-NEXT:    [[INDVARS_IV_NEXT_3]] = add nsw i64 [[INDVARS_IV_NEXT_2]], 2
 670 ; CHECK-NEXT:    [[TMP6:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT_3]], 616
 671 ; CHECK-NEXT:    br i1 [[TMP6]], label [[HEADER]], label [[LATCHEXIT_UNR_LCSSA:%.*]], !llvm.loop [[LOOP10:![0-9]+]]
 672 ;
 673 entry:
 674   br label %header
 675
 676 header:                                          ; preds = %latch, %entry
 677   %indvars.iv = phi i64 [ undef, %entry ], [ %indvars.iv.next, %latch ]
 678   br i1 %c, label %latch, label %otherexit
 679
 680 latch:                                         ; preds = %header
 681   %indvars.iv.next = add nsw i64 %indvars.iv, 2
 682   %0 = icmp slt i64 %indvars.iv.next, 616
 683   br i1 %0, label %header, label %latchexit
 684
 685 latchexit:                                          ; preds = %latch
 686   br label %latchexitsucc
 687
 688 otherexit:                                 ; preds = %header
 689   br label %otherexitsucc
 690
 691 otherexitsucc:                                          ; preds = %otherexit
 692   br label %not_zero44
 693
 694 not_zero44:                                       ; preds = %latchexitsucc, %otherexitsucc
 695   unreachable
 696
 697 latchexitsucc:                                      ; preds = %latchexit
 698   br label %not_zero44
 699 }
 700