| blob | fe3d3e19b8429e8f0d1500a89fa3389577b2c5d5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
4 define void @test(float* %A, i32 %x) {
5 ; CHECK-LABEL: @test(
6 ; CHECK-NEXT: entry:
7 ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
8 ; CHECK: vector.scevcheck:
9 ; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[X:%.*]], 1
10 ; CHECK-NEXT: [[TMP0:%.*]] = or i1 false, [[IDENT_CHECK]]
11 ; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 undef)
12 ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
13 ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
14 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 0, [[MUL_RESULT]]
15 ; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[MUL_RESULT]]
16 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[TMP2]], 0
17 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP1]], 0
18 ; CHECK-NEXT: [[TMP5:%.*]] = select i1 false, i1 [[TMP3]], i1 [[TMP4]]
19 ; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP5]], [[MUL_OVERFLOW]]
20 ; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP0]], [[TMP6]]
21 ; CHECK-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 undef)
22 ; CHECK-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
23 ; CHECK-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
24 ; CHECK-NEXT: [[TMP8:%.*]] = add i32 1, [[MUL_RESULT2]]
25 ; CHECK-NEXT: [[TMP9:%.*]] = sub i32 1, [[MUL_RESULT2]]
26 ; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i32 [[TMP9]], 1
27 ; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP8]], 1
28 ; CHECK-NEXT: [[TMP12:%.*]] = select i1 false, i1 [[TMP10]], i1 [[TMP11]]
29 ; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW3]]
30 ; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]
31 ; CHECK-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
32 ; CHECK: vector.ph:
33 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
34 ; CHECK: vector.body:
35 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
36 ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[INDEX]], 0
37 ; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[TMP15]], 1
38 ; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32
39 ; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[X]]
40 ; CHECK-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
41 ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[TMP19]]
42 ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, float* [[TMP20]], i32 0
43 ; CHECK-NEXT: [[TMP22:%.*]] = bitcast float* [[TMP21]] to <4 x float>*
44 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, <4 x float>* [[TMP22]], align 4
45 ; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[INDEX]] to i32
46 ; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP23]], 0
47 ; CHECK-NEXT: [[TMP25:%.*]] = mul i32 [[TMP24]], [[X]]
48 ; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP25]] to i64
49 ; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[TMP26]]
50 ; CHECK-NEXT: [[TMP28:%.*]] = getelementptr inbounds float, float* [[TMP27]], i32 0
51 ; CHECK-NEXT: [[TMP29:%.*]] = bitcast float* [[TMP28]] to <4 x float>*
52 ; CHECK-NEXT: store <4 x float> [[WIDE_LOAD]], <4 x float>* [[TMP29]], align 4
53 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
54 ; CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], undef
55 ; CHECK-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
56 ; CHECK: middle.block:
57 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 undef, undef
58 ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
59 ; CHECK: scalar.ph:
60 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ undef, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
61 ; CHECK-NEXT: br label [[LOOP:%.*]]
62 ; CHECK: loop:
63 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
64 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
65 ; CHECK-NEXT: [[T_IV_NEXT:%.*]] = trunc i64 [[IV_NEXT]] to i32
66 ; CHECK-NEXT: [[MUL_IV_NEXT:%.*]] = mul i32 [[T_IV_NEXT]], [[X]]
67 ; CHECK-NEXT: [[IDX_1:%.*]] = zext i32 [[MUL_IV_NEXT]] to i64
68 ; CHECK-NEXT: [[ARRAYIDX1215:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[IDX_1]]
69 ; CHECK-NEXT: [[LV:%.*]] = load float, float* [[ARRAYIDX1215]], align 4
70 ; CHECK-NEXT: [[T_IV:%.*]] = trunc i64 [[IV]] to i32
71 ; CHECK-NEXT: [[MUL_IV:%.*]] = mul i32 [[T_IV]], [[X]]
72 ; CHECK-NEXT: [[IDX_2:%.*]] = zext i32 [[MUL_IV]] to i64
73 ; CHECK-NEXT: [[ARRAYIDX1209:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[IDX_2]]
74 ; CHECK-NEXT: store float [[LV]], float* [[ARRAYIDX1209]], align 4
75 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], undef
76 ; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop !2
77 ; CHECK: exit:
78 ; CHECK-NEXT: ret void
79 ;
80 entry:
81 br label %loop
83 loop: ; preds = %loop, %entry
84 %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ]
85 %iv.next = add nuw nsw i64 %iv, 1
86 %t.iv.next = trunc i64 %iv.next to i32
87 %mul.iv.next = mul i32 %t.iv.next, %x
88 %idx.1 = zext i32 %mul.iv.next to i64
89 %arrayidx1215 = getelementptr inbounds float, float* %A, i64 %idx.1
90 %lv = load float, float* %arrayidx1215, align 4
92 %t.iv = trunc i64 %iv to i32
93 %mul.iv = mul i32 %t.iv, %x
94 %idx.2 = zext i32 %mul.iv to i64
95 %arrayidx1209 = getelementptr inbounds float, float* %A, i64 %idx.2
96 store float %lv, float* %arrayidx1209, align 4
97 %ec = icmp eq i64 %iv.next, undef
98 br i1 %ec, label %exit, label %loop
100 exit: ; preds = %loop
101 ret void
102 }