1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -basic-aa -newgvn -S | FileCheck %s
4 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
6 define i1 @patatino(i8* %blah, i32 %choice) {
7 ; CHECK-LABEL: @patatino(
9 ; CHECK-NEXT: br label [[WHILE_COND:%.*]]
11 ; CHECK-NEXT: [[FOO:%.*]] = phi i8* [ [[BLAH:%.*]], [[ENTRY:%.*]] ], [ null, [[WHILE_BODY:%.*]] ]
12 ; CHECK-NEXT: switch i32 [[CHOICE:%.*]], label [[WHILE_BODY]] [
13 ; CHECK-NEXT: i32 -1, label [[WHILE_END:%.*]]
14 ; CHECK-NEXT: i32 40, label [[LAND_END:%.*]]
17 ; CHECK-NEXT: br label [[WHILE_END]]
19 ; CHECK-NEXT: br label [[WHILE_COND]]
21 ; CHECK-NEXT: store i8 0, i8* [[FOO]], align 1
22 ; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[BLAH]], align 1
23 ; CHECK-NEXT: [[LOADED:%.*]] = icmp eq i8 [[TMP0]], 0
24 ; CHECK-NEXT: store i8 0, i8* [[BLAH]], align 1
25 ; CHECK-NEXT: ret i1 [[LOADED]]
31 %foo = phi i8* [ %blah, %entry ], [ null, %while.body ]
32 switch i32 %choice, label %while.body [
33 i32 -1, label %while.end
34 i32 40, label %land.end
44 %foo.lcssa = phi i8* [ %foo, %land.end ], [ %foo, %while.cond ]
45 ;; These two stores will initially be considered equivalent, but then proven not.
46 ;; the second store would previously end up deciding it's equivalent to a previous
47 ;; store, but it was really just finding an optimistic version of itself
48 ;; in the congruence class.
49 store i8 0, i8* %foo.lcssa, align 1
50 %0 = load i8, i8* %blah, align 1
51 %loaded = icmp eq i8 %0, 0
52 store i8 0, i8* %blah, align 1
57 ;; This is an example of a case where the memory states are equivalent solely due to unreachability,
58 ;; but the stores are not equal.
59 define void @foo(i8* %arg) {
62 ; CHECK-NEXT: br label [[BB1:%.*]]
64 ; CHECK-NEXT: [[TMP:%.*]] = phi i8* [ [[ARG:%.*]], [[BB:%.*]] ], [ null, [[BB2:%.*]] ]
65 ; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB2]]
67 ; CHECK-NEXT: br label [[BB1]]
69 ; CHECK-NEXT: store i8 0, i8* [[TMP]], align 1, !g !0
70 ; CHECK-NEXT: br label [[BB4:%.*]]
72 ; CHECK-NEXT: br label [[BB6:%.*]]
74 ; CHECK-NEXT: br i1 undef, label [[BB9:%.*]], label [[BB7:%.*]]
76 ; CHECK-NEXT: switch i8 0, label [[BB6]] [
77 ; CHECK-NEXT: i8 6, label [[BB8:%.*]]
80 ; CHECK-NEXT: store i8 undef, i8* null, align 1
81 ; CHECK-NEXT: br label [[BB4]]
83 ; CHECK-NEXT: store i8 0, i8* [[ARG]], align 1, !g !0
84 ; CHECK-NEXT: unreachable
89 bb1: ; preds = %bb2, %bb
90 %tmp = phi i8* [ %arg, %bb ], [ null, %bb2 ]
91 br i1 undef, label %bb3, label %bb2
97 store i8 0, i8* %tmp, !g !0
100 bb4: ; preds = %bb8, %bb3
101 %tmp5 = phi i8* [ null, %bb8 ], [ %arg, %bb3 ]
104 bb6: ; preds = %bb7, %bb4
105 br i1 undef, label %bb9, label %bb7
108 switch i8 0, label %bb6 [
113 store i8 undef, i8* %tmp5, !g !0
117 %tmp10 = phi i8* [ %tmp5, %bb6 ]
118 store i8 0, i8* %tmp10, !g !0