1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
2 ; RUN: opt -S -passes=indvars < %s | FileCheck %s
4 target datalayout = "n8:16:32:64"
6 ; The udiv should not get hoisted into the preheader (past a conditional).
7 define i32 @test(i1 %c, i32 %arg1, i32 %arg2) {
8 ; CHECK-LABEL: define i32 @test(
9 ; CHECK-SAME: i1 [[C:%.*]], i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) {
11 ; CHECK-NEXT: br label [[LOOP:%.*]]
13 ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[ADD9:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
14 ; CHECK-NEXT: br i1 [[C]], label [[IF:%.*]], label [[LOOP_LATCH]]
16 ; CHECK-NEXT: [[UDIV:%.*]] = udiv i32 [[ARG1]], [[ARG2]]
17 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[UDIV]], [[PHI]]
18 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[ADD]] to i64
19 ; CHECK-NEXT: br label [[LOOP2:%.*]]
21 ; CHECK-NEXT: [[PHI6:%.*]] = phi i64 [ [[ADD7:%.*]], [[LOOP2]] ], [ 0, [[IF]] ]
22 ; CHECK-NEXT: [[ADD7]] = add nuw nsw i64 [[PHI6]], 1
23 ; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[PHI6]], [[ZEXT]]
24 ; CHECK-NEXT: br i1 [[ICMP]], label [[LOOP2]], label [[LOOP_LATCH_LOOPEXIT:%.*]]
25 ; CHECK: loop.latch.loopexit:
26 ; CHECK-NEXT: br label [[LOOP_LATCH]]
28 ; CHECK-NEXT: [[ADD9]] = add i32 [[PHI]], 1
29 ; CHECK-NEXT: br label [[LOOP]]
35 %phi = phi i32 [ %add9, %loop.latch ], [ 0, %entry ]
36 br i1 %c, label %if, label %loop.latch
39 %udiv = udiv i32 %arg1, %arg2
40 %add = add i32 %udiv, %phi
41 %zext = zext i32 %add to i64
45 %phi6 = phi i64 [ %add7, %loop2 ], [ 0, %if ]
46 %add7 = add i64 %phi6, 1
47 %icmp = icmp slt i64 %phi6, %zext
48 br i1 %icmp, label %loop2, label %loop.latch
51 %add9 = add i32 %phi, 1