llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=arm -mcpu=cortex-m7 --timeline --iterations=1 < %s | FileCheck %s
   3
   4 add r1, r1, #1
   5 # ReadAdvance: 0
   6 add r1, r1, #2
   7 # ReadAdvance: -1
   8 vldr d0, [r1]
   9
  10 # CHECK:      Iterations:        1
  11 # CHECK-NEXT: Instructions:      3
  12 # CHECK-NEXT: Total Cycles:      6
  13 # CHECK-NEXT: Total uOps:        3
  14
  15 # CHECK:      Dispatch Width:    2
  16 # CHECK-NEXT: uOps Per Cycle:    0.50
  17 # CHECK-NEXT: IPC:               0.50
  18 # CHECK-NEXT: Block RThroughput: 1.5
  19
  20 # CHECK:      Instruction Info:
  21 # CHECK-NEXT: [1]: #uOps
  22 # CHECK-NEXT: [2]: Latency
  23 # CHECK-NEXT: [3]: RThroughput
  24 # CHECK-NEXT: [4]: MayLoad
  25 # CHECK-NEXT: [5]: MayStore
  26 # CHECK-NEXT: [6]: HasSideEffects (U)
  27
  28 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  29 # CHECK-NEXT:  1      1     0.50                        add.w   r1, r1, #1
  30 # CHECK-NEXT:  1      1     0.50                        add.w   r1, r1, #2
  31 # CHECK-NEXT:  1      3     1.00    *                   vldr    d0, [r1]
  32
  33 # CHECK:      Resources:
  34 # CHECK-NEXT: [0.0] - M7UnitALU
  35 # CHECK-NEXT: [0.1] - M7UnitALU
  36 # CHECK-NEXT: [1]   - M7UnitBranch
  37 # CHECK-NEXT: [2]   - M7UnitLoadH
  38 # CHECK-NEXT: [3]   - M7UnitLoadL
  39 # CHECK-NEXT: [4]   - M7UnitMAC
  40 # CHECK-NEXT: [5]   - M7UnitSIMD
  41 # CHECK-NEXT: [6]   - M7UnitShift1
  42 # CHECK-NEXT: [7]   - M7UnitShift2
  43 # CHECK-NEXT: [8]   - M7UnitStore
  44 # CHECK-NEXT: [9]   - M7UnitVFP
  45 # CHECK-NEXT: [10]  - M7UnitVPortH
  46 # CHECK-NEXT: [11]  - M7UnitVPortL
  47
  48 # CHECK:      Resource pressure per iteration:
  49 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]
  50 # CHECK-NEXT: 1.00   1.00    -     1.00   1.00    -      -      -      -      -      -     1.00   1.00
  51
  52 # CHECK:      Resource pressure by instruction:
  53 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   Instructions:
  54 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     add.w  r1, r1, #1
  55 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     add.w  r1, r1, #2
  56 # CHECK-NEXT:  -      -      -     1.00   1.00    -      -      -      -      -      -     1.00   1.00   vldr   d0, [r1]
  57
  58 # CHECK:      Timeline view:
  59 # CHECK-NEXT: Index     012345
  60
  61 # CHECK:      [0,0]     DE   .   add.w  r1, r1, #1
  62 # CHECK-NEXT: [0,1]     .DE  .   add.w  r1, r1, #2
  63 # CHECK-NEXT: [0,2]     .  DeE   vldr   d0, [r1]
  64
  65 # CHECK:      Average Wait times (based on the timeline view):
  66 # CHECK-NEXT: [0]: Executions
  67 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  68 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  69 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  70
  71 # CHECK:            [0]    [1]    [2]    [3]
  72 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       add.w        r1, r1, #1
  73 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       add.w        r1, r1, #2
  74 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       vldr d0, [r1]
  75 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>