1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s
4 vsetvli zero
, a0
, e8
, m2
, tu
, mu
5 # LLVM-MCA-RISCV-LMUL M2
7 vsetvli zero
, a0
, e8
, m1
, tu
, mu
8 # LLVM-MCA-RISCV-LMUL M1
10 vsetvli zero
, a0
, e8
, m8
, tu
, mu
11 # LLVM-MCA-RISCV-LMUL M8
14 # CHECK: Iterations: 1
15 # CHECK-NEXT: Instructions: 6
16 # CHECK-NEXT: Total Cycles: 42
17 # CHECK-NEXT: Total uOps: 6
19 # CHECK: Dispatch Width: 2
20 # CHECK-NEXT: uOps Per Cycle: 0.14
21 # CHECK-NEXT: IPC: 0.14
22 # CHECK-NEXT: Block RThroughput: 51.0
24 # CHECK: Instruction Info:
25 # CHECK-NEXT: [1]: #uOps
26 # CHECK-NEXT: [2]: Latency
27 # CHECK-NEXT: [3]: RThroughput
28 # CHECK-NEXT: [4]: MayLoad
29 # CHECK-NEXT: [5]: MayStore
30 # CHECK-NEXT: [6]: HasSideEffects (U)
32 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
33 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
34 # CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
35 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
36 # CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
37 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
38 # CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
41 # CHECK-NEXT: [0] - SiFive7FDiv
42 # CHECK-NEXT: [1] - SiFive7IDiv
43 # CHECK-NEXT: [2] - SiFive7PipeA
44 # CHECK-NEXT: [3] - SiFive7PipeB
45 # CHECK-NEXT: [4] - SiFive7VA
46 # CHECK-NEXT: [5] - SiFive7VCQ
47 # CHECK-NEXT: [6] - SiFive7VL
48 # CHECK-NEXT: [7] - SiFive7VS
50 # CHECK: Resource pressure per iteration:
51 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
52 # CHECK-NEXT: - - 3.00 - 51.00 3.00 - -
54 # CHECK: Resource pressure by instruction:
55 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
56 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
57 # CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
58 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
59 # CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
60 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
61 # CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
63 # CHECK: Timeline view:
64 # CHECK-NEXT: 0123456789 0123456789
65 # CHECK-NEXT: Index 0123456789 0123456789 01
67 # CHECK: [0,0] DeeE . . . . . . . .. vsetvli zero, a0, e8, m2, tu, mu
68 # CHECK-NEXT: [0,1] . DeeeE . . . . . . .. vadd.vv v12, v12, v12
69 # CHECK-NEXT: [0,2] . DeeE . . . . . . .. vsetvli zero, a0, e8, m1, tu, mu
70 # CHECK-NEXT: [0,3] . . . . DeeeE. . . .. vadd.vv v12, v12, v12
71 # CHECK-NEXT: [0,4] . . . . .DeeE. . . .. vsetvli zero, a0, e8, m8, tu, mu
72 # CHECK-NEXT: [0,5] . . . . . . . . DeeeE vadd.vv v12, v12, v12
74 # CHECK: Average Wait times (based on the timeline view):
75 # CHECK-NEXT: [0]: Executions
76 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
77 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
78 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
80 # CHECK: [0] [1] [2] [3]
81 # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m2, tu, mu
82 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
83 # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
84 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
85 # CHECK-NEXT: 4. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
86 # CHECK-NEXT: 5. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
87 # CHECK-NEXT: 1 0.0 0.0 0.0 <total>