llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
   3
   4 # TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)
   5 # pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV
   6 # SPEC.
   7 vsetvli zero, zero, e32, mf2, tu, mu
   8 vdiv.vv v12, v12, v12
   9 vsetvli zero, zero, e8, mf8, tu, mu
  10 vdiv.vv v12, v12, v12
  11
  12 # CHECK:      Iterations:        1
  13 # CHECK-NEXT: Instructions:      4
  14 # CHECK-NEXT: Total Cycles:      91
  15 # CHECK-NEXT: Total uOps:        4
  16
  17 # CHECK:      Dispatch Width:    2
  18 # CHECK-NEXT: uOps Per Cycle:    0.04
  19 # CHECK-NEXT: IPC:               0.04
  20 # CHECK-NEXT: Block RThroughput: 88.0
  21
  22 # CHECK:      Instruction Info:
  23 # CHECK-NEXT: [1]: #uOps
  24 # CHECK-NEXT: [2]: Latency
  25 # CHECK-NEXT: [3]: RThroughput
  26 # CHECK-NEXT: [4]: MayLoad
  27 # CHECK-NEXT: [5]: MayStore
  28 # CHECK-NEXT: [6]: HasSideEffects (U)
  29
  30 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  31 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, zero, e32, mf2, tu, mu
  32 # CHECK-NEXT:  1      56    57.00                       vdiv.vv v12, v12, v12
  33 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, zero, e8, mf8, tu, mu
  34 # CHECK-NEXT:  1      30    31.00                       vdiv.vv v12, v12, v12
  35
  36 # CHECK:      Resources:
  37 # CHECK-NEXT: [0]   - SiFive7FDiv
  38 # CHECK-NEXT: [1]   - SiFive7IDiv
  39 # CHECK-NEXT: [2]   - SiFive7PipeA
  40 # CHECK-NEXT: [3]   - SiFive7PipeB
  41 # CHECK-NEXT: [4]   - SiFive7VA
  42 # CHECK-NEXT: [5]   - SiFive7VCQ
  43 # CHECK-NEXT: [6]   - SiFive7VL
  44 # CHECK-NEXT: [7]   - SiFive7VS
  45
  46 # CHECK:      Resource pressure per iteration:
  47 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
  48 # CHECK-NEXT:  -      -     2.00    -     88.00  2.00    -      -
  49
  50 # CHECK:      Resource pressure by instruction:
  51 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
  52 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, zero, e32, mf2, tu, mu
  53 # CHECK-NEXT:  -      -      -      -     57.00  1.00    -      -     vdiv.vv   v12, v12, v12
  54 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, zero, e8, mf8, tu, mu
  55 # CHECK-NEXT:  -      -      -      -     31.00  1.00    -      -     vdiv.vv   v12, v12, v12