1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
5 vsetvli zero
, a0
, e8
, m1
, tu
, mu
6 # LLVM-MCA-RISCV-LMUL M1
10 # CHECK: [0] Code Region - foo
12 # CHECK: Iterations: 1
13 # CHECK-NEXT: Instructions: 2
14 # CHECK-NEXT: Total Cycles: 8
15 # CHECK-NEXT: Total uOps: 2
17 # CHECK: Dispatch Width: 2
18 # CHECK-NEXT: uOps Per Cycle: 0.25
19 # CHECK-NEXT: IPC: 0.25
20 # CHECK-NEXT: Block RThroughput: 3.0
22 # CHECK: Instruction Info:
23 # CHECK-NEXT: [1]: #uOps
24 # CHECK-NEXT: [2]: Latency
25 # CHECK-NEXT: [3]: RThroughput
26 # CHECK-NEXT: [4]: MayLoad
27 # CHECK-NEXT: [5]: MayStore
28 # CHECK-NEXT: [6]: HasSideEffects (U)
30 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
31 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
32 # CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
35 # CHECK-NEXT: [0] - SiFive7FDiv
36 # CHECK-NEXT: [1] - SiFive7IDiv
37 # CHECK-NEXT: [2] - SiFive7PipeA
38 # CHECK-NEXT: [3] - SiFive7PipeB
39 # CHECK-NEXT: [4] - SiFive7VA
40 # CHECK-NEXT: [5] - SiFive7VCQ
41 # CHECK-NEXT: [6] - SiFive7VL
42 # CHECK-NEXT: [7] - SiFive7VS
44 # CHECK: Resource pressure per iteration:
45 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
46 # CHECK-NEXT: - - 1.00 - 3.00 1.00 - -
48 # CHECK: Resource pressure by instruction:
49 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
50 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
51 # CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
53 # CHECK: Timeline view:
54 # CHECK-NEXT: Index 01234567
56 # CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
57 # CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
59 # CHECK: Average Wait times (based on the timeline view):
60 # CHECK-NEXT: [0]: Executions
61 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
62 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
63 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
65 # CHECK: [0] [1] [2] [3]
66 # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
67 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
68 # CHECK-NEXT: 1 0.0 0.0 0.0 <total>