llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
   3
   4 vsetvli zero, a0, e64, m1, tu, mu
   5 # LLVM-MCA-RISCV-LMUL M1
   6 # LLVM-MCA-RISCV-SEW E64
   7 vdiv.vv v8, v8, v12
   8 vsetvli zero, a0, e64, m1, tu, mu
   9 # LLVM-MCA-RISCV-SEW E64
  10 vdiv.vv v8, v8, v12
  11 vdivu.vv v8, v8, v12
  12 vsetvli zero, a0, e32, m1, tu, mu
  13 # LLVM-MCA-RISCV-SEW E32
  14 vdiv.vv v8, v8, v12
  15 vdivu.vv v8, v8, v12
  16
  17 # CHECK:      Iterations:        1
  18 # CHECK-NEXT: Instructions:      8
  19 # CHECK-NEXT: Total Cycles:      574
  20 # CHECK-NEXT: Total uOps:        8
  21
  22 # CHECK:      Dispatch Width:    2
  23 # CHECK-NEXT: uOps Per Cycle:    0.01
  24 # CHECK-NEXT: IPC:               0.01
  25 # CHECK-NEXT: Block RThroughput: 571.0
  26
  27 # CHECK:      Instruction Info:
  28 # CHECK-NEXT: [1]: #uOps
  29 # CHECK-NEXT: [2]: Latency
  30 # CHECK-NEXT: [3]: RThroughput
  31 # CHECK-NEXT: [4]: MayLoad
  32 # CHECK-NEXT: [5]: MayStore
  33 # CHECK-NEXT: [6]: HasSideEffects (U)
  34
  35 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  36 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
  37 # CHECK-NEXT:  1      114   115.00                      vdiv.vv v8, v8, v12
  38 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
  39 # CHECK-NEXT:  1      114   115.00                      vdiv.vv v8, v8, v12
  40 # CHECK-NEXT:  1      114   115.00                      vdivu.vv        v8, v8, v12
  41 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e32, m1, tu, mu
  42 # CHECK-NEXT:  1      112   113.00                      vdiv.vv v8, v8, v12
  43 # CHECK-NEXT:  1      112   113.00                      vdivu.vv        v8, v8, v12
  44
  45 # CHECK:      Resources:
  46 # CHECK-NEXT: [0]   - SiFive7FDiv
  47 # CHECK-NEXT: [1]   - SiFive7IDiv
  48 # CHECK-NEXT: [2]   - SiFive7PipeA
  49 # CHECK-NEXT: [3]   - SiFive7PipeB
  50 # CHECK-NEXT: [4]   - SiFive7VA
  51 # CHECK-NEXT: [5]   - SiFive7VCQ
  52 # CHECK-NEXT: [6]   - SiFive7VL
  53 # CHECK-NEXT: [7]   - SiFive7VS
  54
  55 # CHECK:      Resource pressure per iteration:
  56 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
  57 # CHECK-NEXT:  -      -     3.00    -     571.00 5.00    -      -
  58
  59 # CHECK:      Resource pressure by instruction:
  60 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
  61 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, a0, e64, m1, tu, mu
  62 # CHECK-NEXT:  -      -      -      -     115.00 1.00    -      -     vdiv.vv   v8, v8, v12
  63 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, a0, e64, m1, tu, mu
  64 # CHECK-NEXT:  -      -      -      -     115.00 1.00    -      -     vdiv.vv   v8, v8, v12
  65 # CHECK-NEXT:  -      -      -      -     115.00 1.00    -      -     vdivu.vv  v8, v8, v12
  66 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, a0, e32, m1, tu, mu
  67 # CHECK-NEXT:  -      -      -      -     113.00 1.00    -      -     vdiv.vv   v8, v8, v12
  68 # CHECK-NEXT:  -      -      -      -     113.00 1.00    -      -     vdivu.vv  v8, v8, v12
  69
  70 # CHECK:      Timeline view:
  71 # CHECK-NEXT: Index     0123
  72
  73 # CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e64, m1, tu, mu
  74 # CHECK-NEXT: Truncated display due to cycle limit
  75
  76 # CHECK:      Average Wait times (based on the timeline view):
  77 # CHECK-NEXT: [0]: Executions
  78 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  79 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  80 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  81
  82 # CHECK:            [0]    [1]    [2]    [3]
  83 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli      zero, a0, e64, m1, tu, mu
  84 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  85 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli      zero, a0, e64, m1, tu, mu
  86 # CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  87 # CHECK-NEXT: 4.     1     0.0    0.0    0.0       vdivu.vv     v8, v8, v12
  88 # CHECK-NEXT: 5.     1     0.0    0.0    0.0       vsetvli      zero, a0, e32, m1, tu, mu
  89 # CHECK-NEXT: 6.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  90 # CHECK-NEXT: 7.     1     0.0    0.0    0.0       vdivu.vv     v8, v8, v12
  91 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>