llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
   3
   4 # Test LMUL but no SEW falls back to worst case.
   5 vsetvli zero, a0, e8, m1, tu, mu
   6 # LLVM-MCA-RISCV-LMUL M1
   7 vdiv.vv v8, v8, v12
   8 # LLVM-MCA-RISCV-SEW E8
   9 vdiv.vv v8, v8, v12
  10
  11 # CHECK:      Iterations:        1
  12 # CHECK-NEXT: Instructions:      3
  13 # CHECK-NEXT: Total Cycles:      485
  14 # CHECK-NEXT: Total uOps:        3
  15
  16 # CHECK:      Dispatch Width:    2
  17 # CHECK-NEXT: uOps Per Cycle:    0.01
  18 # CHECK-NEXT: IPC:               0.01
  19 # CHECK-NEXT: Block RThroughput: 482.0
  20
  21 # CHECK:      Instruction Info:
  22 # CHECK-NEXT: [1]: #uOps
  23 # CHECK-NEXT: [2]: Latency
  24 # CHECK-NEXT: [3]: RThroughput
  25 # CHECK-NEXT: [4]: MayLoad
  26 # CHECK-NEXT: [5]: MayStore
  27 # CHECK-NEXT: [6]: HasSideEffects (U)
  28
  29 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  30 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
  31 # CHECK-NEXT:  1      240   241.00                      vdiv.vv v8, v8, v12
  32 # CHECK-NEXT:  1      240   241.00                      vdiv.vv v8, v8, v12
  33
  34 # CHECK:      Resources:
  35 # CHECK-NEXT: [0]   - SiFive7FDiv
  36 # CHECK-NEXT: [1]   - SiFive7IDiv
  37 # CHECK-NEXT: [2]   - SiFive7PipeA
  38 # CHECK-NEXT: [3]   - SiFive7PipeB
  39 # CHECK-NEXT: [4]   - SiFive7VA
  40 # CHECK-NEXT: [5]   - SiFive7VCQ
  41 # CHECK-NEXT: [6]   - SiFive7VL
  42 # CHECK-NEXT: [7]   - SiFive7VS
  43
  44 # CHECK:      Resource pressure per iteration:
  45 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
  46 # CHECK-NEXT:  -      -     1.00    -     482.00 2.00    -      -
  47
  48 # CHECK:      Resource pressure by instruction:
  49 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
  50 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli   zero, a0, e8, m1, tu, mu
  51 # CHECK-NEXT:  -      -      -      -     241.00 1.00    -      -     vdiv.vv   v8, v8, v12
  52 # CHECK-NEXT:  -      -      -      -     241.00 1.00    -      -     vdiv.vv   v8, v8, v12
  53
  54 # CHECK:      Timeline view:
  55 # CHECK-NEXT: Index     0123
  56
  57 # CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e8, m1, tu, mu
  58 # CHECK-NEXT: Truncated display due to cycle limit
  59
  60 # CHECK:      Average Wait times (based on the timeline view):
  61 # CHECK-NEXT: [0]: Executions
  62 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  63 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  64 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  65
  66 # CHECK:            [0]    [1]    [2]    [3]
  67 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli      zero, a0, e8, m1, tu, mu
  68 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  69 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  70 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>