llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
   3
   4 vsetivli zero, 8, e8, m1, tu, mu
   5 vdiv.vv v8, v8, v12
   6 vsetivli zero, 8, e32, m8, tu, mu
   7 vdiv.vv v8, v8, v12
   8
   9 # CHECK:      Iterations:        1
  10 # CHECK-NEXT: Instructions:      4
  11 # CHECK-NEXT: Total Cycles:      1141
  12 # CHECK-NEXT: Total uOps:        4
  13
  14 # CHECK:      Dispatch Width:    2
  15 # CHECK-NEXT: uOps Per Cycle:    0.00
  16 # CHECK-NEXT: IPC:               0.00
  17 # CHECK-NEXT: Block RThroughput: 1138.0
  18
  19 # CHECK:      Instruction Info:
  20 # CHECK-NEXT: [1]: #uOps
  21 # CHECK-NEXT: [2]: Latency
  22 # CHECK-NEXT: [3]: RThroughput
  23 # CHECK-NEXT: [4]: MayLoad
  24 # CHECK-NEXT: [5]: MayStore
  25 # CHECK-NEXT: [6]: HasSideEffects (U)
  26
  27 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  28 # CHECK-NEXT:  1      3     1.00                  U     vsetivli        zero, 8, e8, m1, tu, mu
  29 # CHECK-NEXT:  1      240   241.00                      vdiv.vv v8, v8, v12
  30 # CHECK-NEXT:  1      3     1.00                  U     vsetivli        zero, 8, e32, m8, tu, mu
  31 # CHECK-NEXT:  1      896   897.00                      vdiv.vv v8, v8, v12
  32
  33 # CHECK:      Resources:
  34 # CHECK-NEXT: [0]   - SiFive7FDiv
  35 # CHECK-NEXT: [1]   - SiFive7IDiv
  36 # CHECK-NEXT: [2]   - SiFive7PipeA
  37 # CHECK-NEXT: [3]   - SiFive7PipeB
  38 # CHECK-NEXT: [4]   - SiFive7VA
  39 # CHECK-NEXT: [5]   - SiFive7VCQ
  40 # CHECK-NEXT: [6]   - SiFive7VL
  41 # CHECK-NEXT: [7]   - SiFive7VS
  42
  43 # CHECK:      Resource pressure per iteration:
  44 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
  45 # CHECK-NEXT:  -      -     2.00    -     1138.00 2.00   -      -
  46
  47 # CHECK:      Resource pressure by instruction:
  48 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
  49 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetivli  zero, 8, e8, m1, tu, mu
  50 # CHECK-NEXT:  -      -      -      -     241.00 1.00    -      -     vdiv.vv   v8, v8, v12
  51 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetivli  zero, 8, e32, m8, tu, mu
  52 # CHECK-NEXT:  -      -      -      -     897.00 1.00    -      -     vdiv.vv   v8, v8, v12
  53
  54 # CHECK:      Timeline view:
  55 # CHECK-NEXT: Index     0123
  56
  57 # CHECK:      [0,0]     DeeE   vsetivli zero, 8, e8, m1, tu, mu
  58 # CHECK-NEXT: Truncated display due to cycle limit
  59
  60 # CHECK:      Average Wait times (based on the timeline view):
  61 # CHECK-NEXT: [0]: Executions
  62 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  63 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  64 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  65
  66 # CHECK:            [0]    [1]    [2]    [3]
  67 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetivli     zero, 8, e8, m1, tu, mu
  68 # CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  69 # CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetivli     zero, 8, e32, m8, tu, mu
  70 # CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv      v8, v8, v12
  71 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>