[llvm-project.git] / llvm / test / CodeGen / AMDGPU / GlobalISel / divergence-divergent-i1-used-outside-loop.mir
| blob | 5bbe3e488689983f28781dfd4767ce959283223a |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2 # RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
4 ---
5 name: divergent_i1_phi_used_outside_loop
6 legalized: true
7 tracksRegLiveness: true
8 body: |
9 ; GFX10-LABEL: name: divergent_i1_phi_used_outside_loop
10 ; GFX10: bb.0:
11 ; GFX10-NEXT: successors: %bb.1(0x80000000)
12 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
13 ; GFX10-NEXT: {{ $}}
14 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
16 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
17 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
18 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
19 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
20 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
21 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]]
22 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)
23 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
24 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[DEF]](s1)
25 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
26 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc
27 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
28 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
29 ; GFX10-NEXT: {{ $}}
30 ; GFX10-NEXT: bb.1:
31 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
32 ; GFX10-NEXT: {{ $}}
33 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %36(s1), %bb.1
34 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.0, %24(s1), %bb.1
35 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.1, [[C]](s32), %bb.0
36 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.1
37 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
38 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
39 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)
40 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
41 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
42 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY7]], [[C2]]
43 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
44 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)
45 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
46 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
47 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C3]]
48 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)
49 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc
50 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc
51 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
52 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
53 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY8]](s1), implicit-def $scc
54 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
55 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
56 ; GFX10-NEXT: G_BR %bb.2
57 ; GFX10-NEXT: {{ $}}
58 ; GFX10-NEXT: bb.2:
59 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.1
60 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_2]](s1)
61 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
62 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
63 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
64 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY11]](s1), [[C5]], [[C4]]
65 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))
66 ; GFX10-NEXT: SI_RETURN
67 bb.0:
68 successors: %bb.1(0x80000000)
69 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
71 %0:_(s32) = COPY $vgpr0
72 %1:_(s32) = COPY $vgpr1
73 %2:_(s32) = COPY $vgpr2
74 %3:_(s32) = COPY $vgpr3
75 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)
76 %5:_(s32) = G_CONSTANT i32 0
77 %6:_(s32) = G_FCONSTANT float 1.000000e+00
78 %7:_(s1) = G_FCMP floatpred(ogt), %1(s32), %6
80 bb.1:
81 successors: %bb.2(0x04000000), %bb.1(0x7c000000)
83 %8:_(s32) = G_PHI %9(s32), %bb.1, %5(s32), %bb.0
84 %10:_(s32) = G_PHI %5(s32), %bb.0, %11(s32), %bb.1
85 %12:_(s1) = G_PHI %7(s1), %bb.0, %13(s1), %bb.1
86 %14:_(s1) = G_CONSTANT i1 true
87 %13:_(s1) = G_XOR %12, %14
88 %15:_(s32) = G_UITOFP %10(s32)
89 %16:_(s1) = G_FCMP floatpred(ogt), %15(s32), %0
90 %17:_(s32) = G_CONSTANT i32 1
91 %11:_(s32) = G_ADD %10, %17
92 %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %16(s1), %8(s32)
93 SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
94 G_BR %bb.2
96 bb.2:
97 %18:_(s1) = G_PHI %12(s1), %bb.1
98 %19:_(s32) = G_PHI %9(s32), %bb.1
99 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %19(s32)
100 %20:_(s32) = G_FCONSTANT float 0.000000e+00
101 %21:_(s32) = G_FCONSTANT float 1.000000e+00
102 %22:_(s32) = G_SELECT %18(s1), %21, %20
103 G_STORE %22(s32), %4(p0) :: (store (s32))
104 SI_RETURN
105 ...
107 ---
108 name: divergent_i1_phi_used_outside_loop_larger_loop_body
109 legalized: true
110 tracksRegLiveness: true
111 body: |
112 ; GFX10-LABEL: name: divergent_i1_phi_used_outside_loop_larger_loop_body
113 ; GFX10: bb.0:
114 ; GFX10-NEXT: successors: %bb.1(0x80000000)
115 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
116 ; GFX10-NEXT: {{ $}}
117 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1
118 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
119 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
120 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr3
121 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr4
122 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
123 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
124 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
125 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[C1]](s1)
126 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
127 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[DEF]](s1)
128 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
129 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc
130 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
131 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
132 ; GFX10-NEXT: {{ $}}
133 ; GFX10-NEXT: bb.1:
134 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
135 ; GFX10-NEXT: {{ $}}
136 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %41(s1), %bb.3
137 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[S_OR_B32_]](s1), %bb.0, %27(s1), %bb.3
138 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.3
139 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(p1) = G_PHI [[MV]](p1), %bb.0, %11(p1), %bb.3
140 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
141 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)
142 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)
143 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI1]](s1)
144 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
145 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY8]](s1), implicit-def $scc
146 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
147 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)
148 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY7]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
149 ; GFX10-NEXT: G_BR %bb.2
150 ; GFX10-NEXT: {{ $}}
151 ; GFX10-NEXT: bb.2:
152 ; GFX10-NEXT: successors: %bb.3(0x80000000)
153 ; GFX10-NEXT: {{ $}}
154 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PHI3]](p1) :: (load (s32), addrspace 1)
155 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
156 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C2]]
157 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
158 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
159 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
160 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
161 ; GFX10-NEXT: {{ $}}
162 ; GFX10-NEXT: bb.3:
163 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)
164 ; GFX10-NEXT: {{ $}}
165 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.1, [[S_OR_B32_2]](s1), %bb.2
166 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[PHI4]](s1)
167 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY12]](s1)
168 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
169 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
170 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[PHI3]], [[C3]](s64)
171 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
172 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[PHI2]], [[C4]]
173 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
174 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[ADD]](s32), [[C5]]
175 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc
176 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc
177 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
178 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[COPY7]](s1)
179 ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.1
180 ; GFX10-NEXT: G_BR %bb.4
181 ; GFX10-NEXT: {{ $}}
182 ; GFX10-NEXT: bb.4:
183 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[COPY14]](s1)
184 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
185 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
186 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY15]](s1), [[C7]], [[C6]]
187 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV1]](p0) :: (store (s32))
188 ; GFX10-NEXT: SI_RETURN
189 bb.0:
190 successors: %bb.1(0x80000000)
191 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
193 %0:_(s32) = COPY $vgpr1
194 %1:_(s32) = COPY $vgpr2
195 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
196 %3:_(s32) = COPY $vgpr3
197 %4:_(s32) = COPY $vgpr4
198 %5:_(p0) = G_MERGE_VALUES %3(s32), %4(s32)
199 %6:_(s32) = G_CONSTANT i32 -1
200 %7:_(s1) = G_CONSTANT i1 true
202 bb.1:
203 successors: %bb.2(0x40000000), %bb.3(0x40000000)
205 %8:_(s32) = G_PHI %6(s32), %bb.0, %9(s32), %bb.3
206 %10:_(p1) = G_PHI %2(p1), %bb.0, %11(p1), %bb.3
207 %12:sreg_32_xm0_xexec(s1) = G_PHI %7(s1), %bb.0, %13(s1), %bb.3
208 %14:sreg_32_xm0_xexec(s32) = SI_IF %12(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
209 G_BR %bb.2
211 bb.2:
212 successors: %bb.3(0x80000000)
214 %15:_(s32) = G_LOAD %10(p1) :: (load (s32), addrspace 1)
215 %16:_(s32) = G_CONSTANT i32 0
216 %17:_(s1) = G_ICMP intpred(eq), %15(s32), %16
218 bb.3:
219 successors: %bb.4(0x04000000), %bb.1(0x7c000000)
221 %13:_(s1) = G_PHI %17(s1), %bb.2, %12(s1), %bb.1
222 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s32)
223 %18:_(s64) = G_CONSTANT i64 4
224 %11:_(p1) = G_PTR_ADD %10, %18(s64)
225 %19:_(s32) = G_CONSTANT i32 1
226 %9:_(s32) = nsw G_ADD %8, %19
227 %20:_(s32) = G_CONSTANT i32 10
228 %21:_(s1) = G_ICMP intpred(sge), %9(s32), %20
229 G_BRCOND %21(s1), %bb.1
230 G_BR %bb.4
232 bb.4:
233 %22:_(s1) = G_PHI %12(s1), %bb.3
234 %23:_(s32) = G_FCONSTANT float 0.000000e+00
235 %24:_(s32) = G_FCONSTANT float 1.000000e+00
236 %25:_(s32) = G_SELECT %22(s1), %24, %23
237 G_STORE %25(s32), %5(p0) :: (store (s32))
238 SI_RETURN
239 ...
241 ---
242 name: divergent_i1_xor_used_outside_loop
243 legalized: true
244 tracksRegLiveness: true
245 body: |
246 ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop
247 ; GFX10: bb.0:
248 ; GFX10-NEXT: successors: %bb.1(0x80000000)
249 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
250 ; GFX10-NEXT: {{ $}}
251 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
252 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
253 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
254 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
255 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
256 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
257 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
258 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]]
259 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)
260 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
261 ; GFX10-NEXT: {{ $}}
262 ; GFX10-NEXT: bb.1:
263 ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
264 ; GFX10-NEXT: {{ $}}
265 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %27(s1), %bb.1
266 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, %24(s1), %bb.1
267 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.1, [[C]](s32), %bb.0
268 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.1
269 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
270 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
271 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
272 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY6]], [[C2]]
273 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
274 ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)
275 ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
276 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
277 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C3]]
278 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)
279 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
280 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
281 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc
282 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
283 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
284 ; GFX10-NEXT: G_BR %bb.2
285 ; GFX10-NEXT: {{ $}}
286 ; GFX10-NEXT: bb.2:
287 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.1
288 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
289 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
290 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
291 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
292 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY9]](s1), [[C5]], [[C4]]
293 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))
294 ; GFX10-NEXT: SI_RETURN
295 bb.0:
296 successors: %bb.1(0x80000000)
297 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
299 %0:_(s32) = COPY $vgpr0
300 %1:_(s32) = COPY $vgpr1
301 %2:_(s32) = COPY $vgpr2
302 %3:_(s32) = COPY $vgpr3
303 %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)
304 %5:_(s32) = G_CONSTANT i32 0
305 %6:_(s32) = G_FCONSTANT float 1.000000e+00
306 %7:_(s1) = G_FCMP floatpred(ogt), %1(s32), %6
308 bb.1:
309 successors: %bb.2(0x04000000), %bb.1(0x7c000000)
311 %8:_(s32) = G_PHI %9(s32), %bb.1, %5(s32), %bb.0
312 %10:_(s32) = G_PHI %5(s32), %bb.0, %11(s32), %bb.1
313 %12:_(s1) = G_PHI %7(s1), %bb.0, %13(s1), %bb.1
314 %14:_(s1) = G_CONSTANT i1 true
315 %13:_(s1) = G_XOR %12, %14
316 %15:_(s32) = G_UITOFP %10(s32)
317 %16:_(s1) = G_FCMP floatpred(ogt), %15(s32), %0
318 %17:_(s32) = G_CONSTANT i32 1
319 %11:_(s32) = G_ADD %10, %17
320 %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %16(s1), %8(s32)
321 SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
322 G_BR %bb.2
324 bb.2:
325 %18:_(s1) = G_PHI %13(s1), %bb.1
326 %19:_(s32) = G_PHI %9(s32), %bb.1
327 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %19(s32)
328 %20:_(s32) = G_FCONSTANT float 0.000000e+00
329 %21:_(s32) = G_FCONSTANT float 1.000000e+00
330 %22:_(s32) = G_SELECT %18(s1), %21, %20
331 G_STORE %22(s32), %4(p0) :: (store (s32))
332 SI_RETURN
333 ...
335 ---
336 name: divergent_i1_xor_used_outside_loop_larger_loop_body
337 legalized: true
338 tracksRegLiveness: true
339 body: |
340 ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop_larger_loop_body
341 ; GFX10: bb.0:
342 ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
343 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
344 ; GFX10-NEXT: {{ $}}
345 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
346 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
347 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
348 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
349 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
350 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
351 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
352 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
353 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
354 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
355 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
356 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
357 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY5]](s1)
358 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
359 ; GFX10-NEXT: G_BR %bb.1
360 ; GFX10-NEXT: {{ $}}
361 ; GFX10-NEXT: bb.1:
362 ; GFX10-NEXT: successors: %bb.3(0x80000000)
363 ; GFX10-NEXT: {{ $}}
364 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
365 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
366 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
367 ; GFX10-NEXT: [[DEF3:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
368 ; GFX10-NEXT: G_BR %bb.3
369 ; GFX10-NEXT: {{ $}}
370 ; GFX10-NEXT: bb.2:
371 ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
372 ; GFX10-NEXT: {{ $}}
373 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY5]](s1), %bb.0, %40(s1), %bb.8
374 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)
375 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
376 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY7]](s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec
377 ; GFX10-NEXT: G_BR %bb.5
378 ; GFX10-NEXT: {{ $}}
379 ; GFX10-NEXT: bb.3:
380 ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000)
381 ; GFX10-NEXT: {{ $}}
382 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF3]](s1), %bb.1, %73(s1), %bb.7
383 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.1, %62(s1), %bb.7
384 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.1, %49(s1), %bb.7
385 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C2]](s32), %bb.1, %17(s32), %bb.7
386 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI %19(s32), %bb.7, [[C2]](s32), %bb.1
387 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
388 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)
389 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
390 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
391 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)
392 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)
393 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI5]](s32)
394 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
395 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32)
396 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64)
397 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
398 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
399 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C5]]
400 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
401 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc
402 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
403 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
404 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc
405 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
406 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
407 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)
408 ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
409 ; GFX10-NEXT: G_BR %bb.4
410 ; GFX10-NEXT: {{ $}}
411 ; GFX10-NEXT: bb.4:
412 ; GFX10-NEXT: successors: %bb.7(0x80000000)
413 ; GFX10-NEXT: {{ $}}
414 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
415 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[C6]](s1)
416 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
417 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI5]], [[C7]]
418 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[PHI5]](s32), [[COPY]]
419 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
420 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY13]](s1), $exec_lo, implicit-def $scc
421 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY15]](s1), implicit-def $scc
422 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
423 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY14]](s1), $exec_lo, implicit-def $scc
424 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY16]](s1), implicit-def $scc
425 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
426 ; GFX10-NEXT: G_BR %bb.7
427 ; GFX10-NEXT: {{ $}}
428 ; GFX10-NEXT: bb.5:
429 ; GFX10-NEXT: successors: %bb.6(0x80000000)
430 ; GFX10-NEXT: {{ $}}
431 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
432 ; GFX10-NEXT: G_STORE [[C8]](s32), [[MV1]](p0) :: (store (s32))
433 ; GFX10-NEXT: {{ $}}
434 ; GFX10-NEXT: bb.6:
435 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)
436 ; GFX10-NEXT: SI_RETURN
437 ; GFX10-NEXT: {{ $}}
438 ; GFX10-NEXT: bb.7:
439 ; GFX10-NEXT: successors: %bb.8(0x04000000), %bb.3(0x7c000000)
440 ; GFX10-NEXT: {{ $}}
441 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.3, [[S_OR_B32_3]](s1), %bb.4
442 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.3, [[S_OR_B32_2]](s1), %bb.4
443 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.4, [[DEF]](s32), %bb.3
444 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)
445 ; GFX10-NEXT: [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[PHI7]](s1)
446 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)
447 ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
448 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[COPY18]], [[C9]]
449 ; GFX10-NEXT: [[COPY19:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
450 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY17]](s1), [[PHI4]](s32)
451 ; GFX10-NEXT: [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
452 ; GFX10-NEXT: [[S_AND_B32_4:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY19]](s1), implicit-def $scc
453 ; GFX10-NEXT: [[S_OR_B32_4:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc
454 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
455 ; GFX10-NEXT: G_BR %bb.8
456 ; GFX10-NEXT: {{ $}}
457 ; GFX10-NEXT: bb.8:
458 ; GFX10-NEXT: successors: %bb.2(0x80000000)
459 ; GFX10-NEXT: {{ $}}
460 ; GFX10-NEXT: [[PHI9:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.7
461 ; GFX10-NEXT: [[COPY20:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_4]](s1)
462 ; GFX10-NEXT: [[COPY21:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY20]](s1)
463 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI9]](s32)
464 ; GFX10-NEXT: [[S_ANDN2_B32_5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
465 ; GFX10-NEXT: [[S_AND_B32_5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY21]](s1), implicit-def $scc
466 ; GFX10-NEXT: [[S_OR_B32_5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_5]](s1), [[S_AND_B32_5]](s1), implicit-def $scc
467 ; GFX10-NEXT: G_BR %bb.2
468 bb.0:
469 successors: %bb.1(0x40000000), %bb.2(0x40000000)
470 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
472 %0:_(s32) = COPY $vgpr0
473 %1:_(s32) = COPY $vgpr1
474 %2:_(s32) = COPY $vgpr2
475 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)
476 %4:_(s32) = COPY $vgpr3
477 %5:_(s32) = COPY $vgpr4
478 %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32)
479 %7:_(s32) = G_IMPLICIT_DEF
480 %8:_(s32) = G_CONSTANT i32 0
481 %9:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %8
482 %10:_(s1) = G_CONSTANT i1 true
483 %11:sreg_32_xm0_xexec(s32) = SI_IF %9(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
484 G_BR %bb.1
486 bb.1:
487 successors: %bb.3(0x80000000)
489 %12:_(s32) = G_CONSTANT i32 0
490 G_BR %bb.3
492 bb.2:
493 successors: %bb.5(0x40000000), %bb.6(0x40000000)
495 %13:sreg_32_xm0_xexec(s1) = G_PHI %14(s1), %bb.8, %10(s1), %bb.0
496 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32)
497 %15:sreg_32_xm0_xexec(s32) = SI_IF %13(s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec
498 G_BR %bb.5
500 bb.3:
501 successors: %bb.4(0x40000000), %bb.7(0x40000000)
503 %16:_(s32) = G_PHI %12(s32), %bb.1, %17(s32), %bb.7
504 %18:_(s32) = G_PHI %19(s32), %bb.7, %12(s32), %bb.1
505 %20:_(s1) = G_CONSTANT i1 true
506 %21:_(s64) = G_SEXT %18(s32)
507 %22:_(s32) = G_CONSTANT i32 2
508 %23:_(s64) = G_SHL %21, %22(s32)
509 %24:_(p1) = G_PTR_ADD %3, %23(s64)
510 %25:_(s32) = G_LOAD %24(p1) :: (load (s32), addrspace 1)
511 %26:_(s32) = G_CONSTANT i32 0
512 %27:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %25(s32), %26
513 %28:sreg_32_xm0_xexec(s32) = SI_IF %27(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec
514 G_BR %bb.4
516 bb.4:
517 successors: %bb.7(0x80000000)
519 %29:_(s1) = G_CONSTANT i1 false
520 %30:_(s32) = G_CONSTANT i32 1
521 %31:_(s32) = G_ADD %18, %30
522 %32:_(s1) = G_ICMP intpred(slt), %18(s32), %0
523 G_BR %bb.7
525 bb.5:
526 successors: %bb.6(0x80000000)
528 %33:_(s32) = G_CONSTANT i32 5
529 G_STORE %33(s32), %6(p0) :: (store (s32))
531 bb.6:
532 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
533 SI_RETURN
535 bb.7:
536 successors: %bb.8(0x04000000), %bb.3(0x7c000000)
538 %19:_(s32) = G_PHI %31(s32), %bb.4, %7(s32), %bb.3
539 %34:_(s1) = G_PHI %29(s1), %bb.4, %20(s1), %bb.3
540 %35:_(s1) = G_PHI %32(s1), %bb.4, %20(s1), %bb.3
541 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %28(s32)
542 %36:_(s1) = G_CONSTANT i1 true
543 %37:_(s1) = G_XOR %34, %36
544 %17:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %35(s1), %16(s32)
545 SI_LOOP %17(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
546 G_BR %bb.8
548 bb.8:
549 successors: %bb.2(0x80000000)
551 %14:_(s1) = G_PHI %37(s1), %bb.7
552 %38:_(s32) = G_PHI %17(s32), %bb.7
553 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %38(s32)
554 G_BR %bb.2
555 ...
557 ---
558 name: divergent_i1_icmp_used_outside_loop
559 legalized: true
560 tracksRegLiveness: true
561 body: |
562 ; GFX10-LABEL: name: divergent_i1_icmp_used_outside_loop
563 ; GFX10: bb.0:
564 ; GFX10-NEXT: successors: %bb.1(0x80000000)
565 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
566 ; GFX10-NEXT: {{ $}}
567 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
568 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
569 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
570 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
571 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
572 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr6
573 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr7
574 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
575 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
576 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
577 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
578 ; GFX10-NEXT: {{ $}}
579 ; GFX10-NEXT: bb.1:
580 ; GFX10-NEXT: successors: %bb.2(0x80000000)
581 ; GFX10-NEXT: {{ $}}
582 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[DEF1]](s1), %bb.0, %39(s1), %bb.6
583 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %11(s32), %bb.6, [[C]](s32), %bb.0
584 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %13(s32), %bb.6
585 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)
586 ; GFX10-NEXT: {{ $}}
587 ; GFX10-NEXT: bb.2:
588 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
589 ; GFX10-NEXT: {{ $}}
590 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[PHI2]]
591 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)
592 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
593 ; GFX10-NEXT: G_BR %bb.3
594 ; GFX10-NEXT: {{ $}}
595 ; GFX10-NEXT: bb.3:
596 ; GFX10-NEXT: successors: %bb.4(0x80000000)
597 ; GFX10-NEXT: {{ $}}
598 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32)
599 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
600 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32)
601 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64)
602 ; GFX10-NEXT: G_STORE [[PHI2]](s32), [[PTR_ADD]](p1) :: (store (s32), addrspace 1)
603 ; GFX10-NEXT: {{ $}}
604 ; GFX10-NEXT: bb.4:
605 ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
606 ; GFX10-NEXT: {{ $}}
607 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
608 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
609 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[PHI2]]
610 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[C2]](s1)
611 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[COPY8]](s1)
612 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec
613 ; GFX10-NEXT: G_BR %bb.5
614 ; GFX10-NEXT: {{ $}}
615 ; GFX10-NEXT: bb.5:
616 ; GFX10-NEXT: successors: %bb.6(0x80000000)
617 ; GFX10-NEXT: {{ $}}
618 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
619 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)
620 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
621 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C4]]
622 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc
623 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc
624 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
625 ; GFX10-NEXT: {{ $}}
626 ; GFX10-NEXT: bb.6:
627 ; GFX10-NEXT: successors: %bb.7(0x04000000), %bb.1(0x7c000000)
628 ; GFX10-NEXT: {{ $}}
629 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[COPY8]](s1), %bb.4, [[S_OR_B32_]](s1), %bb.5
630 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.5, [[DEF]](s32), %bb.4
631 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
632 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32)
633 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY11]](s1), [[PHI1]](s32)
634 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
635 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY7]](s1), implicit-def $scc
636 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
637 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
638 ; GFX10-NEXT: G_BR %bb.7
639 ; GFX10-NEXT: {{ $}}
640 ; GFX10-NEXT: bb.7:
641 ; GFX10-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000)
642 ; GFX10-NEXT: {{ $}}
643 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.6
644 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[PHI2]](s32), %bb.6
645 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_1]](s1)
646 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32)
647 ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY12]](s1), %bb.9, implicit-def $exec, implicit-def $scc, implicit $exec
648 ; GFX10-NEXT: G_BR %bb.8
649 ; GFX10-NEXT: {{ $}}
650 ; GFX10-NEXT: bb.8:
651 ; GFX10-NEXT: successors: %bb.9(0x80000000)
652 ; GFX10-NEXT: {{ $}}
653 ; GFX10-NEXT: G_STORE [[PHI6]](s32), [[MV1]](p1) :: (store (s32), addrspace 1)
654 ; GFX10-NEXT: {{ $}}
655 ; GFX10-NEXT: bb.9:
656 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32)
657 ; GFX10-NEXT: SI_RETURN
658 bb.0:
659 successors: %bb.1(0x80000000)
660 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
662 %0:_(s32) = COPY $vgpr0
663 %1:_(s32) = COPY $vgpr1
664 %2:_(s32) = COPY $vgpr2
665 %3:_(s32) = COPY $vgpr3
666 %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32)
667 %5:_(s32) = COPY $vgpr6
668 %6:_(s32) = COPY $vgpr7
669 %7:_(p1) = G_MERGE_VALUES %5(s32), %6(s32)
670 %8:_(s32) = G_CONSTANT i32 0
671 %9:_(s32) = G_IMPLICIT_DEF
673 bb.1:
674 successors: %bb.2(0x80000000)
676 %10:_(s32) = G_PHI %11(s32), %bb.6, %8(s32), %bb.0
677 %12:_(s32) = G_PHI %8(s32), %bb.0, %13(s32), %bb.6
679 bb.2:
680 successors: %bb.3(0x40000000), %bb.4(0x40000000)
682 %14:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %12
683 %15:sreg_32_xm0_xexec(s32) = SI_IF %14(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
684 G_BR %bb.3
686 bb.3:
687 successors: %bb.4(0x80000000)
689 %16:_(s64) = G_SEXT %12(s32)
690 %17:_(s32) = G_CONSTANT i32 2
691 %18:_(s64) = G_SHL %16, %17(s32)
692 %19:_(p1) = G_PTR_ADD %4, %18(s64)
693 G_STORE %12(s32), %19(p1) :: (store (s32), addrspace 1)
695 bb.4:
696 successors: %bb.5(0x40000000), %bb.6(0x40000000)
698 %20:_(s1) = G_CONSTANT i1 true
699 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
700 %21:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %1(s32), %12
701 %22:sreg_32_xm0_xexec(s32) = SI_IF %21(s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec
702 G_BR %bb.5
704 bb.5:
705 successors: %bb.6(0x80000000)
707 %23:_(s1) = G_CONSTANT i1 false
708 %24:_(s32) = G_CONSTANT i32 1
709 %25:_(s32) = G_ADD %12, %24
711 bb.6:
712 successors: %bb.7(0x04000000), %bb.1(0x7c000000)
714 %13:_(s32) = G_PHI %25(s32), %bb.5, %9(s32), %bb.4
715 %26:_(s1) = G_PHI %23(s1), %bb.5, %20(s1), %bb.4
716 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %22(s32)
717 %11:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %26(s1), %10(s32)
718 SI_LOOP %11(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
719 G_BR %bb.7
721 bb.7:
722 successors: %bb.8(0x40000000), %bb.9(0x40000000)
724 %27:_(s32) = G_PHI %11(s32), %bb.6
725 %28:sreg_32_xm0_xexec(s1) = G_PHI %14(s1), %bb.6
726 %29:_(s32) = G_PHI %12(s32), %bb.6
727 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32)
728 %30:sreg_32_xm0_xexec(s32) = SI_IF %28(s1), %bb.9, implicit-def $exec, implicit-def $scc, implicit $exec
729 G_BR %bb.8
731 bb.8:
732 successors: %bb.9(0x80000000)
734 G_STORE %29(s32), %7(p1) :: (store (s32), addrspace 1)
736 bb.9:
737 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %30(s32)
738 SI_RETURN
739 ...
741 ---
742 name: divergent_i1_freeze_used_outside_loop
743 legalized: true
744 tracksRegLiveness: true
745 body: |
746 ; GFX10-LABEL: name: divergent_i1_freeze_used_outside_loop
747 ; GFX10: bb.0:
748 ; GFX10-NEXT: successors: %bb.1(0x80000000)
749 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
750 ; GFX10-NEXT: {{ $}}
751 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
752 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
753 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
754 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
755 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
756 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
757 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
758 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
759 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
760 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
761 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
762 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
763 ; GFX10-NEXT: {{ $}}
764 ; GFX10-NEXT: bb.1:
765 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
766 ; GFX10-NEXT: {{ $}}
767 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %54(s1), %bb.3
768 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %43(s1), %bb.3
769 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[COPY5]](s1), %bb.0, %33(s1), %bb.3
770 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %10(s32), %bb.3, [[C]](s32), %bb.0
771 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %12(s32), %bb.3
772 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
773 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
774 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI2]](s1)
775 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[COPY8]](s1)
776 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc
777 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc
778 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
779 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
780 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY8]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
781 ; GFX10-NEXT: G_BR %bb.2
782 ; GFX10-NEXT: {{ $}}
783 ; GFX10-NEXT: bb.2:
784 ; GFX10-NEXT: successors: %bb.3(0x80000000)
785 ; GFX10-NEXT: {{ $}}
786 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI4]](s32)
787 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
788 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
789 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64)
790 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
791 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
792 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]]
793 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
794 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
795 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
796 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
797 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
798 ; GFX10-NEXT: {{ $}}
799 ; GFX10-NEXT: bb.3:
800 ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000)
801 ; GFX10-NEXT: {{ $}}
802 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_1]](s1), %bb.2
803 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[PHI2]](s1), %bb.1, [[DEF2]](s1), %bb.2
804 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)
805 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI6]](s1)
806 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
807 ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE [[COPY12]]
808 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[FREEZE]](s1)
809 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[FREEZE]](s1)
810 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
811 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI4]], [[C4]]
812 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[PHI4]](s32), [[COPY]]
813 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI3]](s32)
814 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY13]](s1), $exec_lo, implicit-def $scc
815 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY15]](s1), implicit-def $scc
816 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
817 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
818 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc
819 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
820 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
821 ; GFX10-NEXT: G_BR %bb.4
822 ; GFX10-NEXT: {{ $}}
823 ; GFX10-NEXT: bb.4:
824 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.3
825 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_3]](s1)
826 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI7]](s32)
827 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
828 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
829 ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY16]](s1), [[C6]], [[C5]]
830 ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV1]](p0) :: (store (s32))
831 ; GFX10-NEXT: S_ENDPGM 0
832 bb.0:
833 successors: %bb.1(0x80000000)
834 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
836 %0:_(s32) = COPY $vgpr0
837 %1:_(s32) = COPY $vgpr1
838 %2:_(s32) = COPY $vgpr2
839 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)
840 %4:_(s32) = COPY $vgpr3
841 %5:_(s32) = COPY $vgpr4
842 %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32)
843 %7:_(s32) = G_CONSTANT i32 0
844 %8:_(s1) = G_CONSTANT i1 true
846 bb.1:
847 successors: %bb.2(0x40000000), %bb.3(0x40000000)
849 %9:_(s32) = G_PHI %10(s32), %bb.3, %7(s32), %bb.0
850 %11:_(s32) = G_PHI %7(s32), %bb.0, %12(s32), %bb.3
851 %13:sreg_32_xm0_xexec(s1) = G_PHI %8(s1), %bb.0, %14(s1), %bb.3
852 %15:sreg_32_xm0_xexec(s32) = SI_IF %13(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec
853 G_BR %bb.2
855 bb.2:
856 successors: %bb.3(0x80000000)
858 %16:_(s64) = G_SEXT %11(s32)
859 %17:_(s32) = G_CONSTANT i32 2
860 %18:_(s64) = G_SHL %16, %17(s32)
861 %19:_(p1) = G_PTR_ADD %3, %18(s64)
862 %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)
863 %21:_(s32) = G_CONSTANT i32 0
864 %22:_(s1) = G_ICMP intpred(eq), %20(s32), %21
866 bb.3:
867 successors: %bb.4(0x04000000), %bb.1(0x7c000000)
869 %23:_(s1) = G_PHI %22(s1), %bb.2, %13(s1), %bb.1
870 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
871 %14:_(s1) = G_FREEZE %23
872 %24:_(s32) = G_CONSTANT i32 1
873 %12:_(s32) = G_ADD %11, %24
874 %25:_(s1) = G_ICMP intpred(slt), %11(s32), %0
875 %10:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %25(s1), %9(s32)
876 SI_LOOP %10(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
877 G_BR %bb.4
879 bb.4:
880 %26:_(s1) = G_PHI %14(s1), %bb.3
881 %27:_(s32) = G_PHI %10(s32), %bb.3
882 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32)
883 %28:_(s32) = G_FCONSTANT float 0.000000e+00
884 %29:_(s32) = G_FCONSTANT float 1.000000e+00
885 %30:_(s32) = G_SELECT %26(s1), %29, %28
886 G_STORE %30(s32), %6(p0) :: (store (s32))
887 S_ENDPGM 0
888 ...
890 ---
891 name: loop_with_1break
892 legalized: true
893 tracksRegLiveness: true
894 body: |
895 ; GFX10-LABEL: name: loop_with_1break
896 ; GFX10: bb.0:
897 ; GFX10-NEXT: successors: %bb.1(0x80000000)
898 ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
899 ; GFX10-NEXT: {{ $}}
900 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
901 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
902 ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
903 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
904 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
905 ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
906 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
907 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
908 ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
909 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
910 ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
911 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
912 ; GFX10-NEXT: [[DEF2:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
913 ; GFX10-NEXT: [[DEF3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
914 ; GFX10-NEXT: {{ $}}
915 ; GFX10-NEXT: bb.1:
916 ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
917 ; GFX10-NEXT: {{ $}}
918 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[DEF3]](s1), %bb.0, %67(s1), %bb.5
919 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF2]](s1), %bb.0, %56(s1), %bb.5
920 ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %43(s1), %bb.5
921 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0
922 ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5
923 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)
924 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
925 ; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI2]](s1)
926 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
927 ; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
928 ; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
929 ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI4]](s32)
930 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
931 ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
932 ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
933 ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
934 ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
935 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
936 ; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
937 ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY10]](s1), implicit-def $scc
938 ; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
939 ; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
940 ; GFX10-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc
941 ; GFX10-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc
942 ; GFX10-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
943 ; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_1]](s1)
944 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
945 ; GFX10-NEXT: G_BR %bb.3
946 ; GFX10-NEXT: {{ $}}
947 ; GFX10-NEXT: bb.2:
948 ; GFX10-NEXT: successors: %bb.4(0x80000000)
949 ; GFX10-NEXT: {{ $}}
950 ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
951 ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)
952 ; GFX10-NEXT: G_BR %bb.4
953 ; GFX10-NEXT: {{ $}}
954 ; GFX10-NEXT: bb.3:
955 ; GFX10-NEXT: successors: %bb.5(0x80000000)
956 ; GFX10-NEXT: {{ $}}
957 ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
958 ; GFX10-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)
959 ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
960 ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32)
961 ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)
962 ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
963 ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
964 ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]]
965 ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)
966 ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI4]], [[C7]]
967 ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 100
968 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI4]](s32), [[C8]]
969 ; GFX10-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)
970 ; GFX10-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY11]](s1), $exec_lo, implicit-def $scc
971 ; GFX10-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY13]](s1), implicit-def $scc
972 ; GFX10-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
973 ; GFX10-NEXT: [[S_ANDN2_B32_3:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc
974 ; GFX10-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY14]](s1), implicit-def $scc
975 ; GFX10-NEXT: [[S_OR_B32_3:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_3]](s1), [[S_AND_B32_3]](s1), implicit-def $scc
976 ; GFX10-NEXT: G_BR %bb.5
977 ; GFX10-NEXT: {{ $}}
978 ; GFX10-NEXT: bb.4:
979 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)
980 ; GFX10-NEXT: S_ENDPGM 0
981 ; GFX10-NEXT: {{ $}}
982 ; GFX10-NEXT: bb.5:
983 ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
984 ; GFX10-NEXT: {{ $}}
985 ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_1]](s1), %bb.1, [[S_OR_B32_3]](s1), %bb.3
986 ; GFX10-NEXT: [[PHI6:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_2]](s1), %bb.3
987 ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1
988 ; GFX10-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)
989 ; GFX10-NEXT: [[COPY16:%[0-9]+]]:sreg_32(s1) = COPY [[PHI6]](s1)
990 ; GFX10-NEXT: [[COPY17:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[COPY16]](s1)
991 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32)
992 ; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY15]](s1), [[PHI3]](s32)
993 ; GFX10-NEXT: [[S_ANDN2_B32_4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc
994 ; GFX10-NEXT: [[S_AND_B32_4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc
995 ; GFX10-NEXT: [[S_OR_B32_4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_4]](s1), [[S_AND_B32_4]](s1), implicit-def $scc
996 ; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
997 ; GFX10-NEXT: G_BR %bb.6
998 ; GFX10-NEXT: {{ $}}
999 ; GFX10-NEXT: bb.6:
1000 ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
1001 ; GFX10-NEXT: {{ $}}
1002 ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.5
1003 ; GFX10-NEXT: [[COPY18:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_4]](s1)
1004 ; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI8]](s32)
1005 ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY18]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
1006 ; GFX10-NEXT: G_BR %bb.2
1007 bb.0:
1008 successors: %bb.1(0x80000000)
1009 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
1011 %0:_(s32) = COPY $vgpr0
1012 %1:_(s32) = COPY $vgpr1
1013 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
1014 %3:_(s32) = COPY $vgpr2
1015 %4:_(s32) = COPY $vgpr3
1016 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)
1017 %6:_(s32) = COPY $vgpr4
1018 %7:_(s32) = COPY $vgpr5
1019 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)
1020 %9:_(s32) = G_CONSTANT i32 0
1021 %10:_(s32) = G_IMPLICIT_DEF
1023 bb.1:
1024 successors: %bb.3(0x40000000), %bb.5(0x40000000)
1026 %11:_(s32) = G_PHI %12(s32), %bb.5, %9(s32), %bb.0
1027 %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.5
1028 %15:_(s1) = G_CONSTANT i1 true
1029 %16:_(s64) = G_SEXT %13(s32)
1030 %17:_(s32) = G_CONSTANT i32 2
1031 %18:_(s64) = G_SHL %16, %17(s32)
1032 %19:_(p1) = G_PTR_ADD %5, %18(s64)
1033 %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1)
1034 %21:_(s32) = G_CONSTANT i32 0
1035 %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21
1036 %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec
1037 G_BR %bb.3
1039 bb.2:
1040 successors: %bb.4(0x80000000)
1042 %24:_(s32) = G_CONSTANT i32 10
1043 G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1)
1044 G_BR %bb.4
1046 bb.3:
1047 successors: %bb.5(0x80000000)
1049 %25:_(s1) = G_CONSTANT i1 false
1050 %26:_(s32) = G_CONSTANT i32 2
1051 %27:_(s64) = G_SHL %16, %26(s32)
1052 %28:_(p1) = G_PTR_ADD %2, %27(s64)
1053 %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1)
1054 %30:_(s32) = G_CONSTANT i32 1
1055 %31:_(s32) = G_ADD %29, %30
1056 G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1)
1057 %32:_(s32) = G_ADD %13, %30
1058 %33:_(s32) = G_CONSTANT i32 100
1059 %34:_(s1) = G_ICMP intpred(ult), %13(s32), %33
1060 G_BR %bb.5
1062 bb.4:
1063 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32)
1064 S_ENDPGM 0
1066 bb.5:
1067 successors: %bb.6(0x04000000), %bb.1(0x7c000000)
1069 %14:_(s32) = G_PHI %32(s32), %bb.3, %10(s32), %bb.1
1070 %36:_(s1) = G_PHI %25(s1), %bb.3, %15(s1), %bb.1
1071 %37:_(s1) = G_PHI %34(s1), %bb.3, %15(s1), %bb.1
1072 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32)
1073 %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32)
1074 SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
1075 G_BR %bb.6
1077 bb.6:
1078 successors: %bb.2(0x40000000), %bb.4(0x40000000)
1080 %38:sreg_32_xm0_xexec(s1) = G_PHI %36(s1), %bb.5
1081 %39:_(s32) = G_PHI %12(s32), %bb.5
1082 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %39(s32)
1083 %35:sreg_32_xm0_xexec(s32) = SI_IF %38(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
1084 G_BR %bb.2
1085 ...