| blob | fe5601594dca8d3242c7b352c45c38d567235930 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,SI %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=SICI,CI %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
7 declare half @llvm.nearbyint.f16(half) #0
8 declare float @llvm.nearbyint.f32(float) #0
9 declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) #0
10 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #0
11 declare double @llvm.nearbyint.f64(double) #0
12 declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) #0
13 declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) #0
15 define amdgpu_kernel void @fnearbyint_f16(ptr addrspace(1) %out, half %in) #1 {
16 ; SI-LABEL: fnearbyint_f16:
17 ; SI: ; %bb.0:
18 ; SI-NEXT: s_load_dword s6, s[4:5], 0xb
19 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
20 ; SI-NEXT: s_mov_b32 s3, 0xf000
21 ; SI-NEXT: s_mov_b32 s2, -1
22 ; SI-NEXT: s_waitcnt lgkmcnt(0)
23 ; SI-NEXT: v_cvt_f32_f16_e32 v0, s6
24 ; SI-NEXT: v_rndne_f32_e32 v0, v0
25 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
26 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
27 ; SI-NEXT: s_endpgm
28 ;
29 ; CI-LABEL: fnearbyint_f16:
30 ; CI: ; %bb.0:
31 ; CI-NEXT: s_load_dword s0, s[4:5], 0xb
32 ; CI-NEXT: s_mov_b32 s3, 0xf000
33 ; CI-NEXT: s_mov_b32 s2, -1
34 ; CI-NEXT: s_waitcnt lgkmcnt(0)
35 ; CI-NEXT: v_cvt_f32_f16_e32 v0, s0
36 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
37 ; CI-NEXT: v_rndne_f32_e32 v0, v0
38 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
39 ; CI-NEXT: s_waitcnt lgkmcnt(0)
40 ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0
41 ; CI-NEXT: s_endpgm
42 ;
43 ; VI-LABEL: fnearbyint_f16:
44 ; VI: ; %bb.0:
45 ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
46 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
47 ; VI-NEXT: s_waitcnt lgkmcnt(0)
48 ; VI-NEXT: v_rndne_f16_e32 v2, s2
49 ; VI-NEXT: v_mov_b32_e32 v0, s0
50 ; VI-NEXT: v_mov_b32_e32 v1, s1
51 ; VI-NEXT: flat_store_short v[0:1], v2
52 ; VI-NEXT: s_endpgm
53 ;
54 ; GFX11-LABEL: fnearbyint_f16:
55 ; GFX11: ; %bb.0:
56 ; GFX11-NEXT: s_clause 0x1
57 ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
58 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
59 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
60 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
61 ; GFX11-NEXT: v_rndne_f16_e32 v1, s2
62 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
63 ; GFX11-NEXT: s_endpgm
64 %1 = call half @llvm.nearbyint.f16(half %in)
65 store half %1, ptr addrspace(1) %out
66 ret void
67 }
69 define amdgpu_kernel void @fnearbyint_f32(ptr addrspace(1) %out, float %in) #1 {
70 ; SICI-LABEL: fnearbyint_f32:
71 ; SICI: ; %bb.0: ; %entry
72 ; SICI-NEXT: s_load_dword s6, s[4:5], 0xb
73 ; SICI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
74 ; SICI-NEXT: s_mov_b32 s3, 0xf000
75 ; SICI-NEXT: s_mov_b32 s2, -1
76 ; SICI-NEXT: s_waitcnt lgkmcnt(0)
77 ; SICI-NEXT: v_rndne_f32_e32 v0, s6
78 ; SICI-NEXT: buffer_store_dword v0, off, s[0:3], 0
79 ; SICI-NEXT: s_endpgm
80 ;
81 ; VI-LABEL: fnearbyint_f32:
82 ; VI: ; %bb.0: ; %entry
83 ; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
84 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
85 ; VI-NEXT: s_waitcnt lgkmcnt(0)
86 ; VI-NEXT: v_rndne_f32_e32 v2, s2
87 ; VI-NEXT: v_mov_b32_e32 v0, s0
88 ; VI-NEXT: v_mov_b32_e32 v1, s1
89 ; VI-NEXT: flat_store_dword v[0:1], v2
90 ; VI-NEXT: s_endpgm
91 ;
92 ; GFX11-LABEL: fnearbyint_f32:
93 ; GFX11: ; %bb.0: ; %entry
94 ; GFX11-NEXT: s_clause 0x1
95 ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
96 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
97 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
98 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
99 ; GFX11-NEXT: v_rndne_f32_e32 v1, s2
100 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
101 ; GFX11-NEXT: s_endpgm
102 entry:
103 %0 = call float @llvm.nearbyint.f32(float %in)
104 store float %0, ptr addrspace(1) %out
105 ret void
106 }
108 define amdgpu_kernel void @fnearbyint_v2f32(ptr addrspace(1) %out, <2 x float> %in) #1 {
109 ; SICI-LABEL: fnearbyint_v2f32:
110 ; SICI: ; %bb.0: ; %entry
111 ; SICI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
112 ; SICI-NEXT: s_mov_b32 s7, 0xf000
113 ; SICI-NEXT: s_mov_b32 s6, -1
114 ; SICI-NEXT: s_waitcnt lgkmcnt(0)
115 ; SICI-NEXT: s_mov_b32 s4, s0
116 ; SICI-NEXT: s_mov_b32 s5, s1
117 ; SICI-NEXT: v_rndne_f32_e32 v1, s3
118 ; SICI-NEXT: v_rndne_f32_e32 v0, s2
119 ; SICI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
120 ; SICI-NEXT: s_endpgm
121 ;
122 ; VI-LABEL: fnearbyint_v2f32:
123 ; VI: ; %bb.0: ; %entry
124 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
125 ; VI-NEXT: s_waitcnt lgkmcnt(0)
126 ; VI-NEXT: v_mov_b32_e32 v3, s1
127 ; VI-NEXT: v_rndne_f32_e32 v1, s3
128 ; VI-NEXT: v_rndne_f32_e32 v0, s2
129 ; VI-NEXT: v_mov_b32_e32 v2, s0
130 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
131 ; VI-NEXT: s_endpgm
132 ;
133 ; GFX11-LABEL: fnearbyint_v2f32:
134 ; GFX11: ; %bb.0: ; %entry
135 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
136 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
137 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
138 ; GFX11-NEXT: v_rndne_f32_e32 v1, s3
139 ; GFX11-NEXT: v_rndne_f32_e32 v0, s2
140 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
141 ; GFX11-NEXT: s_endpgm
142 entry:
143 %0 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %in)
144 store <2 x float> %0, ptr addrspace(1) %out
145 ret void
146 }
148 define amdgpu_kernel void @fnearbyint_v4f32(ptr addrspace(1) %out, <4 x float> %in) #1 {
149 ; SICI-LABEL: fnearbyint_v4f32:
150 ; SICI: ; %bb.0: ; %entry
151 ; SICI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
152 ; SICI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
153 ; SICI-NEXT: s_mov_b32 s7, 0xf000
154 ; SICI-NEXT: s_mov_b32 s6, -1
155 ; SICI-NEXT: s_waitcnt lgkmcnt(0)
156 ; SICI-NEXT: v_rndne_f32_e32 v3, s3
157 ; SICI-NEXT: v_rndne_f32_e32 v2, s2
158 ; SICI-NEXT: v_rndne_f32_e32 v1, s1
159 ; SICI-NEXT: v_rndne_f32_e32 v0, s0
160 ; SICI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
161 ; SICI-NEXT: s_endpgm
162 ;
163 ; VI-LABEL: fnearbyint_v4f32:
164 ; VI: ; %bb.0: ; %entry
165 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
166 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
167 ; VI-NEXT: s_waitcnt lgkmcnt(0)
168 ; VI-NEXT: v_rndne_f32_e32 v3, s3
169 ; VI-NEXT: v_mov_b32_e32 v4, s4
170 ; VI-NEXT: v_rndne_f32_e32 v2, s2
171 ; VI-NEXT: v_rndne_f32_e32 v1, s1
172 ; VI-NEXT: v_rndne_f32_e32 v0, s0
173 ; VI-NEXT: v_mov_b32_e32 v5, s5
174 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
175 ; VI-NEXT: s_endpgm
176 ;
177 ; GFX11-LABEL: fnearbyint_v4f32:
178 ; GFX11: ; %bb.0: ; %entry
179 ; GFX11-NEXT: s_clause 0x1
180 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
181 ; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
182 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
183 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
184 ; GFX11-NEXT: v_rndne_f32_e32 v3, s3
185 ; GFX11-NEXT: v_rndne_f32_e32 v2, s2
186 ; GFX11-NEXT: v_rndne_f32_e32 v1, s1
187 ; GFX11-NEXT: v_rndne_f32_e32 v0, s0
188 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
189 ; GFX11-NEXT: s_endpgm
190 entry:
191 %0 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %in)
192 store <4 x float> %0, ptr addrspace(1) %out
193 ret void
194 }
196 define amdgpu_kernel void @nearbyint_f64(ptr addrspace(1) %out, double %in) {
197 ; SI-LABEL: nearbyint_f64:
198 ; SI: ; %bb.0: ; %entry
199 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
200 ; SI-NEXT: s_mov_b32 s7, 0xf000
201 ; SI-NEXT: s_mov_b32 s6, -1
202 ; SI-NEXT: s_brev_b32 s8, -2
203 ; SI-NEXT: v_mov_b32_e32 v1, 0x43300000
204 ; SI-NEXT: v_mov_b32_e32 v0, 0
205 ; SI-NEXT: v_mov_b32_e32 v2, -1
206 ; SI-NEXT: v_mov_b32_e32 v3, 0x432fffff
207 ; SI-NEXT: s_waitcnt lgkmcnt(0)
208 ; SI-NEXT: s_mov_b32 s4, s0
209 ; SI-NEXT: s_mov_b32 s5, s1
210 ; SI-NEXT: v_mov_b32_e32 v6, s3
211 ; SI-NEXT: v_bfi_b32 v1, s8, v1, v6
212 ; SI-NEXT: v_mov_b32_e32 v7, s2
213 ; SI-NEXT: v_add_f64 v[4:5], s[2:3], v[0:1]
214 ; SI-NEXT: v_add_f64 v[0:1], v[4:5], -v[0:1]
215 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[2:3]
216 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
217 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
218 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
219 ; SI-NEXT: s_endpgm
220 ;
221 ; CI-LABEL: nearbyint_f64:
222 ; CI: ; %bb.0: ; %entry
223 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
224 ; CI-NEXT: s_waitcnt lgkmcnt(0)
225 ; CI-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
226 ; CI-NEXT: s_mov_b32 s3, 0xf000
227 ; CI-NEXT: s_mov_b32 s2, -1
228 ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
229 ; CI-NEXT: s_endpgm
230 ;
231 ; VI-LABEL: nearbyint_f64:
232 ; VI: ; %bb.0: ; %entry
233 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
234 ; VI-NEXT: s_waitcnt lgkmcnt(0)
235 ; VI-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
236 ; VI-NEXT: v_mov_b32_e32 v2, s0
237 ; VI-NEXT: v_mov_b32_e32 v3, s1
238 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
239 ; VI-NEXT: s_endpgm
240 ;
241 ; GFX11-LABEL: nearbyint_f64:
242 ; GFX11: ; %bb.0: ; %entry
243 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
244 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
245 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
246 ; GFX11-NEXT: v_rndne_f64_e32 v[0:1], s[2:3]
247 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
248 ; GFX11-NEXT: s_endpgm
249 entry:
250 %0 = call double @llvm.nearbyint.f64(double %in)
251 store double %0, ptr addrspace(1) %out
252 ret void
253 }
254 define amdgpu_kernel void @nearbyint_v2f64(ptr addrspace(1) %out, <2 x double> %in) {
255 ; SI-LABEL: nearbyint_v2f64:
256 ; SI: ; %bb.0: ; %entry
257 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
258 ; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd
259 ; SI-NEXT: s_mov_b32 s3, 0xf000
260 ; SI-NEXT: s_mov_b32 s2, -1
261 ; SI-NEXT: s_brev_b32 s10, -2
262 ; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
263 ; SI-NEXT: s_mov_b32 s9, 0x432fffff
264 ; SI-NEXT: v_mov_b32_e32 v0, 0
265 ; SI-NEXT: s_mov_b32 s8, s2
266 ; SI-NEXT: v_mov_b32_e32 v4, s8
267 ; SI-NEXT: v_mov_b32_e32 v5, s9
268 ; SI-NEXT: s_waitcnt lgkmcnt(0)
269 ; SI-NEXT: v_mov_b32_e32 v7, s7
270 ; SI-NEXT: v_bfi_b32 v1, s10, v6, v7
271 ; SI-NEXT: v_mov_b32_e32 v8, s6
272 ; SI-NEXT: v_mov_b32_e32 v9, s5
273 ; SI-NEXT: v_mov_b32_e32 v10, s4
274 ; SI-NEXT: v_add_f64 v[2:3], s[6:7], v[0:1]
275 ; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[0:1]
276 ; SI-NEXT: v_bfi_b32 v1, s10, v6, v9
277 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, v[4:5]
278 ; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
279 ; SI-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
280 ; SI-NEXT: v_add_f64 v[6:7], s[4:5], v[0:1]
281 ; SI-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
282 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, v[4:5]
283 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
284 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
285 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
286 ; SI-NEXT: s_endpgm
287 ;
288 ; CI-LABEL: nearbyint_v2f64:
289 ; CI: ; %bb.0: ; %entry
290 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
291 ; CI-NEXT: s_waitcnt lgkmcnt(0)
292 ; CI-NEXT: v_rndne_f64_e32 v[2:3], s[2:3]
293 ; CI-NEXT: v_rndne_f64_e32 v[0:1], s[0:1]
294 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
295 ; CI-NEXT: s_mov_b32 s3, 0xf000
296 ; CI-NEXT: s_mov_b32 s2, -1
297 ; CI-NEXT: s_waitcnt lgkmcnt(0)
298 ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
299 ; CI-NEXT: s_endpgm
300 ;
301 ; VI-LABEL: nearbyint_v2f64:
302 ; VI: ; %bb.0: ; %entry
303 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
304 ; VI-NEXT: s_waitcnt lgkmcnt(0)
305 ; VI-NEXT: v_rndne_f64_e32 v[2:3], s[2:3]
306 ; VI-NEXT: v_rndne_f64_e32 v[0:1], s[0:1]
307 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
308 ; VI-NEXT: s_waitcnt lgkmcnt(0)
309 ; VI-NEXT: v_mov_b32_e32 v5, s1
310 ; VI-NEXT: v_mov_b32_e32 v4, s0
311 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
312 ; VI-NEXT: s_endpgm
313 ;
314 ; GFX11-LABEL: nearbyint_v2f64:
315 ; GFX11: ; %bb.0: ; %entry
316 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
317 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
318 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
319 ; GFX11-NEXT: v_rndne_f64_e32 v[2:3], s[2:3]
320 ; GFX11-NEXT: v_rndne_f64_e32 v[0:1], s[0:1]
321 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
322 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
323 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
324 ; GFX11-NEXT: s_endpgm
325 entry:
326 %0 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %in)
327 store <2 x double> %0, ptr addrspace(1) %out
328 ret void
329 }
331 define amdgpu_kernel void @nearbyint_v4f64(ptr addrspace(1) %out, <4 x double> %in) {
332 ; SI-LABEL: nearbyint_v4f64:
333 ; SI: ; %bb.0: ; %entry
334 ; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x9
335 ; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x11
336 ; SI-NEXT: s_mov_b32 s11, 0xf000
337 ; SI-NEXT: s_mov_b32 s10, -1
338 ; SI-NEXT: s_brev_b32 s14, -2
339 ; SI-NEXT: v_mov_b32_e32 v10, 0x43300000
340 ; SI-NEXT: s_mov_b32 s13, 0x432fffff
341 ; SI-NEXT: v_mov_b32_e32 v4, 0
342 ; SI-NEXT: s_mov_b32 s12, s10
343 ; SI-NEXT: v_mov_b32_e32 v8, s12
344 ; SI-NEXT: v_mov_b32_e32 v9, s13
345 ; SI-NEXT: s_waitcnt lgkmcnt(0)
346 ; SI-NEXT: v_mov_b32_e32 v2, s3
347 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v2
348 ; SI-NEXT: v_mov_b32_e32 v6, s2
349 ; SI-NEXT: v_mov_b32_e32 v7, s1
350 ; SI-NEXT: v_mov_b32_e32 v11, s0
351 ; SI-NEXT: v_mov_b32_e32 v12, s7
352 ; SI-NEXT: v_mov_b32_e32 v13, s6
353 ; SI-NEXT: v_mov_b32_e32 v14, s5
354 ; SI-NEXT: v_mov_b32_e32 v15, s4
355 ; SI-NEXT: v_add_f64 v[0:1], s[2:3], v[4:5]
356 ; SI-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]
357 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v7
358 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[8:9]
359 ; SI-NEXT: v_cndmask_b32_e32 v3, v1, v2, vcc
360 ; SI-NEXT: v_cndmask_b32_e32 v2, v0, v6, vcc
361 ; SI-NEXT: v_add_f64 v[0:1], s[0:1], v[4:5]
362 ; SI-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]
363 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v12
364 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[0:1]|, v[8:9]
365 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
366 ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc
367 ; SI-NEXT: v_add_f64 v[6:7], s[6:7], v[4:5]
368 ; SI-NEXT: v_add_f64 v[6:7], v[6:7], -v[4:5]
369 ; SI-NEXT: v_bfi_b32 v5, s14, v10, v14
370 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, v[8:9]
371 ; SI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
372 ; SI-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
373 ; SI-NEXT: v_add_f64 v[10:11], s[4:5], v[4:5]
374 ; SI-NEXT: v_add_f64 v[4:5], v[10:11], -v[4:5]
375 ; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, v[8:9]
376 ; SI-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
377 ; SI-NEXT: v_cndmask_b32_e32 v4, v4, v15, vcc
378 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
379 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
380 ; SI-NEXT: s_endpgm
381 ;
382 ; CI-LABEL: nearbyint_v4f64:
383 ; CI: ; %bb.0: ; %entry
384 ; CI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x11
385 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
386 ; CI-NEXT: s_mov_b32 s3, 0xf000
387 ; CI-NEXT: s_mov_b32 s2, -1
388 ; CI-NEXT: s_waitcnt lgkmcnt(0)
389 ; CI-NEXT: v_rndne_f64_e32 v[6:7], s[14:15]
390 ; CI-NEXT: v_rndne_f64_e32 v[4:5], s[12:13]
391 ; CI-NEXT: v_rndne_f64_e32 v[2:3], s[10:11]
392 ; CI-NEXT: v_rndne_f64_e32 v[0:1], s[8:9]
393 ; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
394 ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
395 ; CI-NEXT: s_endpgm
396 ;
397 ; VI-LABEL: nearbyint_v4f64:
398 ; VI: ; %bb.0: ; %entry
399 ; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x44
400 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
401 ; VI-NEXT: s_waitcnt lgkmcnt(0)
402 ; VI-NEXT: v_rndne_f64_e32 v[6:7], s[14:15]
403 ; VI-NEXT: v_rndne_f64_e32 v[4:5], s[12:13]
404 ; VI-NEXT: v_rndne_f64_e32 v[2:3], s[10:11]
405 ; VI-NEXT: v_rndne_f64_e32 v[0:1], s[8:9]
406 ; VI-NEXT: s_add_u32 s2, s0, 16
407 ; VI-NEXT: s_addc_u32 s3, s1, 0
408 ; VI-NEXT: v_mov_b32_e32 v11, s3
409 ; VI-NEXT: v_mov_b32_e32 v9, s1
410 ; VI-NEXT: v_mov_b32_e32 v10, s2
411 ; VI-NEXT: v_mov_b32_e32 v8, s0
412 ; VI-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
413 ; VI-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
414 ; VI-NEXT: s_endpgm
415 ;
416 ; GFX11-LABEL: nearbyint_v4f64:
417 ; GFX11: ; %bb.0: ; %entry
418 ; GFX11-NEXT: s_clause 0x1
419 ; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x44
420 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
421 ; GFX11-NEXT: v_mov_b32_e32 v8, 0
422 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
423 ; GFX11-NEXT: v_rndne_f64_e32 v[6:7], s[14:15]
424 ; GFX11-NEXT: v_rndne_f64_e32 v[4:5], s[12:13]
425 ; GFX11-NEXT: v_rndne_f64_e32 v[2:3], s[10:11]
426 ; GFX11-NEXT: v_rndne_f64_e32 v[0:1], s[8:9]
427 ; GFX11-NEXT: s_clause 0x1
428 ; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
429 ; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1]
430 ; GFX11-NEXT: s_endpgm
431 entry:
432 %0 = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %in)
433 store <4 x double> %0, ptr addrspace(1) %out
434 ret void
435 }
437 attributes #0 = { nounwind readonly }
438 attributes #1 = { nounwind }