| blob | d62f045674acec6e89c1f094b17c8225053606a7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX12 %s
5 define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
6 ; GFX10-LABEL: _amdgpu_cs_main:
7 ; GFX10: ; %bb.0: ; %branch1_true
8 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
9 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
10 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
11 ; GFX10-NEXT: s_mov_b32 s4, 0
12 ; GFX10-NEXT: s_mov_b32 s1, 0
13 ; GFX10-NEXT: ; implicit-def: $sgpr2
14 ; GFX10-NEXT: s_inst_prefetch 0x1
15 ; GFX10-NEXT: s_branch .LBB0_2
16 ; GFX10-NEXT: .p2align 6
17 ; GFX10-NEXT: .LBB0_1: ; %Flow
18 ; GFX10-NEXT: ; in Loop: Header=BB0_2 Depth=1
19 ; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3
20 ; GFX10-NEXT: v_mov_b32_e32 v1, v0
21 ; GFX10-NEXT: s_and_b32 s0, exec_lo, s2
22 ; GFX10-NEXT: s_or_b32 s1, s0, s1
23 ; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s1
24 ; GFX10-NEXT: s_cbranch_execz .LBB0_4
25 ; GFX10-NEXT: .LBB0_2: ; %bb
26 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
27 ; GFX10-NEXT: s_or_b32 s2, s2, exec_lo
28 ; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo
29 ; GFX10-NEXT: s_cbranch_execz .LBB0_1
30 ; GFX10-NEXT: ; %bb.3: ; %branch2_merge
31 ; GFX10-NEXT: ; in Loop: Header=BB0_2 Depth=1
32 ; GFX10-NEXT: s_mov_b32 s5, s4
33 ; GFX10-NEXT: s_mov_b32 s6, s4
34 ; GFX10-NEXT: s_mov_b32 s7, s4
35 ; GFX10-NEXT: s_mov_b32 s8, s4
36 ; GFX10-NEXT: s_mov_b32 s9, s4
37 ; GFX10-NEXT: s_mov_b32 s10, s4
38 ; GFX10-NEXT: s_mov_b32 s11, s4
39 ; GFX10-NEXT: s_mov_b32 s12, s4
40 ; GFX10-NEXT: s_mov_b32 s13, s4
41 ; GFX10-NEXT: s_mov_b32 s14, s4
42 ; GFX10-NEXT: s_mov_b32 s15, s4
43 ; GFX10-NEXT: s_andn2_b32 s2, s2, exec_lo
44 ; GFX10-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
45 ; GFX10-NEXT: s_waitcnt vmcnt(0)
46 ; GFX10-NEXT: v_fma_f32 v1, v1, v0, 0
47 ; GFX10-NEXT: v_cmp_le_f32_e64 s0, 0, v1
48 ; GFX10-NEXT: s_and_b32 s0, s0, exec_lo
49 ; GFX10-NEXT: s_or_b32 s2, s2, s0
50 ; GFX10-NEXT: s_branch .LBB0_1
51 ; GFX10-NEXT: .LBB0_4: ; %loop0_merge
52 ; GFX10-NEXT: s_inst_prefetch 0x2
53 ; GFX10-NEXT: s_endpgm
54 ;
55 ; GFX12-LABEL: _amdgpu_cs_main:
56 ; GFX12: ; %bb.0: ; %branch1_true
57 ; GFX12-NEXT: v_mov_b32_e32 v2, 0
58 ; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1
59 ; GFX12-NEXT: v_mov_b32_e32 v1, 0
60 ; GFX12-NEXT: s_mov_b32 s4, 0
61 ; GFX12-NEXT: s_mov_b32 s1, 0
62 ; GFX12-NEXT: ; implicit-def: $sgpr2
63 ; GFX12-NEXT: s_branch .LBB0_2
64 ; GFX12-NEXT: .LBB0_1: ; %Flow
65 ; GFX12-NEXT: ; in Loop: Header=BB0_2 Depth=1
66 ; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s3
67 ; GFX12-NEXT: v_mov_b32_e32 v1, v0
68 ; GFX12-NEXT: s_and_b32 s0, exec_lo, s2
69 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
70 ; GFX12-NEXT: s_or_b32 s1, s0, s1
71 ; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s1
72 ; GFX12-NEXT: s_cbranch_execz .LBB0_4
73 ; GFX12-NEXT: .LBB0_2: ; %bb
74 ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
75 ; GFX12-NEXT: s_or_b32 s2, s2, exec_lo
76 ; GFX12-NEXT: s_and_saveexec_b32 s3, vcc_lo
77 ; GFX12-NEXT: s_cbranch_execz .LBB0_1
78 ; GFX12-NEXT: ; %bb.3: ; %branch2_merge
79 ; GFX12-NEXT: ; in Loop: Header=BB0_2 Depth=1
80 ; GFX12-NEXT: s_mov_b32 s5, s4
81 ; GFX12-NEXT: s_mov_b32 s6, s4
82 ; GFX12-NEXT: s_mov_b32 s7, s4
83 ; GFX12-NEXT: s_mov_b32 s8, s4
84 ; GFX12-NEXT: s_mov_b32 s9, s4
85 ; GFX12-NEXT: s_mov_b32 s10, s4
86 ; GFX12-NEXT: s_mov_b32 s11, s4
87 ; GFX12-NEXT: s_mov_b32 s12, s4
88 ; GFX12-NEXT: s_mov_b32 s13, s4
89 ; GFX12-NEXT: s_mov_b32 s14, s4
90 ; GFX12-NEXT: s_mov_b32 s15, s4
91 ; GFX12-NEXT: s_and_not1_b32 s2, s2, exec_lo
92 ; GFX12-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
93 ; GFX12-NEXT: s_wait_samplecnt 0x0
94 ; GFX12-NEXT: v_fma_f32 v1, v1, v0, 0
95 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
96 ; GFX12-NEXT: v_cmp_le_f32_e64 s0, 0, v1
97 ; GFX12-NEXT: s_and_b32 s0, s0, exec_lo
98 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
99 ; GFX12-NEXT: s_or_b32 s2, s2, s0
100 ; GFX12-NEXT: s_branch .LBB0_1
101 ; GFX12-NEXT: .LBB0_4: ; %loop0_merge
102 ; GFX12-NEXT: s_endpgm
103 branch1_true:
104 br label %bb
106 bb: ; preds = %branch2_merge, %branch1_true
107 %r1.8.vec.insert14.i1 = phi float [ 0.000000e+00, %branch1_true ], [ %0, %branch2_merge ]
108 %i = icmp eq i32 %1, 0
109 br i1 %i, label %loop0_merge, label %branch2_merge
111 branch2_merge: ; preds = %bb
112 %i2 = call float @llvm.amdgcn.image.sample.lz.3d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, float %r1.8.vec.insert14.i1, <8 x i32> zeroinitializer, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
113 %i3 = call reassoc nnan nsz arcp contract afn float @llvm.fma.f32(float %i2, float %0, float 0.000000e+00)
114 %i4 = fcmp ult float %i3, 0.000000e+00
115 br i1 %i4, label %bb, label %loop0_merge
117 loop0_merge: ; preds = %branch2_merge, %bb
118 ret void
119 }
121 ; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
122 declare float @llvm.fma.f32(float, float, float) #0
124 ; Function Attrs: nounwind readonly willreturn
125 declare float @llvm.amdgcn.image.sample.lz.3d.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
127 attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
128 attributes #1 = { nounwind readonly willreturn }