| blob | db56589b799ddac99189ac83b6295ddd835295e2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
3 ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
6 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
8 define amdgpu_kernel void @rotr_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
9 ; R600-LABEL: rotr_i32:
10 ; R600: ; %bb.0: ; %entry
11 ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
12 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
13 ; R600-NEXT: CF_END
14 ; R600-NEXT: PAD
15 ; R600-NEXT: ALU clause starting at 4:
16 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
17 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
18 ; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].Z, KC0[2].W,
19 ;
20 ; SI-LABEL: rotr_i32:
21 ; SI: ; %bb.0: ; %entry
22 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
23 ; SI-NEXT: s_mov_b32 s7, 0xf000
24 ; SI-NEXT: s_mov_b32 s6, -1
25 ; SI-NEXT: s_waitcnt lgkmcnt(0)
26 ; SI-NEXT: s_mov_b32 s4, s0
27 ; SI-NEXT: s_mov_b32 s5, s1
28 ; SI-NEXT: v_mov_b32_e32 v0, s3
29 ; SI-NEXT: v_alignbit_b32 v0, s2, s2, v0
30 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
31 ; SI-NEXT: s_endpgm
32 ;
33 ; GFX8-LABEL: rotr_i32:
34 ; GFX8: ; %bb.0: ; %entry
35 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
36 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
37 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
38 ; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v0
39 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
40 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
41 ; GFX8-NEXT: flat_store_dword v[0:1], v2
42 ; GFX8-NEXT: s_endpgm
43 ;
44 ; GFX10-LABEL: rotr_i32:
45 ; GFX10: ; %bb.0: ; %entry
46 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
47 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
48 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
49 ; GFX10-NEXT: v_alignbit_b32 v1, s2, s2, s3
50 ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
51 ; GFX10-NEXT: s_endpgm
52 ;
53 ; GFX11-LABEL: rotr_i32:
54 ; GFX11: ; %bb.0: ; %entry
55 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
56 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
57 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
58 ; GFX11-NEXT: v_alignbit_b32 v1, s2, s2, s3
59 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
60 ; GFX11-NEXT: s_endpgm
61 entry:
62 %tmp0 = sub i32 32, %y
63 %tmp1 = shl i32 %x, %tmp0
64 %tmp2 = lshr i32 %x, %y
65 %tmp3 = or i32 %tmp1, %tmp2
66 store i32 %tmp3, ptr addrspace(1) %in
67 ret void
68 }
70 define amdgpu_kernel void @rotr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
71 ; R600-LABEL: rotr_v2i32:
72 ; R600: ; %bb.0: ; %entry
73 ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
74 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
75 ; R600-NEXT: CF_END
76 ; R600-NEXT: PAD
77 ; R600-NEXT: ALU clause starting at 4:
78 ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].X, KC0[3].Z,
79 ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[2].W, KC0[3].Y,
80 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
81 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
82 ;
83 ; SI-LABEL: rotr_v2i32:
84 ; SI: ; %bb.0: ; %entry
85 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
86 ; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
87 ; SI-NEXT: s_mov_b32 s7, 0xf000
88 ; SI-NEXT: s_mov_b32 s6, -1
89 ; SI-NEXT: s_waitcnt lgkmcnt(0)
90 ; SI-NEXT: v_mov_b32_e32 v0, s3
91 ; SI-NEXT: v_alignbit_b32 v1, s1, s1, v0
92 ; SI-NEXT: v_mov_b32_e32 v0, s2
93 ; SI-NEXT: v_alignbit_b32 v0, s0, s0, v0
94 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
95 ; SI-NEXT: s_endpgm
96 ;
97 ; GFX8-LABEL: rotr_v2i32:
98 ; GFX8: ; %bb.0: ; %entry
99 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
100 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
101 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
102 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
103 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
104 ; GFX8-NEXT: v_alignbit_b32 v1, s1, s1, v0
105 ; GFX8-NEXT: v_alignbit_b32 v0, s0, s0, v2
106 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
107 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
108 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
109 ; GFX8-NEXT: s_endpgm
110 ;
111 ; GFX10-LABEL: rotr_v2i32:
112 ; GFX10: ; %bb.0: ; %entry
113 ; GFX10-NEXT: s_clause 0x1
114 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
115 ; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
116 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
117 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
118 ; GFX10-NEXT: v_alignbit_b32 v1, s1, s1, s3
119 ; GFX10-NEXT: v_alignbit_b32 v0, s0, s0, s2
120 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
121 ; GFX10-NEXT: s_endpgm
122 ;
123 ; GFX11-LABEL: rotr_v2i32:
124 ; GFX11: ; %bb.0: ; %entry
125 ; GFX11-NEXT: s_clause 0x1
126 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
127 ; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
128 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
129 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
130 ; GFX11-NEXT: v_alignbit_b32 v1, s1, s1, s3
131 ; GFX11-NEXT: v_alignbit_b32 v0, s0, s0, s2
132 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[4:5]
133 ; GFX11-NEXT: s_endpgm
134 entry:
135 %tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
136 %tmp1 = shl <2 x i32> %x, %tmp0
137 %tmp2 = lshr <2 x i32> %x, %y
138 %tmp3 = or <2 x i32> %tmp1, %tmp2
139 store <2 x i32> %tmp3, ptr addrspace(1) %in
140 ret void
141 }
143 define amdgpu_kernel void @rotr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
144 ; R600-LABEL: rotr_v4i32:
145 ; R600: ; %bb.0: ; %entry
146 ; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
147 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
148 ; R600-NEXT: CF_END
149 ; R600-NEXT: PAD
150 ; R600-NEXT: ALU clause starting at 4:
151 ; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[4].X, KC0[5].X,
152 ; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[3].W, KC0[4].W,
153 ; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[3].Z, KC0[4].Z,
154 ; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[3].Y, KC0[4].Y,
155 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
156 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
157 ;
158 ; SI-LABEL: rotr_v4i32:
159 ; SI: ; %bb.0: ; %entry
160 ; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
161 ; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
162 ; SI-NEXT: s_mov_b32 s3, 0xf000
163 ; SI-NEXT: s_mov_b32 s2, -1
164 ; SI-NEXT: s_waitcnt lgkmcnt(0)
165 ; SI-NEXT: v_mov_b32_e32 v0, s15
166 ; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0
167 ; SI-NEXT: v_mov_b32_e32 v0, s14
168 ; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0
169 ; SI-NEXT: v_mov_b32_e32 v0, s13
170 ; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0
171 ; SI-NEXT: v_mov_b32_e32 v0, s12
172 ; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0
173 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
174 ; SI-NEXT: s_endpgm
175 ;
176 ; GFX8-LABEL: rotr_v4i32:
177 ; GFX8: ; %bb.0: ; %entry
178 ; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
179 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
180 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
181 ; GFX8-NEXT: v_mov_b32_e32 v0, s15
182 ; GFX8-NEXT: v_mov_b32_e32 v1, s14
183 ; GFX8-NEXT: v_mov_b32_e32 v4, s13
184 ; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0
185 ; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v1
186 ; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v4
187 ; GFX8-NEXT: v_mov_b32_e32 v0, s12
188 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
189 ; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0
190 ; GFX8-NEXT: v_mov_b32_e32 v4, s0
191 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
192 ; GFX8-NEXT: s_endpgm
193 ;
194 ; GFX10-LABEL: rotr_v4i32:
195 ; GFX10: ; %bb.0: ; %entry
196 ; GFX10-NEXT: s_clause 0x1
197 ; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
198 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
199 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
200 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
201 ; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s15
202 ; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s14
203 ; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s13
204 ; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s12
205 ; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
206 ; GFX10-NEXT: s_endpgm
207 ;
208 ; GFX11-LABEL: rotr_v4i32:
209 ; GFX11: ; %bb.0: ; %entry
210 ; GFX11-NEXT: s_clause 0x1
211 ; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
212 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
213 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
214 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
215 ; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s15
216 ; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s14
217 ; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s13
218 ; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s12
219 ; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
220 ; GFX11-NEXT: s_endpgm
221 entry:
222 %tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
223 %tmp1 = shl <4 x i32> %x, %tmp0
224 %tmp2 = lshr <4 x i32> %x, %y
225 %tmp3 = or <4 x i32> %tmp1, %tmp2
226 store <4 x i32> %tmp3, ptr addrspace(1) %in
227 ret void
228 }
230 declare i16 @llvm.fshr.i16(i16, i16, i16)
232 define void @test_rotr_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr addrspace(1) nocapture readonly %sourceB, ptr addrspace(1) nocapture %destValues) {
233 ; R600-LABEL: test_rotr_i16:
234 ; R600: ; %bb.0: ; %entry
235 ; R600-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
236 ; R600-NEXT: TEX 0 @8
237 ; R600-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
238 ; R600-NEXT: TEX 0 @10
239 ; R600-NEXT: ALU 21, @14, KC0[CB0:0-32], KC1[]
240 ; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
241 ; R600-NEXT: CF_END
242 ; R600-NEXT: PAD
243 ; R600-NEXT: Fetch clause starting at 8:
244 ; R600-NEXT: VTX_READ_16 T0.X, T0.X, 48, #1
245 ; R600-NEXT: Fetch clause starting at 10:
246 ; R600-NEXT: VTX_READ_16 T1.X, T1.X, 32, #1
247 ; R600-NEXT: ALU clause starting at 12:
248 ; R600-NEXT: MOV * T0.X, KC0[2].Z,
249 ; R600-NEXT: ALU clause starting at 13:
250 ; R600-NEXT: MOV * T1.X, KC0[2].Y,
251 ; R600-NEXT: ALU clause starting at 14:
252 ; R600-NEXT: SUB_INT T0.W, 0.0, T0.X,
253 ; R600-NEXT: AND_INT * T1.W, T0.X, literal.x,
254 ; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
255 ; R600-NEXT: AND_INT * T0.W, PV.W, literal.x,
256 ; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
257 ; R600-NEXT: LSHL T0.Z, T1.X, PV.W,
258 ; R600-NEXT: LSHR T0.W, T1.X, T1.W,
259 ; R600-NEXT: ADD_INT * T1.W, KC0[2].W, literal.x,
260 ; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
261 ; R600-NEXT: AND_INT T2.W, PS, literal.x,
262 ; R600-NEXT: OR_INT * T0.W, PV.W, PV.Z,
263 ; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
264 ; R600-NEXT: AND_INT T0.W, PS, literal.x,
265 ; R600-NEXT: LSHL * T2.W, PV.W, literal.y,
266 ; R600-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
267 ; R600-NEXT: LSHL T0.X, PV.W, PS,
268 ; R600-NEXT: LSHL * T0.W, literal.x, PS,
269 ; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
270 ; R600-NEXT: MOV T0.Y, 0.0,
271 ; R600-NEXT: MOV * T0.Z, 0.0,
272 ; R600-NEXT: LSHR * T1.X, T1.W, literal.x,
273 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
274 ;
275 ; SI-LABEL: test_rotr_i16:
276 ; SI: ; %bb.0: ; %entry
277 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
278 ; SI-NEXT: s_mov_b32 s6, 0
279 ; SI-NEXT: s_mov_b32 s7, 0xf000
280 ; SI-NEXT: s_mov_b32 s4, s6
281 ; SI-NEXT: s_mov_b32 s5, s6
282 ; SI-NEXT: buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:48
283 ; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:32
284 ; SI-NEXT: s_waitcnt vmcnt(1)
285 ; SI-NEXT: v_and_b32_e32 v1, 15, v2
286 ; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2
287 ; SI-NEXT: s_waitcnt vmcnt(0)
288 ; SI-NEXT: v_lshrrev_b32_e32 v1, v1, v0
289 ; SI-NEXT: v_and_b32_e32 v2, 15, v2
290 ; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
291 ; SI-NEXT: v_or_b32_e32 v0, v1, v0
292 ; SI-NEXT: buffer_store_short v0, v[4:5], s[4:7], 0 addr64 offset:8
293 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
294 ; SI-NEXT: s_setpc_b64 s[30:31]
295 ;
296 ; GFX8-LABEL: test_rotr_i16:
297 ; GFX8: ; %bb.0: ; %entry
298 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
299 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 32, v0
300 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
301 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 48, v2
302 ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
303 ; GFX8-NEXT: flat_load_ushort v2, v[2:3]
304 ; GFX8-NEXT: flat_load_ushort v0, v[0:1]
305 ; GFX8-NEXT: s_waitcnt vmcnt(0)
306 ; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v0
307 ; GFX8-NEXT: v_sub_u16_e32 v2, 0, v2
308 ; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
309 ; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
310 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
311 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
312 ; GFX8-NEXT: flat_store_short v[0:1], v2
313 ; GFX8-NEXT: s_waitcnt vmcnt(0)
314 ; GFX8-NEXT: s_setpc_b64 s[30:31]
315 ;
316 ; GFX10-LABEL: test_rotr_i16:
317 ; GFX10: ; %bb.0: ; %entry
318 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
319 ; GFX10-NEXT: global_load_ushort v6, v[2:3], off offset:48
320 ; GFX10-NEXT: global_load_ushort v7, v[0:1], off offset:32
321 ; GFX10-NEXT: s_waitcnt vmcnt(1)
322 ; GFX10-NEXT: v_sub_nc_u16 v0, 0, v6
323 ; GFX10-NEXT: s_waitcnt vmcnt(0)
324 ; GFX10-NEXT: v_lshrrev_b16 v1, v6, v7
325 ; GFX10-NEXT: v_lshlrev_b16 v0, v0, v7
326 ; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
327 ; GFX10-NEXT: global_store_short v[4:5], v0, off offset:8
328 ; GFX10-NEXT: s_setpc_b64 s[30:31]
329 ;
330 ; GFX11-LABEL: test_rotr_i16:
331 ; GFX11: ; %bb.0: ; %entry
332 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
333 ; GFX11-NEXT: global_load_u16 v2, v[2:3], off offset:48
334 ; GFX11-NEXT: global_load_u16 v0, v[0:1], off offset:32
335 ; GFX11-NEXT: s_waitcnt vmcnt(1)
336 ; GFX11-NEXT: v_sub_nc_u16 v1, 0, v2
337 ; GFX11-NEXT: s_waitcnt vmcnt(0)
338 ; GFX11-NEXT: v_lshrrev_b16 v2, v2, v0
339 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
340 ; GFX11-NEXT: v_lshlrev_b16 v0, v1, v0
341 ; GFX11-NEXT: v_or_b32_e32 v0, v2, v0
342 ; GFX11-NEXT: global_store_b16 v[4:5], v0, off offset:8
343 ; GFX11-NEXT: s_setpc_b64 s[30:31]
344 entry:
345 %arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16
346 %a = load i16, ptr addrspace(1) %arrayidx
347 %arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %sourceB, i64 24
348 %b = load i16, ptr addrspace(1) %arrayidx2
349 %c = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)
350 %arrayidx5 = getelementptr inbounds i16, ptr addrspace(1) %destValues, i64 4
351 store i16 %c, ptr addrspace(1) %arrayidx5
352 ret void
353 }