[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
[llvm-project.git] / llvm / test / CodeGen / AMDGPU / shrink-true16.mir
blob245c5e1005d08f063ebaf17811a13632412b5e6c
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
3 # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1100 %s
5 ---
6 name: 16bit_lo128_shrink
7 tracksRegLiveness: true
8 body: |
9   bb.0:
10     liveins: $vgpr127
11     ; GFX1100-LABEL: name: 16bit_lo128_shrink
12     ; GFX1100: liveins: $vgpr127
13     ; GFX1100-NEXT: {{  $}}
14     ; GFX1100-NEXT: V_CMP_EQ_U16_fake16_e32 0, $vgpr127, implicit-def $vcc_lo, implicit $exec, implicit $exec
15     $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr127, implicit-def $vcc, implicit $exec
16 ...
18 ---
19 name: 16bit_lo128_no_shrink
20 tracksRegLiveness: true
21 body: |
22   bb.0:
23     liveins: $vgpr128
24     ; GFX1100-LABEL: name: 16bit_lo128_no_shrink
25     ; GFX1100: liveins: $vgpr128
26     ; GFX1100-NEXT: {{  $}}
27     ; GFX1100-NEXT: $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr128, implicit-def $vcc_lo, implicit $exec
28     $vcc_lo = V_CMP_EQ_U16_fake16_e64 0, $vgpr128, implicit-def $vcc, implicit $exec
29 ...