| blob | db7d816386a70de372d43a710b4b3cb8a2524944 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
5 define amdgpu_kernel void @s_test_udiv_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
6 ; GCN-LABEL: s_test_udiv_i64:
7 ; GCN: ; %bb.0:
8 ; GCN-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
10 ; GCN-NEXT: s_mov_b32 s7, 0xf000
11 ; GCN-NEXT: s_mov_b32 s6, -1
12 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
13 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
14 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
15 ; GCN-NEXT: s_sub_u32 s4, 0, s8
16 ; GCN-NEXT: s_subb_u32 s5, 0, s9
17 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
18 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
19 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
20 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
21 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
22 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
23 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
24 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
25 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
26 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
27 ; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
28 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
29 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
30 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
31 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
32 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
33 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v2
34 ; GCN-NEXT: v_mul_hi_u32 v6, v1, v4
35 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
36 ; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
37 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
38 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
39 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
40 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
41 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc
42 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
43 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
44 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
45 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
46 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
47 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
48 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
49 ; GCN-NEXT: v_mul_lo_u32 v4, s5, v0
50 ; GCN-NEXT: s_mov_b32 s5, s1
51 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
52 ; GCN-NEXT: v_mul_lo_u32 v3, s4, v0
53 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
54 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
55 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3
56 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
57 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
58 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
59 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v2
60 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
61 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
62 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
63 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
64 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
65 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
66 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
67 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
68 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
69 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
70 ; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
71 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
72 ; GCN-NEXT: v_mul_hi_u32 v4, s2, v1
73 ; GCN-NEXT: v_mul_hi_u32 v5, s3, v1
74 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v1
75 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
76 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
77 ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
78 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
79 ; GCN-NEXT: s_mov_b32 s4, s0
80 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
81 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
82 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
83 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
84 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
85 ; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
86 ; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
87 ; GCN-NEXT: v_mul_lo_u32 v4, s9, v0
88 ; GCN-NEXT: v_mov_b32_e32 v5, s9
89 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
90 ; GCN-NEXT: v_mul_lo_u32 v3, s8, v0
91 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
92 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
93 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
94 ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
95 ; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v3
96 ; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
97 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
98 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
99 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v5
100 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
101 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
102 ; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
103 ; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 1, v0
104 ; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
105 ; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0
106 ; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
107 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
108 ; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1]
109 ; GCN-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1]
110 ; GCN-NEXT: v_mov_b32_e32 v6, s3
111 ; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
112 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
113 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
114 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
115 ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
116 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2
117 ; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
118 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
119 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
120 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
121 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
122 ; GCN-NEXT: s_endpgm
123 ;
124 ; GCN-IR-LABEL: s_test_udiv_i64:
125 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
126 ; GCN-IR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
127 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
128 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
129 ; GCN-IR-NEXT: s_mov_b32 s11, 0
130 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
131 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
132 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
133 ; GCN-IR-NEXT: s_flbit_i32_b64 s10, s[6:7]
134 ; GCN-IR-NEXT: s_flbit_i32_b64 s16, s[2:3]
135 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
136 ; GCN-IR-NEXT: s_sub_u32 s12, s10, s16
137 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
138 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
139 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63
140 ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
141 ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
142 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
143 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
144 ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
145 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
146 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
147 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
148 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
149 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
150 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
151 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
152 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
153 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12
154 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
155 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
156 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s14
157 ; GCN-IR-NEXT: s_add_u32 s14, s6, -1
158 ; GCN-IR-NEXT: s_addc_u32 s15, s7, -1
159 ; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11]
160 ; GCN-IR-NEXT: s_add_u32 s2, s2, s16
161 ; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
162 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
163 ; GCN-IR-NEXT: s_mov_b32 s5, 0
164 ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
165 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
166 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
167 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
168 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
169 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
170 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
171 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s12
172 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s13
173 ; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
174 ; GCN-IR-NEXT: s_mov_b32 s11, s10
175 ; GCN-IR-NEXT: s_and_b32 s4, s10, 1
176 ; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[6:7]
177 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s10
178 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s11
179 ; GCN-IR-NEXT: s_add_u32 s2, s2, 1
180 ; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
181 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[2:3], 0
182 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
183 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
184 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
185 ; GCN-IR-NEXT: .LBB0_4: ; %Flow7
186 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
187 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[2:3]
188 ; GCN-IR-NEXT: .LBB0_5: ; %udiv-end
189 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
190 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
191 ; GCN-IR-NEXT: s_mov_b32 s2, -1
192 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
193 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
194 ; GCN-IR-NEXT: s_endpgm
195 %result = udiv i64 %x, %y
196 store i64 %result, ptr addrspace(1) %out
197 ret void
198 }
200 define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
201 ; GCN-LABEL: v_test_udiv_i64:
202 ; GCN: ; %bb.0:
203 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
204 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
205 ; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
206 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
207 ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
208 ; GCN-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4
209 ; GCN-NEXT: v_rcp_f32_e32 v4, v4
210 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
211 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
212 ; GCN-NEXT: v_trunc_f32_e32 v5, v5
213 ; GCN-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4
214 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
215 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
216 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
217 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
218 ; GCN-NEXT: v_mul_lo_u32 v10, v7, v4
219 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
220 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v4
221 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
222 ; GCN-NEXT: v_mul_lo_u32 v10, v4, v8
223 ; GCN-NEXT: v_mul_hi_u32 v11, v4, v9
224 ; GCN-NEXT: v_mul_hi_u32 v12, v4, v8
225 ; GCN-NEXT: v_mul_hi_u32 v13, v5, v8
226 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
227 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
228 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
229 ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
230 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
231 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12
232 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
233 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v13, vcc
234 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
235 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
236 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
237 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
238 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
239 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
240 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
241 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
242 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
243 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
244 ; GCN-NEXT: v_mul_lo_u32 v10, v4, v7
245 ; GCN-NEXT: v_mul_hi_u32 v11, v4, v6
246 ; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
247 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v6
248 ; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
249 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
250 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
251 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
252 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
253 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
254 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
255 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
256 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
257 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
258 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
259 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
260 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
261 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v4
262 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
263 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v5
264 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
265 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
266 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
267 ; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
268 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
269 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
270 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc
271 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
272 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
273 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
274 ; GCN-NEXT: v_mul_lo_u32 v6, v2, v5
275 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v4
276 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v4
277 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
278 ; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
279 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
280 ; GCN-NEXT: v_sub_i32_e32 v8, vcc, v1, v6
281 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
282 ; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
283 ; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2
284 ; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
285 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3
286 ; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
287 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
288 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
289 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3
290 ; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5]
291 ; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v4
292 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
293 ; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
294 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
295 ; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v4
296 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
297 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
298 ; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
299 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
300 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
301 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
302 ; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
303 ; GCN-NEXT: v_cndmask_b32_e64 v7, v10, v8, s[4:5]
304 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
305 ; GCN-NEXT: v_cndmask_b32_e64 v1, v11, v9, s[4:5]
306 ; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
307 ; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
308 ; GCN-NEXT: s_setpc_b64 s[30:31]
309 ;
310 ; GCN-IR-LABEL: v_test_udiv_i64:
311 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
312 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
313 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
314 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
315 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
316 ; GCN-IR-NEXT: v_min_u32_e32 v10, v4, v5
317 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
318 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
319 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
320 ; GCN-IR-NEXT: v_min_u32_e32 v11, v4, v5
321 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[6:7], v10, v11
322 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
323 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
324 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, s[6:7]
325 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[6:7]
326 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
327 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
328 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7]
329 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
330 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5]
331 ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
332 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
333 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
334 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
335 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
336 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v6
337 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc
338 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6
339 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
340 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
341 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
342 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
343 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
344 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
345 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
346 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
347 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2
348 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v8
349 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc
350 ; GCN-IR-NEXT: v_not_b32_e32 v0, v10
351 ; GCN-IR-NEXT: v_not_b32_e32 v1, 0
352 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v11
353 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
354 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
355 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
356 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
357 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
358 ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
359 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
360 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
361 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
362 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v6
363 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
364 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v12, v8
365 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v13, v9, vcc
366 ; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4
367 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6
368 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
369 ; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5
370 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10
371 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v3
372 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v2
373 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
374 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
375 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
376 ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
377 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
378 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
379 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
380 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
381 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
382 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
383 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
384 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
385 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
386 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
387 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
388 ; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0
389 ; GCN-IR-NEXT: .LBB1_6: ; %Flow5
390 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
391 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v5
392 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v4
393 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
394 %result = udiv i64 %x, %y
395 ret i64 %result
396 }
398 define amdgpu_kernel void @s_test_udiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
399 ; GCN-LABEL: s_test_udiv24_64:
400 ; GCN: ; %bb.0:
401 ; GCN-NEXT: s_load_dword s6, s[4:5], 0xe
402 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
403 ; GCN-NEXT: s_mov_b32 s7, 0xf000
404 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
405 ; GCN-NEXT: s_lshr_b32 s2, s6, 8
406 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
407 ; GCN-NEXT: s_lshr_b32 s2, s3, 8
408 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
409 ; GCN-NEXT: s_mov_b32 s6, -1
410 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
411 ; GCN-NEXT: s_mov_b32 s4, s0
412 ; GCN-NEXT: s_mov_b32 s5, s1
413 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
414 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
415 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
416 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
417 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
418 ; GCN-NEXT: v_mov_b32_e32 v1, 0
419 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
420 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
421 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
422 ; GCN-NEXT: s_endpgm
423 ;
424 ; GCN-IR-LABEL: s_test_udiv24_64:
425 ; GCN-IR: ; %bb.0:
426 ; GCN-IR-NEXT: s_load_dword s6, s[4:5], 0xe
427 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
428 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
429 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
430 ; GCN-IR-NEXT: s_lshr_b32 s2, s6, 8
431 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
432 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
433 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
434 ; GCN-IR-NEXT: s_mov_b32 s6, -1
435 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
436 ; GCN-IR-NEXT: s_mov_b32 s4, s0
437 ; GCN-IR-NEXT: s_mov_b32 s5, s1
438 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
439 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
440 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
441 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
442 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
443 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
444 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
445 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
446 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
447 ; GCN-IR-NEXT: s_endpgm
448 %1 = lshr i64 %x, 40
449 %2 = lshr i64 %y, 40
450 %result = udiv i64 %1, %2
451 store i64 %result, ptr addrspace(1) %out
452 ret void
453 }
455 define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
456 ; GCN-LABEL: v_test_udiv24_i64:
457 ; GCN: ; %bb.0:
458 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
459 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3
460 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
461 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1
462 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v1
463 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
464 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
465 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
466 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
467 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
468 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
469 ; GCN-NEXT: v_mov_b32_e32 v1, 0
470 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
471 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
472 ; GCN-NEXT: s_setpc_b64 s[30:31]
473 ;
474 ; GCN-IR-LABEL: v_test_udiv24_i64:
475 ; GCN-IR: ; %bb.0:
476 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
477 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3
478 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
479 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1
480 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v1
481 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
482 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
483 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
484 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
485 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
486 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
487 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
488 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
489 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
490 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
491 %1 = lshr i64 %x, 40
492 %2 = lshr i64 %y, 40
493 %result = udiv i64 %1, %2
494 ret i64 %result
495 }
497 define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
498 ; GCN-LABEL: s_test_udiv32_i64:
499 ; GCN: ; %bb.0:
500 ; GCN-NEXT: s_load_dword s8, s[4:5], 0xe
501 ; GCN-NEXT: s_mov_b32 s7, 0xf000
502 ; GCN-NEXT: s_mov_b32 s6, -1
503 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
504 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
505 ; GCN-NEXT: s_sub_i32 s0, 0, s8
506 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
507 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
508 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
509 ; GCN-NEXT: v_mul_lo_u32 v1, s0, v0
510 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
511 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
512 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
513 ; GCN-NEXT: s_mov_b32 s4, s0
514 ; GCN-NEXT: s_mov_b32 s5, s1
515 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
516 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
517 ; GCN-NEXT: v_readfirstlane_b32 s0, v0
518 ; GCN-NEXT: s_mul_i32 s0, s0, s8
519 ; GCN-NEXT: s_sub_i32 s0, s3, s0
520 ; GCN-NEXT: s_sub_i32 s1, s0, s8
521 ; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
522 ; GCN-NEXT: s_cmp_ge_u32 s0, s8
523 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
524 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
525 ; GCN-NEXT: s_cselect_b32 s0, s1, s0
526 ; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
527 ; GCN-NEXT: s_cmp_ge_u32 s0, s8
528 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
529 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
530 ; GCN-NEXT: v_mov_b32_e32 v1, 0
531 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
532 ; GCN-NEXT: s_endpgm
533 ;
534 ; GCN-IR-LABEL: s_test_udiv32_i64:
535 ; GCN-IR: ; %bb.0:
536 ; GCN-IR-NEXT: s_load_dword s8, s[4:5], 0xe
537 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
538 ; GCN-IR-NEXT: s_mov_b32 s6, -1
539 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
540 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
541 ; GCN-IR-NEXT: s_sub_i32 s0, 0, s8
542 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
543 ; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
544 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
545 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v0
546 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
547 ; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
548 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
549 ; GCN-IR-NEXT: s_mov_b32 s4, s0
550 ; GCN-IR-NEXT: s_mov_b32 s5, s1
551 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
552 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0
553 ; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0
554 ; GCN-IR-NEXT: s_mul_i32 s0, s0, s8
555 ; GCN-IR-NEXT: s_sub_i32 s0, s3, s0
556 ; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
557 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
558 ; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
559 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
560 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
561 ; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
562 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
563 ; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
564 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
565 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
566 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
567 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
568 ; GCN-IR-NEXT: s_endpgm
569 %1 = lshr i64 %x, 32
570 %2 = lshr i64 %y, 32
571 %result = udiv i64 %1, %2
572 store i64 %result, ptr addrspace(1) %out
573 ret void
574 }
576 define amdgpu_kernel void @s_test_udiv31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
577 ; GCN-LABEL: s_test_udiv31_i64:
578 ; GCN: ; %bb.0:
579 ; GCN-NEXT: s_load_dword s0, s[4:5], 0xe
580 ; GCN-NEXT: s_mov_b32 s7, 0xf000
581 ; GCN-NEXT: s_mov_b32 s6, -1
582 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
583 ; GCN-NEXT: s_lshr_b32 s8, s0, 1
584 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
585 ; GCN-NEXT: s_sub_i32 s0, 0, s8
586 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
587 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
588 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
589 ; GCN-NEXT: v_mul_lo_u32 v1, s0, v0
590 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
591 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
592 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
593 ; GCN-NEXT: s_lshr_b32 s2, s3, 1
594 ; GCN-NEXT: s_mov_b32 s4, s0
595 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
596 ; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
597 ; GCN-NEXT: s_mov_b32 s5, s1
598 ; GCN-NEXT: v_readfirstlane_b32 s0, v0
599 ; GCN-NEXT: s_mul_i32 s0, s0, s8
600 ; GCN-NEXT: s_sub_i32 s0, s2, s0
601 ; GCN-NEXT: s_sub_i32 s1, s0, s8
602 ; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
603 ; GCN-NEXT: s_cmp_ge_u32 s0, s8
604 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
605 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
606 ; GCN-NEXT: s_cselect_b32 s0, s1, s0
607 ; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0
608 ; GCN-NEXT: s_cmp_ge_u32 s0, s8
609 ; GCN-NEXT: s_cselect_b64 vcc, -1, 0
610 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
611 ; GCN-NEXT: v_mov_b32_e32 v1, 0
612 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
613 ; GCN-NEXT: s_endpgm
614 ;
615 ; GCN-IR-LABEL: s_test_udiv31_i64:
616 ; GCN-IR: ; %bb.0:
617 ; GCN-IR-NEXT: s_load_dword s0, s[4:5], 0xe
618 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
619 ; GCN-IR-NEXT: s_mov_b32 s6, -1
620 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
621 ; GCN-IR-NEXT: s_lshr_b32 s8, s0, 1
622 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
623 ; GCN-IR-NEXT: s_sub_i32 s0, 0, s8
624 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
625 ; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
626 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
627 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v0
628 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
629 ; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
630 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
631 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1
632 ; GCN-IR-NEXT: s_mov_b32 s4, s0
633 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
634 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
635 ; GCN-IR-NEXT: s_mov_b32 s5, s1
636 ; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0
637 ; GCN-IR-NEXT: s_mul_i32 s0, s0, s8
638 ; GCN-IR-NEXT: s_sub_i32 s0, s2, s0
639 ; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
640 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
641 ; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
642 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
643 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
644 ; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
645 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0
646 ; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
647 ; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0
648 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
649 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
650 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
651 ; GCN-IR-NEXT: s_endpgm
652 %1 = lshr i64 %x, 33
653 %2 = lshr i64 %y, 33
654 %result = udiv i64 %1, %2
655 store i64 %result, ptr addrspace(1) %out
656 ret void
657 }
659 define amdgpu_kernel void @s_test_udiv23_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
660 ; GCN-LABEL: s_test_udiv23_i64:
661 ; GCN: ; %bb.0:
662 ; GCN-NEXT: s_load_dword s6, s[4:5], 0xe
663 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
664 ; GCN-NEXT: s_mov_b32 s7, 0xf000
665 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
666 ; GCN-NEXT: s_lshr_b32 s2, s6, 9
667 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
668 ; GCN-NEXT: s_lshr_b32 s2, s3, 9
669 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
670 ; GCN-NEXT: s_mov_b32 s6, -1
671 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
672 ; GCN-NEXT: s_mov_b32 s4, s0
673 ; GCN-NEXT: s_mov_b32 s5, s1
674 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
675 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
676 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
677 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
678 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
679 ; GCN-NEXT: v_mov_b32_e32 v1, 0
680 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
681 ; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
682 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
683 ; GCN-NEXT: s_endpgm
684 ;
685 ; GCN-IR-LABEL: s_test_udiv23_i64:
686 ; GCN-IR: ; %bb.0:
687 ; GCN-IR-NEXT: s_load_dword s6, s[4:5], 0xe
688 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
689 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
690 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
691 ; GCN-IR-NEXT: s_lshr_b32 s2, s6, 9
692 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
693 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 9
694 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
695 ; GCN-IR-NEXT: s_mov_b32 s6, -1
696 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
697 ; GCN-IR-NEXT: s_mov_b32 s4, s0
698 ; GCN-IR-NEXT: s_mov_b32 s5, s1
699 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
700 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
701 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
702 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
703 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
704 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
705 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
706 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
707 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
708 ; GCN-IR-NEXT: s_endpgm
709 %1 = lshr i64 %x, 41
710 %2 = lshr i64 %y, 41
711 %result = udiv i64 %1, %2
712 store i64 %result, ptr addrspace(1) %out
713 ret void
714 }
716 define amdgpu_kernel void @s_test_udiv24_i48(ptr addrspace(1) %out, i48 %x, i48 %y) {
717 ; GCN-LABEL: s_test_udiv24_i48:
718 ; GCN: ; %bb.0:
719 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
720 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
721 ; GCN-NEXT: s_mov_b32 s7, 0xf000
722 ; GCN-NEXT: s_mov_b32 s6, -1
723 ; GCN-NEXT: v_mov_b32_e32 v3, 0
724 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
725 ; GCN-NEXT: s_and_b32 s2, s2, 0xff000000
726 ; GCN-NEXT: s_and_b32 s4, s4, 0xff000000
727 ; GCN-NEXT: s_and_b32 s5, s5, 0xffff
728 ; GCN-NEXT: v_mov_b32_e32 v0, s4
729 ; GCN-NEXT: v_alignbit_b32 v0, s5, v0, 24
730 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
731 ; GCN-NEXT: s_and_b32 s3, s3, 0xffff
732 ; GCN-NEXT: v_mov_b32_e32 v1, s2
733 ; GCN-NEXT: v_alignbit_b32 v1, s3, v1, 24
734 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v1
735 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
736 ; GCN-NEXT: s_mov_b32 s4, s0
737 ; GCN-NEXT: s_mov_b32 s5, s1
738 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
739 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
740 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
741 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
742 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
743 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
744 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
745 ; GCN-NEXT: buffer_store_short v3, off, s[4:7], 0 offset:4
746 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
747 ; GCN-NEXT: s_endpgm
748 ;
749 ; GCN-IR-LABEL: s_test_udiv24_i48:
750 ; GCN-IR: ; %bb.0:
751 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
752 ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
753 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
754 ; GCN-IR-NEXT: s_mov_b32 s6, -1
755 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
756 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
757 ; GCN-IR-NEXT: s_and_b32 s2, s2, 0xff000000
758 ; GCN-IR-NEXT: s_and_b32 s4, s4, 0xff000000
759 ; GCN-IR-NEXT: s_and_b32 s5, s5, 0xffff
760 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
761 ; GCN-IR-NEXT: v_alignbit_b32 v0, s5, v0, 24
762 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
763 ; GCN-IR-NEXT: s_and_b32 s3, s3, 0xffff
764 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s2
765 ; GCN-IR-NEXT: v_alignbit_b32 v1, s3, v1, 24
766 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v1
767 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
768 ; GCN-IR-NEXT: s_mov_b32 s4, s0
769 ; GCN-IR-NEXT: s_mov_b32 s5, s1
770 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
771 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
772 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
773 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2
774 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
775 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
776 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
777 ; GCN-IR-NEXT: buffer_store_short v3, off, s[4:7], 0 offset:4
778 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
779 ; GCN-IR-NEXT: s_endpgm
780 %1 = lshr i48 %x, 24
781 %2 = lshr i48 %y, 24
782 %result = udiv i48 %1, %2
783 store i48 %result, ptr addrspace(1) %out
784 ret void
785 }
787 define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) {
788 ; GCN-LABEL: s_test_udiv_k_num_i64:
789 ; GCN: ; %bb.0:
790 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
791 ; GCN-NEXT: s_mov_b32 s7, 0xf000
792 ; GCN-NEXT: s_mov_b32 s6, -1
793 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
794 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
795 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
796 ; GCN-NEXT: s_sub_u32 s4, 0, s2
797 ; GCN-NEXT: s_subb_u32 s5, 0, s3
798 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
799 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
800 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
801 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
802 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
803 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
804 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
805 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
806 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
807 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
808 ; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
809 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
810 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
811 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
812 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
813 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
814 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v2
815 ; GCN-NEXT: v_mul_hi_u32 v6, v1, v4
816 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
817 ; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
818 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
819 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
820 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
821 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
822 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc
823 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
824 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
825 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
826 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
827 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
828 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
829 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
830 ; GCN-NEXT: v_mul_lo_u32 v4, s5, v0
831 ; GCN-NEXT: s_mov_b32 s5, s1
832 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
833 ; GCN-NEXT: v_mul_lo_u32 v3, s4, v0
834 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
835 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
836 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3
837 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
838 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
839 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
840 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v2
841 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
842 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
843 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
844 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
845 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
846 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
847 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
848 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
849 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
850 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
851 ; GCN-NEXT: v_mul_lo_u32 v2, v1, 24
852 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
853 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
854 ; GCN-NEXT: v_mov_b32_e32 v4, s3
855 ; GCN-NEXT: s_mov_b32 s4, s0
856 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
857 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc
858 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
859 ; GCN-NEXT: v_mul_hi_u32 v2, s2, v0
860 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2
861 ; GCN-NEXT: v_mul_lo_u32 v2, s2, v0
862 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
863 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2
864 ; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
865 ; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2
866 ; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
867 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3
868 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
869 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4
870 ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
871 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3
872 ; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1]
873 ; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 1, v0
874 ; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
875 ; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 2, v0
876 ; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
877 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
878 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
879 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
880 ; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[0:1]
881 ; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1]
882 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
883 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
884 ; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
885 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
886 ; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
887 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
888 ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
889 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
890 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
891 ; GCN-NEXT: s_endpgm
892 ;
893 ; GCN-IR-LABEL: s_test_udiv_k_num_i64:
894 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
895 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
896 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
897 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
898 ; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[2:3]
899 ; GCN-IR-NEXT: s_add_u32 s8, s12, 0xffffffc5
900 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
901 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
902 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[8:9], 63
903 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 63
904 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
905 ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
906 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24
907 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
908 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
909 ; GCN-IR-NEXT: s_mov_b32 s7, 0
910 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5
911 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
912 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
913 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
914 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
915 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
916 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
917 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s8
918 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
919 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
920 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10
921 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
922 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
923 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s12
924 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
925 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
926 ; GCN-IR-NEXT: s_mov_b32 s5, 0
927 ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
928 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
929 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
930 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
931 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
932 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
933 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
934 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s10
935 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s11
936 ; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31
937 ; GCN-IR-NEXT: s_mov_b32 s13, s12
938 ; GCN-IR-NEXT: s_and_b32 s4, s12, 1
939 ; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], s[2:3]
940 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s12
941 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s13
942 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
943 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
944 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
945 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5]
946 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
947 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3
948 ; GCN-IR-NEXT: .LBB8_4: ; %Flow6
949 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
950 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3]
951 ; GCN-IR-NEXT: .LBB8_5: ; %udiv-end
952 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
953 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
954 ; GCN-IR-NEXT: s_mov_b32 s2, -1
955 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
956 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
957 ; GCN-IR-NEXT: s_endpgm
958 %result = udiv i64 24, %x
959 store i64 %result, ptr addrspace(1) %out
960 ret void
961 }
963 ; define i64 @v_test_udiv_k_num_i64(i64 %x) {
964 ; %result = udiv i64 24, %x
965 ; ret i64 %result
966 ; }
968 define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
969 ; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
970 ; GCN: ; %bb.0:
971 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
972 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
973 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
974 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
975 ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
976 ; GCN-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v2
977 ; GCN-NEXT: v_rcp_f32_e32 v2, v2
978 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
979 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
980 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
981 ; GCN-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2
982 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
983 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
984 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
985 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
986 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v2
987 ; GCN-NEXT: v_mul_lo_u32 v9, v4, v2
988 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
989 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
990 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v9
991 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v6
992 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v6
993 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v6
994 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
995 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
996 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v10, vcc
997 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v9
998 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v9
999 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
1000 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v9, vcc
1001 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v11, vcc
1002 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1003 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
1004 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
1005 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
1006 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
1007 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
1008 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
1009 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
1010 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1011 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
1012 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
1013 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
1014 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
1015 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
1016 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
1017 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
1018 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
1019 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
1020 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
1021 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
1022 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
1023 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
1024 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
1025 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
1026 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
1027 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc
1028 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
1029 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
1030 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
1031 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
1032 ; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
1033 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v3
1034 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0x8000, v4
1035 ; GCN-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
1036 ; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v0
1037 ; GCN-NEXT: v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
1038 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v1
1039 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1040 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v0
1041 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
1042 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1
1043 ; GCN-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[4:5]
1044 ; GCN-NEXT: v_add_i32_e64 v6, s[4:5], 2, v2
1045 ; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
1046 ; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 1, v2
1047 ; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
1048 ; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
1049 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
1050 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
1051 ; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v6, s[4:5]
1052 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
1053 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
1054 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
1055 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1
1056 ; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
1057 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
1058 ; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1059 ; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
1060 ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1061 ; GCN-NEXT: s_setpc_b64 s[30:31]
1062 ;
1063 ; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
1064 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1065 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1066 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1067 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
1068 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1069 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
1070 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffd0, v10
1071 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
1072 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1073 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5]
1074 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5]
1075 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0x8000
1076 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1077 ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5]
1078 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1079 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
1080 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
1081 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1082 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
1083 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1084 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4
1085 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
1086 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
1087 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
1088 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1089 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2
1090 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1091 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1092 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc
1093 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
1094 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
1095 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1096 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
1097 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
1098 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6
1099 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10
1100 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
1101 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
1102 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1103 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
1104 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1105 ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
1106 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1107 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
1108 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1109 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
1110 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1111 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
1112 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
1113 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
1114 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
1115 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
1116 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
1117 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
1118 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
1119 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
1120 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1121 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1122 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
1123 ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1124 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
1125 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1126 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
1127 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1128 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
1129 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1130 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1131 ; GCN-IR-NEXT: .LBB9_5: ; %Flow4
1132 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1133 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
1134 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
1135 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
1136 ; GCN-IR-NEXT: .LBB9_6: ; %Flow5
1137 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1138 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
1139 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
1140 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1141 %result = udiv i64 32768, %x
1142 ret i64 %result
1143 }
1145 define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
1146 ; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
1147 ; GCN: ; %bb.0:
1148 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1149 ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 15
1150 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 15, v1
1151 ; GCN-NEXT: s_setpc_b64 s[30:31]
1152 ;
1153 ; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
1154 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1155 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1156 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1157 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
1158 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1159 ; GCN-IR-NEXT: v_min_u32_e32 v8, v2, v3
1160 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v8
1161 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1162 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1163 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1164 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1165 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1166 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
1167 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1168 ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1169 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
1170 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1171 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_6
1172 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1173 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4
1174 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
1175 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
1176 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1177 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
1178 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1179 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1180 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1181 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1182 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_5
1183 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1184 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6
1185 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v8
1186 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
1187 ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1188 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1189 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1190 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
1191 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1192 ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
1193 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1194 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
1195 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1196 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
1197 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6
1198 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1199 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v7, vcc
1200 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
1201 ; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
1202 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
1203 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1204 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v8
1205 ; GCN-IR-NEXT: v_and_b32_e32 v8, 0x8000, v8
1206 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1207 ; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
1208 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v6, v8
1209 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
1210 ; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1211 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1212 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
1213 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1214 ; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3
1215 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1216 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1217 ; GCN-IR-NEXT: .LBB10_5: ; %Flow4
1218 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1219 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
1220 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
1221 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
1222 ; GCN-IR-NEXT: .LBB10_6: ; %Flow5
1223 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1224 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
1225 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
1226 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1227 %result = udiv i64 %x, 32768
1228 ret i64 %result
1229 }
1231 define amdgpu_kernel void @s_test_udiv_k_den_i64(ptr addrspace(1) %out, i64 %x) {
1232 ; GCN-LABEL: s_test_udiv_k_den_i64:
1233 ; GCN: ; %bb.0:
1234 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1235 ; GCN-NEXT: v_mov_b32_e32 v2, 0xaaaaaaab
1236 ; GCN-NEXT: v_mov_b32_e32 v0, 0xaaaaaaaa
1237 ; GCN-NEXT: s_mov_b32 s7, 0xf000
1238 ; GCN-NEXT: s_mov_b32 s6, -1
1239 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1240 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v2
1241 ; GCN-NEXT: v_mul_hi_u32 v2, s3, v2
1242 ; GCN-NEXT: s_mov_b32 s4, s0
1243 ; GCN-NEXT: v_mul_hi_u32 v1, s2, v0
1244 ; GCN-NEXT: s_mul_i32 s0, s2, 0xaaaaaaaa
1245 ; GCN-NEXT: s_mul_i32 s2, s3, 0xaaaaaaab
1246 ; GCN-NEXT: v_add_i32_e32 v3, vcc, s2, v3
1247 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
1248 ; GCN-NEXT: v_add_i32_e32 v3, vcc, s0, v3
1249 ; GCN-NEXT: v_mul_hi_u32 v3, s3, v0
1250 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1251 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1252 ; GCN-NEXT: s_mul_i32 s0, s3, 0xaaaaaaaa
1253 ; GCN-NEXT: v_addc_u32_e64 v2, s[8:9], 0, 0, vcc
1254 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v1
1255 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v2, vcc
1256 ; GCN-NEXT: v_lshr_b64 v[0:1], v[0:1], 4
1257 ; GCN-NEXT: s_mov_b32 s5, s1
1258 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1259 ; GCN-NEXT: s_endpgm
1260 ;
1261 ; GCN-IR-LABEL: s_test_udiv_k_den_i64:
1262 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1263 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1264 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1265 ; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[2:3]
1266 ; GCN-IR-NEXT: s_sub_u32 s8, 59, s12
1267 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
1268 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
1269 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[8:9], 63
1270 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 63
1271 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
1272 ; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec
1273 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3
1274 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2
1275 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
1276 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5]
1277 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
1278 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_5
1279 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1280 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
1281 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
1282 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
1283 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
1284 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
1285 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s8
1286 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4
1287 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1288 ; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[2:3], s10
1289 ; GCN-IR-NEXT: s_add_u32 s2, s12, 0xffffffc4
1290 ; GCN-IR-NEXT: s_addc_u32 s3, 0, -1
1291 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1292 ; GCN-IR-NEXT: s_mov_b32 s5, 0
1293 ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
1294 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1295 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
1296 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
1297 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
1298 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[4:5]
1299 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
1300 ; GCN-IR-NEXT: s_sub_u32 s4, 23, s8
1301 ; GCN-IR-NEXT: s_subb_u32 s4, 0, s9
1302 ; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
1303 ; GCN-IR-NEXT: s_and_b32 s4, s10, 1
1304 ; GCN-IR-NEXT: s_and_b32 s10, s10, 24
1305 ; GCN-IR-NEXT: s_sub_u32 s8, s8, s10
1306 ; GCN-IR-NEXT: s_subb_u32 s9, s9, 0
1307 ; GCN-IR-NEXT: s_add_u32 s2, s2, 1
1308 ; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
1309 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
1310 ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
1311 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
1312 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_3
1313 ; GCN-IR-NEXT: .LBB11_4: ; %Flow6
1314 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
1315 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3]
1316 ; GCN-IR-NEXT: .LBB11_5: ; %udiv-end
1317 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
1318 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
1319 ; GCN-IR-NEXT: s_mov_b32 s2, -1
1320 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
1321 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1322 ; GCN-IR-NEXT: s_endpgm
1323 %result = udiv i64 %x, 24
1324 store i64 %result, ptr addrspace(1) %out
1325 ret void
1326 }
1328 define i64 @v_test_udiv_k_den_i64(i64 %x) {
1329 ; GCN-LABEL: v_test_udiv_k_den_i64:
1330 ; GCN: ; %bb.0:
1331 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1332 ; GCN-NEXT: s_mov_b32 s4, 0xaaaaaaab
1333 ; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
1334 ; GCN-NEXT: v_mul_hi_u32 v4, v0, s4
1335 ; GCN-NEXT: s_mov_b32 s6, 0xaaaaaaaa
1336 ; GCN-NEXT: v_mul_hi_u32 v5, v1, s4
1337 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s6
1338 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s6
1339 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
1340 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
1341 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
1342 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1343 ; GCN-NEXT: v_mul_lo_u32 v2, v1, s6
1344 ; GCN-NEXT: v_mul_hi_u32 v1, v1, s6
1345 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v4, v0
1346 ; GCN-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
1347 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
1348 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
1349 ; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 4
1350 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 4, v1
1351 ; GCN-NEXT: s_setpc_b64 s[30:31]
1352 ;
1353 ; GCN-IR-LABEL: v_test_udiv_k_den_i64:
1354 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1355 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1356 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1357 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
1358 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1359 ; GCN-IR-NEXT: v_min_u32_e32 v8, v2, v3
1360 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v8
1361 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
1362 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1363 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
1364 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1365 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
1366 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
1367 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
1368 ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
1369 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
1370 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1371 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
1372 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1373 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4
1374 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
1375 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
1376 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1377 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
1378 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1379 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1380 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1381 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1382 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
1383 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1384 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6
1385 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v8
1386 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
1387 ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
1388 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1389 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
1390 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1391 ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
1392 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1393 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
1394 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1395 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
1396 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6
1397 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1398 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v7, vcc
1399 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
1400 ; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
1401 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
1402 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1403 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v8
1404 ; GCN-IR-NEXT: v_and_b32_e32 v8, 24, v8
1405 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1406 ; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
1407 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v6, v8
1408 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
1409 ; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1410 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1411 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
1412 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1413 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
1414 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1415 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1416 ; GCN-IR-NEXT: .LBB12_5: ; %Flow4
1417 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1418 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
1419 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
1420 ; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
1421 ; GCN-IR-NEXT: .LBB12_6: ; %Flow5
1422 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1423 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
1424 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
1425 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1426 %result = udiv i64 %x, 24
1427 ret i64 %result
1428 }
1430 define amdgpu_kernel void @s_test_udiv24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
1431 ; GCN-LABEL: s_test_udiv24_k_num_i64:
1432 ; GCN: ; %bb.0:
1433 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1434 ; GCN-NEXT: s_mov_b32 s4, 0x41c00000
1435 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1436 ; GCN-NEXT: s_lshr_b32 s2, s3, 8
1437 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
1438 ; GCN-NEXT: s_mov_b32 s3, 0xf000
1439 ; GCN-NEXT: s_mov_b32 s2, -1
1440 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
1441 ; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1442 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1443 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
1444 ; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
1445 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1446 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1447 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1448 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1449 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1450 ; GCN-NEXT: s_endpgm
1451 ;
1452 ; GCN-IR-LABEL: s_test_udiv24_k_num_i64:
1453 ; GCN-IR: ; %bb.0:
1454 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1455 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
1456 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1457 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
1458 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
1459 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
1460 ; GCN-IR-NEXT: s_mov_b32 s2, -1
1461 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
1462 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1463 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1464 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1465 ; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
1466 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1467 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1468 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1469 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1470 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1471 ; GCN-IR-NEXT: s_endpgm
1472 %x.shr = lshr i64 %x, 40
1473 %result = udiv i64 24, %x.shr
1474 store i64 %result, ptr addrspace(1) %out
1475 ret void
1476 }
1478 define amdgpu_kernel void @s_test_udiv24_k_den_i64(ptr addrspace(1) %out, i64 %x) {
1479 ; GCN-LABEL: s_test_udiv24_k_den_i64:
1480 ; GCN: ; %bb.0:
1481 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1482 ; GCN-NEXT: s_mov_b32 s7, 0xf000
1483 ; GCN-NEXT: s_mov_b32 s6, -1
1484 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1485 ; GCN-NEXT: s_lshr_b32 s2, s3, 8
1486 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
1487 ; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00
1488 ; GCN-NEXT: s_mov_b32 s4, s0
1489 ; GCN-NEXT: s_mov_b32 s5, s1
1490 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1491 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1492 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
1493 ; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0
1494 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
1495 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1496 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1497 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1498 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1499 ; GCN-NEXT: s_endpgm
1500 ;
1501 ; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
1502 ; GCN-IR: ; %bb.0:
1503 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1504 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1505 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1506 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1507 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
1508 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
1509 ; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00
1510 ; GCN-IR-NEXT: s_mov_b32 s4, s0
1511 ; GCN-IR-NEXT: s_mov_b32 s5, s1
1512 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1513 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1514 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1515 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0
1516 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
1517 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1518 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1519 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1520 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1521 ; GCN-IR-NEXT: s_endpgm
1522 %x.shr = lshr i64 %x, 40
1523 %result = udiv i64 %x.shr, 23423
1524 store i64 %result, ptr addrspace(1) %out
1525 ret void
1526 }
1528 define i64 @v_test_udiv24_k_num_i64(i64 %x) {
1529 ; GCN-LABEL: v_test_udiv24_k_num_i64:
1530 ; GCN: ; %bb.0:
1531 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1532 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1533 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
1534 ; GCN-NEXT: s_mov_b32 s4, 0x41c00000
1535 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
1536 ; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1537 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1538 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
1539 ; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
1540 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1541 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1542 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1543 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1544 ; GCN-NEXT: s_setpc_b64 s[30:31]
1545 ;
1546 ; GCN-IR-LABEL: v_test_udiv24_k_num_i64:
1547 ; GCN-IR: ; %bb.0:
1548 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1549 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1550 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
1551 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
1552 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
1553 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1554 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1555 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1556 ; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
1557 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1558 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1559 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1560 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1561 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1562 %x.shr = lshr i64 %x, 40
1563 %result = udiv i64 24, %x.shr
1564 ret i64 %result
1565 }
1567 define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
1568 ; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
1569 ; GCN: ; %bb.0:
1570 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1571 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1572 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
1573 ; GCN-NEXT: s_mov_b32 s4, 0x47000000
1574 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
1575 ; GCN-NEXT: v_mul_f32_e32 v1, 0x47000000, v1
1576 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1577 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
1578 ; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
1579 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1580 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1581 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1582 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1583 ; GCN-NEXT: s_setpc_b64 s[30:31]
1584 ;
1585 ; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64:
1586 ; GCN-IR: ; %bb.0:
1587 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1588 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1589 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
1590 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1591 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
1592 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x47000000, v1
1593 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1594 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1595 ; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
1596 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1597 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1598 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1599 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1600 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1601 %x.shr = lshr i64 %x, 40
1602 %result = udiv i64 32768, %x.shr
1603 ret i64 %result
1604 }
1606 define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
1607 ; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
1608 ; GCN: ; %bb.0:
1609 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1610 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 23, v1
1611 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1612 ; GCN-NEXT: s_setpc_b64 s[30:31]
1613 ;
1614 ; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
1615 ; GCN-IR: ; %bb.0:
1616 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1617 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1618 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
1619 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1620 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38000000, v0
1621 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1622 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1623 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s4, v0
1624 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
1625 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1626 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1627 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1628 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1629 %x.shr = lshr i64 %x, 40
1630 %result = udiv i64 %x.shr, 32768
1631 ret i64 %result
1632 }