| commit | ac4868ea3c495baf5cbcb729e03f95b4425420dc | |
| author | Piyou Chen <piyou.chen@sifive.com> | |
| Thu, 16 Nov 2023 14:34:31 +0000 (16 22:34 +0800) | ||
| committer | GitHub <noreply@github.com> | |
| Thu, 16 Nov 2023 14:34:31 +0000 (16 22:34 +0800) | ||
| tree | d8e7bb662be1295001e962391a55467660597a3e | treesnapshot (tar.gz zip) |
| parent | c0c8679f047e78fbf5d6baa3e9640a3d7e155620 | commitdiff |
[RISCV] Split regalloc between RVV and other (#72096)
Enable this flow by -riscv-split-regalloc=1 (default disable), and could
designate specific allocator to RVV by
-riscv-rvv-regalloc=<fast|basic|greedy>
It uses the RegClass filter function to decide which regclass need to be
processed.
This patch is pre-requirement for supporting PostRA vsetvl insertion
pass.
Enable this flow by -riscv-split-regalloc=1 (default disable), and could
designate specific allocator to RVV by
-riscv-rvv-regalloc=<fast|basic|greedy>
It uses the RegClass filter function to decide which regclass need to be
processed.
This patch is pre-requirement for supporting PostRA vsetvl insertion
pass.
| llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | diffblobblamehistory |