llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

   1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implements the info about RISC-V target spec.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "RISCVTargetMachine.h"
  14 #include "MCTargetDesc/RISCVBaseInfo.h"
  15 #include "RISCV.h"
  16 #include "RISCVMachineFunctionInfo.h"
  17 #include "RISCVMacroFusion.h"
  18 #include "RISCVTargetObjectFile.h"
  19 #include "RISCVTargetTransformInfo.h"
  20 #include "TargetInfo/RISCVTargetInfo.h"
  21 #include "llvm/ADT/STLExtras.h"
  22 #include "llvm/Analysis/TargetTransformInfo.h"
  23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
  24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
  26 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
  27 #include "llvm/CodeGen/MIRParser/MIParser.h"
  28 #include "llvm/CodeGen/MIRYamlMapping.h"
  29 #include "llvm/CodeGen/Passes.h"
  30 #include "llvm/CodeGen/RegAllocRegistry.h"
  31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
  32 #include "llvm/CodeGen/TargetPassConfig.h"
  33 #include "llvm/InitializePasses.h"
  34 #include "llvm/MC/TargetRegistry.h"
  35 #include "llvm/Support/FormattedStream.h"
  36 #include "llvm/Target/TargetOptions.h"
  37 #include "llvm/Transforms/IPO.h"
  38 #include "llvm/Transforms/Scalar.h"
  39 #include <optional>
  40 using namespace llvm;
  41
  42 static cl::opt<bool> EnableRedundantCopyElimination(
  43     "riscv-enable-copyelim",
  44     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
  45     cl::Hidden);
  46
  47 // FIXME: Unify control over GlobalMerge.
  48 static cl::opt<cl::boolOrDefault>
  49     EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
  50                       cl::desc("Enable the global merge pass"));
  51
  52 static cl::opt<bool>
  53     EnableMachineCombiner("riscv-enable-machine-combiner",
  54                           cl::desc("Enable the machine combiner pass"),
  55                           cl::init(true), cl::Hidden);
  56
  57 static cl::opt<unsigned> RVVVectorBitsMaxOpt(
  58     "riscv-v-vector-bits-max",
  59     cl::desc("Assume V extension vector registers are at most this big, "
  60              "with zero meaning no maximum size is assumed."),
  61     cl::init(0), cl::Hidden);
  62
  63 static cl::opt<int> RVVVectorBitsMinOpt(
  64     "riscv-v-vector-bits-min",
  65     cl::desc("Assume V extension vector registers are at least this big, "
  66              "with zero meaning no minimum size is assumed. A value of -1 "
  67              "means use Zvl*b extension. This is primarily used to enable "
  68              "autovectorization with fixed width vectors."),
  69     cl::init(-1), cl::Hidden);
  70
  71 static cl::opt<bool> EnableRISCVCopyPropagation(
  72     "riscv-enable-copy-propagation",
  73     cl::desc("Enable the copy propagation with RISC-V copy instr"),
  74     cl::init(true), cl::Hidden);
  75
  76 static cl::opt<bool> EnableRISCVDeadRegisterElimination(
  77     "riscv-enable-dead-defs", cl::Hidden,
  78     cl::desc("Enable the pass that removes dead"
  79              " definitons and replaces stores to"
  80              " them with stores to x0"),
  81     cl::init(true));
  82
  83 static cl::opt<bool>
  84     EnableSinkFold("riscv-enable-sink-fold",
  85                    cl::desc("Enable sinking and folding of instruction copies"),
  86                    cl::init(false), cl::Hidden);
  87
  88 static cl::opt<bool>
  89     EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden,
  90                            cl::desc("Enable the loop data prefetch pass"),
  91                            cl::init(true));
  92
  93 static cl::opt<bool>
  94     EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
  95                         cl::desc("Enable Split RegisterAlloc for RVV"),
  96                         cl::init(false));
  97
  98 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
  99   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
 100   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
 101   auto *PR = PassRegistry::getPassRegistry();
 102   initializeGlobalISel(*PR);
 103   initializeRISCVO0PreLegalizerCombinerPass(*PR);
 104   initializeRISCVPreLegalizerCombinerPass(*PR);
 105   initializeRISCVPostLegalizerCombinerPass(*PR);
 106   initializeKCFIPass(*PR);
 107   initializeRISCVDeadRegisterDefinitionsPass(*PR);
 108   initializeRISCVMakeCompressibleOptPass(*PR);
 109   initializeRISCVGatherScatterLoweringPass(*PR);
 110   initializeRISCVCodeGenPreparePass(*PR);
 111   initializeRISCVPostRAExpandPseudoPass(*PR);
 112   initializeRISCVMergeBaseOffsetOptPass(*PR);
 113   initializeRISCVOptWInstrsPass(*PR);
 114   initializeRISCVPreRAExpandPseudoPass(*PR);
 115   initializeRISCVExpandPseudoPass(*PR);
 116   initializeRISCVFoldMasksPass(*PR);
 117   initializeRISCVInsertVSETVLIPass(*PR);
 118   initializeRISCVInsertReadWriteCSRPass(*PR);
 119   initializeRISCVInsertWriteVXRMPass(*PR);
 120   initializeRISCVDAGToDAGISelPass(*PR);
 121   initializeRISCVInitUndefPass(*PR);
 122   initializeRISCVMoveMergePass(*PR);
 123   initializeRISCVPushPopOptPass(*PR);
 124 }
 125
 126 static StringRef computeDataLayout(const Triple &TT) {
 127   if (TT.isArch64Bit())
 128     return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
 129   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
 130   return "e-m:e-p:32:32-i64:64-n32-S128";
 131 }
 132
 133 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
 134                                            std::optional<Reloc::Model> RM) {
 135   return RM.value_or(Reloc::Static);
 136 }
 137
 138 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
 139                                        StringRef CPU, StringRef FS,
 140                                        const TargetOptions &Options,
 141                                        std::optional<Reloc::Model> RM,
 142                                        std::optional<CodeModel::Model> CM,
 143                                        CodeGenOptLevel OL, bool JIT)
 144     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
 145                         getEffectiveRelocModel(TT, RM),
 146                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
 147       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
 148   initAsmInfo();
 149
 150   // RISC-V supports the MachineOutliner.
 151   setMachineOutliner(true);
 152   setSupportsDefaultOutlining(true);
 153
 154   if (TT.isOSFuchsia() && !TT.isArch64Bit())
 155     report_fatal_error("Fuchsia is only supported for 64-bit");
 156 }
 157
 158 const RISCVSubtarget *
 159 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
 160   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 161   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
 162   Attribute FSAttr = F.getFnAttribute("target-features");
 163
 164   std::string CPU =
 165       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
 166   std::string TuneCPU =
 167       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
 168   std::string FS =
 169       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
 170
 171   unsigned RVVBitsMin = RVVVectorBitsMinOpt;
 172   unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
 173
 174   Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
 175   if (VScaleRangeAttr.isValid()) {
 176     if (!RVVVectorBitsMinOpt.getNumOccurrences())
 177       RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
 178     std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
 179     if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
 180       RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
 181   }
 182
 183   if (RVVBitsMin != -1U) {
 184     // FIXME: Change to >= 32 when VLEN = 32 is supported.
 185     assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
 186                                 isPowerOf2_32(RVVBitsMin))) &&
 187            "V or Zve* extension requires vector length to be in the range of "
 188            "64 to 65536 and a power 2!");
 189     assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
 190            "Minimum V extension vector length should not be larger than its "
 191            "maximum!");
 192   }
 193   assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
 194                               isPowerOf2_32(RVVBitsMax))) &&
 195          "V or Zve* extension requires vector length to be in the range of "
 196          "64 to 65536 and a power 2!");
 197
 198   if (RVVBitsMin != -1U) {
 199     if (RVVBitsMax != 0) {
 200       RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
 201       RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
 202     }
 203
 204     RVVBitsMin = llvm::bit_floor(
 205         (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
 206   }
 207   RVVBitsMax =
 208       llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
 209
 210   SmallString<512> Key;
 211   Key += "RVVMin";
 212   Key += std::to_string(RVVBitsMin);
 213   Key += "RVVMax";
 214   Key += std::to_string(RVVBitsMax);
 215   Key += CPU;
 216   Key += TuneCPU;
 217   Key += FS;
 218   auto &I = SubtargetMap[Key];
 219   if (!I) {
 220     // This needs to be done before we create a new subtarget since any
 221     // creation will depend on the TM and the code generation flags on the
 222     // function that reside in TargetOptions.
 223     resetTargetOptions(F);
 224     auto ABIName = Options.MCOptions.getABIName();
 225     if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
 226             F.getParent()->getModuleFlag("target-abi"))) {
 227       auto TargetABI = RISCVABI::getTargetABI(ABIName);
 228       if (TargetABI != RISCVABI::ABI_Unknown &&
 229           ModuleTargetABI->getString() != ABIName) {
 230         report_fatal_error("-target-abi option != target-abi module flag");
 231       }
 232       ABIName = ModuleTargetABI->getString();
 233     }
 234     I = std::make_unique<RISCVSubtarget>(
 235         TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
 236   }
 237   return I.get();
 238 }
 239
 240 MachineFunctionInfo *RISCVTargetMachine::createMachineFunctionInfo(
 241     BumpPtrAllocator &Allocator, const Function &F,
 242     const TargetSubtargetInfo *STI) const {
 243   return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
 244                                                                     F, STI);
 245 }
 246
 247 TargetTransformInfo
 248 RISCVTargetMachine::getTargetTransformInfo(const Function &F) const {
 249   return TargetTransformInfo(RISCVTTIImpl(this, F));
 250 }
 251
 252 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
 253 // for all memory accesses, so it is reasonable to assume that an
 254 // implementation has no-op address space casts. If an implementation makes a
 255 // change to this, they can override it here.
 256 bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
 257                                              unsigned DstAS) const {
 258   return true;
 259 }
 260
 261 namespace {
 262
 263 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
 264 public:
 265   RVVRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
 266       : RegisterRegAllocBase(N, D, C) {}
 267 };
 268
 269 static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
 270                                const TargetRegisterClass &RC) {
 271   return RISCV::VRRegClass.hasSubClassEq(&RC) ||
 272          RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
 273          RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
 274          RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
 275          RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
 276          RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
 277          RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
 278          RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
 279          RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
 280          RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
 281          RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
 282          RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
 283          RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
 284          RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
 285          RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
 286 }
 287
 288 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
 289
 290 static llvm::once_flag InitializeDefaultRVVRegisterAllocatorFlag;
 291
 292 /// -riscv-rvv-regalloc=<fast|basic|greedy> command line option.
 293 /// This option could designate the rvv register allocator only.
 294 /// For example: -riscv-rvv-regalloc=basic
 295 static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor, false,
 296                RegisterPassParser<RVVRegisterRegAlloc>>
 297     RVVRegAlloc("riscv-rvv-regalloc", cl::Hidden,
 298                 cl::init(&useDefaultRegisterAllocator),
 299                 cl::desc("Register allocator to use for RVV register."));
 300
 301 static void initializeDefaultRVVRegisterAllocatorOnce() {
 302   RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
 303
 304   if (!Ctor) {
 305     Ctor = RVVRegAlloc;
 306     RVVRegisterRegAlloc::setDefault(RVVRegAlloc);
 307   }
 308 }
 309
 310 static FunctionPass *createBasicRVVRegisterAllocator() {
 311   return createBasicRegisterAllocator(onlyAllocateRVVReg);
 312 }
 313
 314 static FunctionPass *createGreedyRVVRegisterAllocator() {
 315   return createGreedyRegisterAllocator(onlyAllocateRVVReg);
 316 }
 317
 318 static FunctionPass *createFastRVVRegisterAllocator() {
 319   return createFastRegisterAllocator(onlyAllocateRVVReg, false);
 320 }
 321
 322 static RVVRegisterRegAlloc basicRegAllocRVVReg("basic",
 323                                                "basic register allocator",
 324                                                createBasicRVVRegisterAllocator);
 325 static RVVRegisterRegAlloc
 326     greedyRegAllocRVVReg("greedy", "greedy register allocator",
 327                          createGreedyRVVRegisterAllocator);
 328
 329 static RVVRegisterRegAlloc fastRegAllocRVVReg("fast", "fast register allocator",
 330                                               createFastRVVRegisterAllocator);
 331
 332 class RISCVPassConfig : public TargetPassConfig {
 333 public:
 334   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
 335       : TargetPassConfig(TM, PM) {
 336     if (TM.getOptLevel() != CodeGenOptLevel::None)
 337       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
 338     setEnableSinkAndFold(EnableSinkFold);
 339   }
 340
 341   RISCVTargetMachine &getRISCVTargetMachine() const {
 342     return getTM<RISCVTargetMachine>();
 343   }
 344
 345   ScheduleDAGInstrs *
 346   createMachineScheduler(MachineSchedContext *C) const override {
 347     const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
 348     if (ST.hasMacroFusion()) {
 349       ScheduleDAGMILive *DAG = createGenericSchedLive(C);
 350       DAG->addMutation(createRISCVMacroFusionDAGMutation());
 351       return DAG;
 352     }
 353     return nullptr;
 354   }
 355
 356   ScheduleDAGInstrs *
 357   createPostMachineScheduler(MachineSchedContext *C) const override {
 358     const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
 359     if (ST.hasMacroFusion()) {
 360       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
 361       DAG->addMutation(createRISCVMacroFusionDAGMutation());
 362       return DAG;
 363     }
 364     return nullptr;
 365   }
 366
 367   void addIRPasses() override;
 368   bool addPreISel() override;
 369   bool addInstSelector() override;
 370   bool addIRTranslator() override;
 371   void addPreLegalizeMachineIR() override;
 372   bool addLegalizeMachineIR() override;
 373   void addPreRegBankSelect() override;
 374   bool addRegBankSelect() override;
 375   bool addGlobalInstructionSelect() override;
 376   void addPreEmitPass() override;
 377   void addPreEmitPass2() override;
 378   void addPreSched2() override;
 379   void addMachineSSAOptimization() override;
 380   FunctionPass *createRVVRegAllocPass(bool Optimized);
 381   bool addRegAssignAndRewriteFast() override;
 382   bool addRegAssignAndRewriteOptimized() override;
 383   void addPreRegAlloc() override;
 384   void addPostRegAlloc() override;
 385   void addOptimizedRegAlloc() override;
 386   void addFastRegAlloc() override;
 387 };
 388 } // namespace
 389
 390 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
 391   return new RISCVPassConfig(*this, PM);
 392 }
 393
 394 FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
 395   // Initialize the global default.
 396   llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,
 397                   initializeDefaultRVVRegisterAllocatorOnce);
 398
 399   RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
 400   if (Ctor != useDefaultRegisterAllocator)
 401     return Ctor();
 402
 403   if (Optimized)
 404     return createGreedyRVVRegisterAllocator();
 405
 406   return createFastRVVRegisterAllocator();
 407 }
 408
 409 bool RISCVPassConfig::addRegAssignAndRewriteFast() {
 410   if (EnableSplitRegAlloc)
 411     addPass(createRVVRegAllocPass(false));
 412   return TargetPassConfig::addRegAssignAndRewriteFast();
 413 }
 414
 415 bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
 416   if (EnableSplitRegAlloc) {
 417     addPass(createRVVRegAllocPass(true));
 418     addPass(createVirtRegRewriter(false));
 419   }
 420   return TargetPassConfig::addRegAssignAndRewriteOptimized();
 421 }
 422
 423 void RISCVPassConfig::addIRPasses() {
 424   addPass(createAtomicExpandPass());
 425
 426   if (getOptLevel() != CodeGenOptLevel::None) {
 427     if (EnableLoopDataPrefetch)
 428       addPass(createLoopDataPrefetchPass());
 429
 430     addPass(createRISCVGatherScatterLoweringPass());
 431     addPass(createInterleavedAccessPass());
 432     addPass(createRISCVCodeGenPreparePass());
 433   }
 434
 435   TargetPassConfig::addIRPasses();
 436 }
 437
 438 bool RISCVPassConfig::addPreISel() {
 439   if (TM->getOptLevel() != CodeGenOptLevel::None) {
 440     // Add a barrier before instruction selection so that we will not get
 441     // deleted block address after enabling default outlining. See D99707 for
 442     // more details.
 443     addPass(createBarrierNoopPass());
 444   }
 445
 446   if (EnableGlobalMerge == cl::BOU_TRUE) {
 447     addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
 448                                   /* OnlyOptimizeForSize */ false,
 449                                   /* MergeExternalByDefault */ true));
 450   }
 451
 452   return false;
 453 }
 454
 455 bool RISCVPassConfig::addInstSelector() {
 456   addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
 457
 458   return false;
 459 }
 460
 461 bool RISCVPassConfig::addIRTranslator() {
 462   addPass(new IRTranslator(getOptLevel()));
 463   return false;
 464 }
 465
 466 void RISCVPassConfig::addPreLegalizeMachineIR() {
 467   if (getOptLevel() == CodeGenOptLevel::None) {
 468     addPass(createRISCVO0PreLegalizerCombiner());
 469   } else {
 470     addPass(createRISCVPreLegalizerCombiner());
 471   }
 472 }
 473
 474 bool RISCVPassConfig::addLegalizeMachineIR() {
 475   addPass(new Legalizer());
 476   return false;
 477 }
 478
 479 void RISCVPassConfig::addPreRegBankSelect() {
 480   if (getOptLevel() != CodeGenOptLevel::None)
 481     addPass(createRISCVPostLegalizerCombiner());
 482 }
 483
 484 bool RISCVPassConfig::addRegBankSelect() {
 485   addPass(new RegBankSelect());
 486   return false;
 487 }
 488
 489 bool RISCVPassConfig::addGlobalInstructionSelect() {
 490   addPass(new InstructionSelect(getOptLevel()));
 491   return false;
 492 }
 493
 494 void RISCVPassConfig::addPreSched2() {
 495   addPass(createRISCVPostRAExpandPseudoPass());
 496
 497   // Emit KCFI checks for indirect calls.
 498   addPass(createKCFIPass());
 499 }
 500
 501 void RISCVPassConfig::addPreEmitPass() {
 502   addPass(&BranchRelaxationPassID);
 503   addPass(createRISCVMakeCompressibleOptPass());
 504
 505   // TODO: It would potentially be better to schedule copy propagation after
 506   // expanding pseudos (in addPreEmitPass2). However, performing copy
 507   // propagation after the machine outliner (which runs after addPreEmitPass)
 508   // currently leads to incorrect code-gen, where copies to registers within
 509   // outlined functions are removed erroneously.
 510   if (TM->getOptLevel() >= CodeGenOptLevel::Default &&
 511       EnableRISCVCopyPropagation)
 512     addPass(createMachineCopyPropagationPass(true));
 513 }
 514
 515 void RISCVPassConfig::addPreEmitPass2() {
 516   if (TM->getOptLevel() != CodeGenOptLevel::None) {
 517     addPass(createRISCVMoveMergePass());
 518     // Schedule PushPop Optimization before expansion of Pseudo instruction,
 519     // ensuring return instruction is detected correctly.
 520     addPass(createRISCVPushPopOptimizationPass());
 521   }
 522   addPass(createRISCVExpandPseudoPass());
 523
 524   // Schedule the expansion of AMOs at the last possible moment, avoiding the
 525   // possibility for other passes to break the requirements for forward
 526   // progress in the LR/SC block.
 527   addPass(createRISCVExpandAtomicPseudoPass());
 528
 529   // KCFI indirect call checks are lowered to a bundle.
 530   addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
 531     return MF.getFunction().getParent()->getModuleFlag("kcfi");
 532   }));
 533 }
 534
 535 void RISCVPassConfig::addMachineSSAOptimization() {
 536   addPass(createRISCVFoldMasksPass());
 537
 538   TargetPassConfig::addMachineSSAOptimization();
 539
 540   if (EnableMachineCombiner)
 541     addPass(&MachineCombinerID);
 542
 543   if (TM->getTargetTriple().getArch() == Triple::riscv64) {
 544     addPass(createRISCVOptWInstrsPass());
 545   }
 546 }
 547
 548 void RISCVPassConfig::addPreRegAlloc() {
 549   addPass(createRISCVPreRAExpandPseudoPass());
 550   if (TM->getOptLevel() != CodeGenOptLevel::None)
 551     addPass(createRISCVMergeBaseOffsetOptPass());
 552   addPass(createRISCVInsertVSETVLIPass());
 553   if (TM->getOptLevel() != CodeGenOptLevel::None &&
 554       EnableRISCVDeadRegisterElimination)
 555     addPass(createRISCVDeadRegisterDefinitionsPass());
 556   addPass(createRISCVInsertReadWriteCSRPass());
 557   addPass(createRISCVInsertWriteVXRMPass());
 558 }
 559
 560 void RISCVPassConfig::addOptimizedRegAlloc() {
 561   insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
 562
 563   TargetPassConfig::addOptimizedRegAlloc();
 564 }
 565
 566 void RISCVPassConfig::addFastRegAlloc() {
 567   addPass(createRISCVInitUndefPass());
 568   TargetPassConfig::addFastRegAlloc();
 569 }
 570
 571
 572 void RISCVPassConfig::addPostRegAlloc() {
 573   if (TM->getOptLevel() != CodeGenOptLevel::None &&
 574       EnableRedundantCopyElimination)
 575     addPass(createRISCVRedundantCopyEliminationPass());
 576 }
 577
 578 yaml::MachineFunctionInfo *
 579 RISCVTargetMachine::createDefaultFuncInfoYAML() const {
 580   return new yaml::RISCVMachineFunctionInfo();
 581 }
 582
 583 yaml::MachineFunctionInfo *
 584 RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
 585   const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
 586   return new yaml::RISCVMachineFunctionInfo(*MFI);
 587 }
 588
 589 bool RISCVTargetMachine::parseMachineFunctionInfo(
 590     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
 591     SMDiagnostic &Error, SMRange &SourceRange) const {
 592   const auto &YamlMFI =
 593       static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
 594   PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
 595   return false;
 596 }