[RISCV] Split regalloc between RVV and other (#72096)
[llvm-project.git] / llvm / lib / Target / 
tree927017175c132247a778dcf7da914dc4edb8b633
drwxr-xr-x   ..
drwxr-xr-x - AArch64
drwxr-xr-x - AMDGPU
drwxr-xr-x - ARC
drwxr-xr-x - ARM
drwxr-xr-x - AVR
drwxr-xr-x - BPF
-rw-r--r-- 1340 CMakeLists.txt
drwxr-xr-x - CSKY
drwxr-xr-x - DirectX
drwxr-xr-x - Hexagon
drwxr-xr-x - Lanai
drwxr-xr-x - LoongArch
drwxr-xr-x - M68k
drwxr-xr-x - MSP430
drwxr-xr-x - Mips
drwxr-xr-x - NVPTX
drwxr-xr-x - PowerPC
-rw-r--r-- 71259 README.txt
drwxr-xr-x - RISCV
drwxr-xr-x - SPIRV
drwxr-xr-x - Sparc
drwxr-xr-x - SystemZ
-rw-r--r-- 4727 Target.cpp
-rw-r--r-- 979 TargetIntrinsicInfo.cpp
-rw-r--r-- 16838 TargetLoweringObjectFile.cpp
-rw-r--r-- 9809 TargetMachine.cpp
-rw-r--r-- 11262 TargetMachineC.cpp
drwxr-xr-x - VE
drwxr-xr-x - WebAssembly
drwxr-xr-x - X86
drwxr-xr-x - XCore
drwxr-xr-x - Xtensa