[rtsan] Add fork/execve interceptors (#117198)main
[llvm-project.git] / llvm / test / Transforms / InstCombine / AArch64 / 
treea92a5bd76899674d7157fa41e1b0d6dd9d7c5e11
drwxr-xr-x   ..
-rw-r--r-- 3664 2012-04-23-Neon-Intrinsics.ll
-rw-r--r-- 939 VectorUtils_heuristics.ll
-rw-r--r-- 2851 aes-intrinsics.ll
-rw-r--r-- 9090 demandelts.ll
-rw-r--r-- 6376 dmb-intrinsics.ll
-rw-r--r-- 71 lit.local.cfg
-rw-r--r-- 4593 neon-min-max-intrinsics.ll
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-rw-r--r-- 29253 sve-intrinsic-comb-all-active-lanes-cvt.ll
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-rw-r--r-- 11188 sve-intrinsic-comb-no-active-lanes-cmp.ll
-rw-r--r-- 16287 sve-intrinsic-comb-no-active-lanes-cvt.ll
-rw-r--r-- 16481 sve-intrinsic-comb-no-active-lanes-loads.ll
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-rw-r--r-- 13050 sve-intrinsic-comb-no-active-lanes-stores.ll
-rw-r--r-- 9602 sve-intrinsic-comb-no-active-lanes-to-zero.ll
-rw-r--r-- 17380 sve-intrinsic-dupqlane.ll
-rw-r--r-- 13897 sve-intrinsic-fma-binops.ll
-rw-r--r-- 8394 sve-intrinsic-fmul-idempotency.ll
-rw-r--r-- 8474 sve-intrinsic-fmul_u-idempotency.ll
-rw-r--r-- 5089 sve-intrinsic-gatherscatter.ll
-rw-r--r-- 3842 sve-intrinsic-insr.ll
-rw-r--r-- 6846 sve-intrinsic-loadstore.ll
-rw-r--r-- 7952 sve-intrinsic-mul-idempotency.ll
-rw-r--r-- 8028 sve-intrinsic-mul_u-idempotency.ll
-rw-r--r-- 33095 sve-intrinsic-muladdsub.ll
-rw-r--r-- 2364 sve-intrinsic-opts-clast.ll
-rw-r--r-- 22114 sve-intrinsic-opts-cmpne.ll
-rw-r--r-- 5322 sve-intrinsic-opts-counting-elems.ll
-rw-r--r-- 3739 sve-intrinsic-opts-dup.ll
-rw-r--r-- 16130 sve-intrinsic-opts-lasta-lastb.ll
-rw-r--r-- 18463 sve-intrinsic-opts-reinterpret.ll
-rw-r--r-- 3646 sve-intrinsic-opts-unpkhi-unpklo.ll
-rw-r--r-- 11502 sve-intrinsic-opts-uzp1.ll
-rw-r--r-- 1406 sve-intrinsic-opts-zip.ll
-rw-r--r-- 5856 sve-intrinsic-sdiv.ll
-rw-r--r-- 1305 sve-intrinsic-sel.ll
-rw-r--r-- 6627 sve-intrinsic-strictfp.ll
-rw-r--r-- 6255 sve-intrinsic-tbl-dupx.ll
-rw-r--r-- 10527 sve-intrinsic-to-svbool-binops.ll
-rw-r--r-- 157557 sve-intrinsics-combine-to-u-forms.ll
-rw-r--r-- 15608 sve-intrinsics-ptest.ll
-rw-r--r-- 798 sve-intrinsics-rdffr-predication.ll
-rw-r--r-- 3017 tbl1.ll