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23 The LLVM Target-Independent Code Generator
24 </div>
26 <ol>
28 <ul>
31 generator</a></li>
33 </ul>
34 </li>
36 <ul>
45 </ul>
46 </li>
48 <ul>
51 class</a></li>
53 </ul>
54 </li>
56 <ul>
62 </ul>
63 </li>
65 <ul>
67 <ul>
70 Process</a></li>
72 Construction</a></li>
76 Phase: the DAG Combiner</a></li>
79 Phase</a></li>
81 SelectionDAG</a></li>
82 </ul></li>
84 <ul>
87 </ul></li>
89 <ul>
91 LLVM</a></li>
93 registers</a></li>
98 </ul></li>
100 </ul>
101 </li>
105 <ul>
111 <ul>
116 </ul></li>
117 </ul></li>
119 </ol>
123 </div>
127 </div>
129 <!-- *********************************************************************** -->
132 </div>
133 <!-- *********************************************************************** -->
137 <p>The LLVM target-independent code generator is a framework that provides a
138 suite of reusable components for translating the LLVM internal representation
139 to the machine code for a specified target—either in assembly form
140 (suitable for a static compiler) or in binary machine code format (usable for
141 a JIT compiler). The LLVM target-independent code generator consists of six
142 main components:</p>
144 <ol>
146 capture important properties about various aspects of the machine,
147 independently of how they will be used. These interfaces are defined in
151 generated</a> for a target. These classes are intended to be abstract
155 exposed.</li>
157 <li>Classes and algorithms used to represent code as the object file level,
159 constructs like labels, sections, and instructions. At this level,
163 various phases of native code generation (register allocation, scheduling,
164 stack frame representation, etc). This code lives
168 interfaces</a> for particular targets. These machine descriptions make
169 use of the components provided by LLVM, and can optionally provide custom
170 target-specific passes, to build complete code generators for a specific
175 structure to interface for target-specific issues. The code for the
177 </ol>
179 <p>Depending on which part of the code generator you are interested in working
180 on, different pieces of this will be useful to you. In any case, you should
183 want to add a backend for a new target, you will need
186 representation</a>. If you are interested in implementing a
188 depend on the target-description and machine code representation classes,
189 ensuring that it is portable.</p>
191 </div>
193 <!-- ======================================================================= -->
196 </div>
200 <p>The two pieces of the LLVM code generator are the high-level interface to the
201 code generator and the set of reusable components that can be used to build
202 target-specific backends. The two most important interfaces
205 required to be defined for a backend to fit into the LLVM system, but the
206 others must be defined if the reusable code generator components are going to
207 be used.</p>
209 <p>This design has two important implications. The first is that LLVM can
210 support completely non-traditional code generation targets. For example, the
211 C backend does not require register allocation, instruction selection, or any
212 of the other standard components provided by the system. As such, it only
213 implements these two interfaces, and does its own thing. Another example of
214 a code generator like this is a (purely hypothetical) backend that converts
215 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
217 <p>This design also implies that it is possible to design and implement
218 radically different code generators in the LLVM system that do not make use
219 of any of the built-in components. Doing so is not recommended at all, but
220 could be required for radically different targets that do not fit into the
221 LLVM machine description model: FPGAs for example.</p>
223 </div>
225 <!-- ======================================================================= -->
228 </div>
232 <p>The LLVM target-independent code generator is designed to support efficient
233 and quality code generation for standard register-based microprocessors.
234 Code generation in this model is divided into the following stages:</p>
236 <ol>
238 determines an efficient way to express the input LLVM code in the target
239 instruction set. This stage produces the initial code for the program in
240 the target instruction set, then makes use of virtual registers in SSA
241 form and physical registers that represent any required register
242 assignments due to target constraints or calling conventions. This step
243 turns the LLVM code into a DAG of target instructions.</li>
246 This phase takes the DAG of target instructions produced by the
247 instruction selection phase, determines an ordering of the instructions,
248 then emits the instructions
251 selection section</a> because it operates on
255 This optional stage consists of a series of machine-code optimizations
256 that operate on the SSA-form produced by the instruction selector.
257 Optimizations like modulo-scheduling or peephole optimization work
258 here.</li>
261 is transformed from an infinite virtual register file in SSA form to the
262 concrete register file used by the target. This phase introduces spill
263 code and eliminates all virtual register references from the program.</li>
266 the machine code has been generated for the function and the amount of
267 stack space required is known (used for LLVM alloca's and spill slots),
268 the prolog and epilog code for the function can be inserted and "abstract
269 stack location references" can be eliminated. This stage is responsible
270 for implementing optimizations like frame-pointer elimination and stack
271 packing.</li>
274 Optimizations that operate on "final" machine code can go here, such as
275 spill code scheduling and peephole optimizations.</li>
278 actually puts out the code for the current function, either in the target
279 assembler format or in machine code.</li>
280 </ol>
282 <p>The code generator is based on the assumption that the instruction selector
283 will use an optimal pattern matching selector to create high-quality
284 sequences of native instructions. Alternative code generator designs based
285 on pattern expansion and aggressive iterative peephole optimization are much
286 slower. This design permits efficient compilation (important for JIT
287 environments) and aggressive optimization (used when generating code offline)
288 by allowing components of varying levels of sophistication to be used for any
289 step of compilation.</p>
291 <p>In addition to these stages, target implementations can insert arbitrary
292 target-specific passes into the flow. For example, the X86 target uses a
293 special pass to handle the 80x87 floating point stack architecture. Other
294 targets with unusual requirements can be supported with custom passes as
295 needed.</p>
297 </div>
299 <!-- ======================================================================= -->
302 </div>
306 <p>The target description classes require a detailed description of the target
307 architecture. These target descriptions often have a large amount of common
310 commonality to be factored out, the LLVM code generator uses
312 chunks of the target machine, which allows the use of domain-specific and
313 target-specific abstractions to reduce the amount of repetition.</p>
315 <p>As LLVM continues to be developed and refined, we plan to move more and more
317 number of advantages. The most important is that it makes it easier to port
318 LLVM because it reduces the amount of C++ code that has to be written, and
319 the surface area of the code generator that needs to be understood before
320 someone can get something working. Second, it makes it easier to change
321 things. In particular, if tables and other things are all emitted
323 update all of the targets to a new interface.</p>
325 </div>
327 <!-- *********************************************************************** -->
330 </div>
331 <!-- *********************************************************************** -->
335 <p>The LLVM target description classes (located in the
337 the target machine independent of any particular client. These classes are
339 instructions and registers it has), and do not incorporate any particular
340 pieces of code generation algorithms.</p>
342 <p>All of the target description classes (except the
344 subclassed by the concrete target implementation, and have virtual methods
345 implemented. To get to these implementations, the
347 that should be implemented by the target.</p>
349 </div>
351 <!-- ======================================================================= -->
354 </div>
359 access the target-specific implementations of the various target description
362 designed to be specialized by a concrete target implementation
364 methods. The only required target description class is
366 generator components are to be used, the other interfaces should be
367 implemented as well.</p>
369 </div>
371 <!-- ======================================================================= -->
374 </div>
379 and it is the only class that is not extensible (you cannot derived a new
381 target lays out memory for structures, the alignment requirements for various
382 data types, the size of pointers in the target, and whether the target is
383 little-endian or big-endian.</p>
385 </div>
387 <!-- ======================================================================= -->
390 </div>
395 selectors primarily to describe how LLVM code should be lowered to
396 SelectionDAG operations. Among other things, this class indicates:</p>
398 <ul>
407 <li>various high-level characteristics, like whether it is profitable to turn
408 division by a constant into a multiplication sequence</li>
409 </ul>
411 </div>
413 <!-- ======================================================================= -->
416 </div>
421 of the target and any interactions between the registers.</p>
423 <p>Registers in the code generator are represented in the code generator by
424 unsigned integers. Physical registers (those that actually exist in the
425 target description) are unique small numbers, and virtual registers are
428 <p>Each register in the processor description has an associated
430 register (used for assembly output and debugging dumps) and a set of aliases
431 (used to indicate whether one register overlaps with another).</p>
434 class exposes a set of processor specific register classes (instances of the
436 registers that have the same properties (for example, they are all 32-bit
437 integer registers). Each SSA virtual register created by the instruction
438 selector has an associated register class. When the register allocator runs,
439 it replaces virtual registers with a physical register in the set.</p>
441 <p>The target-specific implementations of these classes is auto-generated from
443 register file.</p>
445 </div>
447 <!-- ======================================================================= -->
450 </div>
455 instructions supported by the target. It is essentially an array of
457 instruction the target supports. Descriptors define things like the mnemonic
458 for the opcode, the number of operands, the list of implicit register uses
459 and defs, whether the instruction has certain target-independent properties
460 (accesses memory, is commutable, etc), and holds any target-specific
461 flags.</p>
463 </div>
465 <!-- ======================================================================= -->
468 </div>
473 stack frame layout of the target. It holds the direction of stack growth, the
474 known stack alignment on entry to each function, and the offset to the local
475 area. The offset to the local area is the offset from the stack pointer on
476 function entry to the first location where function data (local variables,
477 spill locations) can be stored.</p>
479 </div>
481 <!-- ======================================================================= -->
484 </div>
489 specific chip set being targeted. A sub-target informs code generation of
490 which instructions are supported, instruction latencies and instruction
491 execution itinerary; i.e., which processing units are used, in what order,
492 and for how long.</p>
494 </div>
497 <!-- ======================================================================= -->
500 </div>
505 Just-In-Time code generator to perform target-specific activities, such as
508 method.</p>
510 </div>
512 <!-- *********************************************************************** -->
515 </div>
516 <!-- *********************************************************************** -->
520 <p>At the high-level, LLVM code is translated to a machine specific
521 representation formed out of
526 agnostic, representing instructions in their most abstract form: an opcode
527 and a series of operands. This representation is designed to support both an
528 SSA representation for machine code, as well as a register allocated, non-SSA
529 form.</p>
531 </div>
533 <!-- ======================================================================= -->
536 </div>
540 <p>Target machine instructions are represented as instances of the
542 representing machine instructions. In particular, it only keeps track of an
543 opcode number and a set of operands.</p>
545 <p>The opcode number is a simple unsigned integer that only has meaning to a
546 specific backend. All of the instructions for a target should be defined in
549 not have any information about how to interpret the instruction (i.e., what
550 the semantics of the instruction are); for that you must refer to the
553 <p>The operands of a machine instruction can be of several different types: a
554 register reference, a constant integer, a basic block reference, etc. In
555 addition, a machine operand should be marked as a def or a use of the value
556 (though only registers are allowed to be defs).</p>
558 <p>By convention, the LLVM code generator orders instruction operands so that
559 all register definitions come before the register uses, even on architectures
560 that are normally printed in other orders. For example, the SPARC add
562 and stores the result into the "%i3" register. In the LLVM code generator,
563 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
564 destination first.</p>
566 <p>Keeping destination (definition) operands at the beginning of the operand
567 list has several advantages. In particular, the debugging printer will print
568 the instruction like this:</p>
571 <pre>
572 %r3 = add %i1, %i2
573 </pre>
574 </div>
579 </div>
581 <!-- _______________________________________________________________________ -->
584 </div>
594 <pre>
596 // instruction. The '1' specifies how many operands will be added.
599 // Create the same instr, but insert it at the end of a basic block.
600 MachineBasicBlock &MBB = ...
603 // Create the same instr, but insert it before a specified iterator point.
604 MachineBasicBlock::iterator MBBI = ...
607 // Create a 'cmp Reg, 0' instruction, no destination reg.
609 // Create an 'sahf' instruction which takes no operands and stores nothing.
610 MI = BuildMI(X86::SAHF, 0);
612 // Create a self looping branch instruction.
614 </pre>
615 </div>
618 have to specify the number of operands that the machine instruction will
619 take. This allows for efficient memory allocation. You also need to specify
620 if operands default to be uses of values, not definitions. If you need to
621 add a definition operand (other than the optional destination register), you
622 must explicitly mark it as such:</p>
625 <pre>
626 MI.addReg(Reg, RegState::Define);
627 </pre>
628 </div>
630 </div>
632 <!-- _______________________________________________________________________ -->
635 </div>
639 <p>One important issue that the code generator needs to be aware of is the
640 presence of fixed registers. In particular, there are often places in the
642 particular value to be in a particular register. This can occur due to
643 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
645 calling conventions. In any case, the instruction selector should emit code
646 that copies a virtual register into or out of a physical register when
647 needed.</p>
652 <pre>
653 define i32 @test(i32 %X, i32 %Y) {
654 %Z = udiv i32 %X, %Y
655 ret i32 %Z
656 }
657 </pre>
658 </div>
662 get this):</p>
665 <pre>
666 ;; Start of div
667 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
668 %reg1027 = sar %reg1024, 31
669 %EDX = mov %reg1027 ;; Sign extend X into EDX
670 idiv %reg1025 ;; Divide by Y (in reg1025)
671 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
673 ;; Start of ret
674 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
675 ret
676 </pre>
677 </div>
679 <p>By the end of code generation, the register allocator has coalesced the
680 registers and deleted the resultant identity moves producing the following
681 code:</p>
684 <pre>
685 ;; X is in EAX, Y is in ECX
686 mov %EAX, %EDX
687 sar %EDX, 31
688 idiv %ECX
689 ret
690 </pre>
691 </div>
693 <p>This approach is extremely general (if it can handle the X86 architecture, it
694 can handle anything!) and allows all of the target specific knowledge about
695 the instruction stream to be isolated in the instruction selector. Note that
696 physical registers should have a short lifetime for good code generation, and
697 all physical registers are assumed dead on entry to and exit from basic
698 blocks (before register allocation). Thus, if you need a value to be live
700 register.</p>
702 </div>
704 <!-- _______________________________________________________________________ -->
707 </div>
712 maintained in SSA-form until register allocation happens. For the most part,
713 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
714 become machine code PHI nodes, and virtual registers are only allowed to have
715 a single definition.</p>
717 <p>After register allocation, machine code is no longer in SSA-form because
718 there are no virtual registers left in the code.</p>
720 </div>
722 <!-- ======================================================================= -->
725 </div>
731 corresponds to the LLVM code input to the instruction selector, but there can
732 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
734 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
735 comes from.</p>
737 </div>
739 <!-- ======================================================================= -->
742 </div>
748 corresponds one-to-one with the LLVM function input to the instruction
749 selector. In addition to a list of basic blocks,
755 </div>
758 <!-- *********************************************************************** -->
761 </div>
762 <!-- *********************************************************************** -->
766 <p>
767 The MC Layer is used to represent and process code at the raw machine code
769 "global variables" or anything like that. At this level, LLVM handles things
770 like label names, machine instructions, and sections in the object file. The
771 code in this layer is used for a number of important purposes: the tail end of
772 the code generator uses it to write a .s or .o file, and it is also used by the
773 llvm-mc tool to implement standalone machine codeassemblers and disassemblers.
774 </p>
776 <p>
777 This section describes some of the important classes. There are also a number
778 of important subsystems that interact at this layer, they are described later
779 in this manual.
780 </p>
782 </div>
785 <!-- ======================================================================= -->
788 </div>
792 <p>
793 MCStreamer is best thought of as an assembler API. It is an abstract API which
795 ELF .o file, etc) but whose API correspond directly to what you see in a .s
796 file. MCStreamer has one method per directive, such as EmitLabel,
797 EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
798 directly correspond to assembly level directives. It also has an
799 EmitInstruction method, which is used to output an MCInst to the streamer.
800 </p>
802 <p>
803 This API is most important for two clients: the llvm-mc stand-alone assembler is
804 effectively a parser that parses a line, then invokes a method on MCStreamer. In
806 generator lowers higher level LLVM IR and Machine* constructs down to the MC
807 layer, emitting directives through MCStreamer.</p>
809 <p>
810 On the implementation side of MCStreamer, there are two major implementations:
811 one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
812 file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
813 that prints out a directive for each method (e.g. EmitValue -> .byte), but
814 MCObjectStreamer implements a full assembler.
815 </p>
817 </div>
819 <!-- ======================================================================= -->
822 </div>
826 <p>
827 The MCContext class is the owner of a variety of uniqued data structures at the
828 MC layer, including symbols, sections, etc. As such, this is the class that you
829 interact with to create symbols and sections. This class can not be subclassed.
830 </p>
832 </div>
834 <!-- ======================================================================= -->
837 </div>
841 <p>
842 The MCSymbol class represents a symbol (aka label) in the assembly file. There
843 are two interesting kinds of symbols: assembler temporary symbols, and normal
844 symbols. Assembler temporary symbols are used and processed by the assembler
845 but are discarded when the object file is produced. The distinction is usually
846 represented by adding a prefix to the label, for example "L" labels are
847 assembler temporary labels in MachO.
848 </p>
850 <p>MCSymbols are created by MCContext and uniqued there. This means that
851 MCSymbols can be compared for pointer equivalence to find out if they are the
852 same symbol. Note that pointer inequality does not guarantee the labels will
853 end up at different addresses though. It's perfectly legal to output something
854 like this to the .s file:<p>
856 <pre>
857 foo:
858 bar:
859 .byte 4
860 </pre>
864 </div>
866 <!-- ======================================================================= -->
869 </div>
873 <p>
874 The MCSection class represents an object-file specific section. It is subclassed
877 by MCContext. The MCStreamer has a notion of the current section, which can be
878 changed with the SwitchToSection method (which corresponds to a ".section"
879 directive in a .s file).
880 </p>
882 </div>
884 <!-- ======================================================================= -->
887 </div>
891 <p>
892 The MCInst class is a target-independent representation of an instruction. It
894 that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
895 turn, is a simple discriminated union of three cases: 1) a simple immediate,
897 MCExpr.
898 </p>
900 <p>MCInst is the common currency used to represent machine instructions at the
901 MC layer. It is the type used by the instruction encoder, the instruction
902 printer, and the type generated by the assembly parser and disassembler.
903 </p>
905 </div>
908 <!-- *********************************************************************** -->
911 </div>
912 <!-- *********************************************************************** -->
916 <p>This section documents the phases described in the
918 It explains how they work and some of the rationale behind their design.</p>
920 </div>
922 <!-- ======================================================================= -->
925 </div>
929 <p>Instruction Selection is the process of translating LLVM code presented to
930 the code generator into target-specific machine instructions. There are
931 several well-known ways to do this in the literature. LLVM uses a
932 SelectionDAG based instruction selector.</p>
934 <p>Portions of the DAG instruction selector are generated from the target
937 there are still things that require custom C++ code.</p>
939 </div>
941 <!-- _______________________________________________________________________ -->
944 </div>
948 <p>The SelectionDAG provides an abstraction for code representation in a way
949 that is amenable to instruction selection using automatic techniques
950 (e.g. dynamic-programming based optimal pattern matching selectors). It is
951 also well-suited to other phases of code generation; in particular,
952 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
953 post-selection). Additionally, the SelectionDAG provides a host
954 representation where a large variety of very-low-level (but
956 performed; ones which require extensive information about the instructions
957 efficiently supported by the target.</p>
959 <p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
961 operation code (Opcode) that indicates what operation the node performs and
962 the operands to the operation. The various operation node types are
964 file.</p>
966 <p>Although most operations define a single value, each node in the graph may
967 define multiple values. For example, a combined div/rem operation will
968 define both the dividend and the remainder. Many other situations require
969 multiple values as well. Each node also has some number of operands, which
970 are edges to the node defining the used value. Because nodes may define
973 and result value being used, respectively. Each value produced by
975 indicating what the type of the value is.</p>
977 <p>SelectionDAGs contain two different kinds of values: those that represent
978 data flow and those that represent control flow dependencies. Data values
979 are simple edges with an integer or floating point value type. Control edges
981 These edges provide an ordering between nodes that have side effects (such as
982 loads, stores, calls, returns, etc). All nodes that have side effects should
983 take a token chain as input and produce a new one as output. By convention,
984 token chain inputs are always operand #0, and chain results are always the
985 last value produced by an operation.</p>
989 node is the final side-effecting node in the token chain. For example, in a
990 single basic block function it would be the return node.</p>
993 "illegal" DAG. A legal DAG for a target is one that only uses supported
994 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
995 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
996 uses a SREM or UREM operation. The
999 responsible for turning an illegal DAG into a legal DAG.</p>
1001 </div>
1003 <!-- _______________________________________________________________________ -->
1006 </div>
1012 <ol>
1014 performs a simple translation from the input LLVM code to an illegal
1015 SelectionDAG.</li>
1018 stage performs simple optimizations on the SelectionDAG to simplify it,
1019 and recognize meta instructions (like rotates
1021 operations. This makes the resultant code more efficient and
1023 (below) simpler.</li>
1026 — This stage transforms SelectionDAG nodes to eliminate any types
1027 that are unsupported on the target.</li>
1030 SelectionDAG optimizer is run to clean up redundancies exposed by type
1031 legalization.</li>
1034 This stage transforms SelectionDAG nodes to eliminate any operations
1035 that are unsupported on the target.</li>
1038 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1039 operation legalization.</li>
1042 Finally, the target instruction selector matches the DAG operations to
1043 target instructions. This process translates the target-independent input
1044 DAG into another DAG of target instructions.</li>
1047 — The last phase assigns a linear order to the instructions in the
1048 target-instruction DAG and emits them into the MachineFunction being
1049 compiled. This step uses traditional prepass scheduling techniques.</li>
1050 </ol>
1052 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
1053 rest of the code generation passes are run.</p>
1055 <p>One great way to visualize what is going on here is to take advantage of a
1056 few LLC command line options. The following options pop up a window
1057 displaying the SelectionDAG at specific times (if you only get errors printed
1058 to the console while using this, you probably
1060 to add support for it).</p>
1062 <ul>
1064 before the first optimization pass.</li>
1069 optimization pass.</li>
1074 </ul>
1077 This graph is based on the final SelectionDAG, with nodes that must be
1078 scheduled together bundled into a single scheduling-unit node, and with
1079 immediate operands and other nodes that aren't relevant for scheduling
1080 omitted.</p>
1082 </div>
1084 <!-- _______________________________________________________________________ -->
1087 </div>
1094 this pass is to expose as much low-level, target-specific details to the
1095 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1098 requires target-specific hooks to lower calls, returns, varargs, etc. For
1100 interface is used.</p>
1102 </div>
1104 <!-- _______________________________________________________________________ -->
1107 </div>
1111 <p>The Legalize phase is in charge of converting a DAG to only use the types
1112 that are natively supported by the target.</p>
1114 <p>There are two main ways of converting values of unsupported scalar types to
1115 values of supported types: converting small types to larger types
1116 ("promoting"), and breaking up large integer types into smaller ones
1117 ("expanding"). For example, a target might require that all f32 values are
1118 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1119 target might require that all i64 values be expanded into pairs of i32
1120 values. These changes can insert sign and zero extensions as needed to make
1121 sure that the final code has the same behavior as the input.</p>
1123 <p>There are two main ways of converting values of unsupported vector types to
1124 value of supported types: splitting vector types, multiple times if
1125 necessary, until a legal type is found, and extending vector types by adding
1126 elements to the end to round them out to legal types ("widening"). If a
1127 vector gets split all the way down to single-element parts with no supported
1128 vector type being found, the elements are converted to scalars
1131 <p>A target implementation tells the legalizer which types are supported (and
1132 which register class to use for them) by calling the
1135 </div>
1137 <!-- _______________________________________________________________________ -->
1140 </div>
1144 <p>The Legalize phase is in charge of converting a DAG to only use the
1145 operations that are natively supported by the target.</p>
1147 <p>Targets often have weird constraints, such as not supporting every operation
1148 on every supported datatype (e.g. X86 does not support byte conditional moves
1149 and PowerPC does not support sign-extending loads from a 16-bit memory
1150 location). Legalize takes care of this by open-coding another sequence of
1151 operations to emulate the operation ("expansion"), by promoting one type to a
1152 larger type that supports the operation ("promotion"), or by using a
1155 <p>A target implementation tells the legalizer which operations are not
1156 supported (and which of the above three actions to take) by calling the
1158 constructor.</p>
1160 <p>Prior to the existence of the Legalize passes, we required that every target
1162 operator and type even if they are not natively supported. The introduction
1163 of the Legalize phases allows all of the canonicalization patterns to be
1164 shared across targets, and makes it very easy to optimize the canonicalized
1165 code because it is still in the form of a DAG.</p>
1167 </div>
1169 <!-- _______________________________________________________________________ -->
1172 Combiner</a>
1173 </div>
1177 <p>The SelectionDAG optimization phase is run multiple times for code
1178 generation, immediately after the DAG is built and once after each
1179 legalization. The first run of the pass allows the initial code to be
1180 cleaned up (e.g. performing optimizations that depend on knowing that the
1181 operators have restricted type inputs). Subsequent runs of the pass clean up
1182 the messy code generated by the Legalize passes, which allows Legalize to be
1183 very simple (it can focus on making code legal instead of focusing on
1186 <p>One important class of optimizations performed is optimizing inserted sign
1187 and zero extension instructions. We currently use ad-hoc techniques, but
1188 could move to more rigorous techniques in the future. Here are some good
1189 papers on the subject:</p>
1193 Kevin Redwine and Norman Ramsey<br>
1198 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1199 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1200 and Implementation.</p>
1202 </div>
1204 <!-- _______________________________________________________________________ -->
1207 </div>
1211 <p>The Select phase is the bulk of the target-specific code for instruction
1212 selection. This phase takes a legal SelectionDAG as input, pattern matches
1213 the instructions supported by the target to this DAG, and produces a new DAG
1214 of target code. For example, consider the following LLVM fragment:</p>
1217 <pre>
1218 %t1 = fadd float %W, %X
1219 %t2 = fmul float %t1, %Y
1220 %t3 = fadd float %t2, %Z
1221 </pre>
1222 </div>
1224 <p>This LLVM code corresponds to a SelectionDAG that looks basically like
1225 this:</p>
1228 <pre>
1229 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
1230 </pre>
1231 </div>
1233 <p>If a target supports floating point multiply-and-add (FMA) operations, one of
1234 the adds can be merged with the multiply. On the PowerPC, for example, the
1235 output of the instruction selector might look like this DAG:</p>
1238 <pre>
1239 (FMADDS (FADDS W, X), Y, Z)
1240 </pre>
1241 </div>
1244 first two operands and adds the third (as single-precision floating-point
1246 add instruction. To perform this pattern match, the PowerPC backend includes
1247 the following instruction definitions:</p>
1250 <pre>
1252 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1253 "fmadds $FRT, $FRA, $FRC, $FRB",
1254 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1257 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1258 "fadds $FRT, $FRA, $FRB",
1260 </pre>
1261 </div>
1263 <p>The portion of the instruction definition in bold indicates the pattern used
1264 to match the instruction. The DAG operators
1269 <p>The TableGen DAG instruction selector generator reads the instruction
1271 pattern matching code for your target. It has the following strengths:</p>
1273 <ul>
1274 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1275 you if your patterns make sense or not.</li>
1277 <li>It can handle arbitrary constraints on operands for the pattern match. In
1278 particular, it is straight-forward to say things like "match any immediate
1279 that is a 13-bit sign-extended value". For examples, see the
1281 backend.</li>
1283 <li>It knows several important identities for the patterns defined. For
1284 example, it knows that addition is commutative, so it allows the
1286 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1287 to specially handle this case.</li>
1289 <li>It has a full-featured type-inferencing system. In particular, you should
1290 rarely have to explicitly tell the system what type parts of your patterns
1293 It was able to infer and propagate this knowledge from the fact that
1297 Pattern fragments are chunks of reusable patterns that get inlined into
1298 your patterns during compiler-compiler time. For example, the integer
1299 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1300 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1302 short-hand fragments as they see fit. See the definition of
1305 <li>In addition to instructions, targets can specify arbitrary patterns that
1306 map to one or more instructions using the 'Pat' class. For example, the
1307 PowerPC has no way to load an arbitrary integer immediate into a register
1308 in one instruction. To tell tblgen how to do this, it defines:
1309 <br>
1310 <br>
1312 <pre>
1313 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1314 def : Pat<(i32 imm:$imm),
1315 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1316 </pre>
1317 </div>
1318 <br>
1319 If none of the single-instruction patterns for loading an immediate into a
1320 register match, this will be used. This rule says "match an arbitrary i32
1321 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1322 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1323 the left 16 bits') instruction". To make this work, the
1325 the input immediate (in this case, take the high or low 16-bits of the
1326 immediate).</li>
1328 <li>While the system does automate a lot, it still allows you to write custom
1329 C++ code to match special cases if there is something that is hard to
1330 express.</li>
1331 </ul>
1333 <p>While it has many strengths, the system currently has some limitations,
1334 primarily because it is a work in progress and is not yet finished:</p>
1336 <ul>
1337 <li>Overall, there is no way to define or match SelectionDAG nodes that define
1339 etc). This is the biggest reason that you currently still <em>have
1342 <li>There is no great way to support matching complex addressing modes yet.
1343 In the future, we will extend pattern fragments to allow them to define
1345 addressing mode</a>, which are currently matched with custom C++ code).
1346 In addition, we'll extend fragments so that a fragment can match multiple
1347 different patterns.</li>
1351 <li>We don't automatically generate the set of supported registers and
1353 yet.</li>
1356 </ul>
1358 <p>Despite these limitations, the instruction selector generator is still quite
1359 useful for most of the binary and logical operations in typical instruction
1360 sets. If you run into any problems or can't figure out how to do something,
1361 please let Chris know!</p>
1363 </div>
1365 <!-- _______________________________________________________________________ -->
1368 </div>
1372 <p>The scheduling phase takes the DAG of target instructions from the selection
1373 phase and assigns an order. The scheduler can pick an order depending on
1374 various constraints of the machines (i.e. order for minimal register pressure
1375 or try to cover instruction latencies). Once an order is established, the
1376 DAG is converted to a list
1378 destroyed.</p>
1380 <p>Note that this phase is logically separate from the instruction selection
1381 phase, but is tied to it closely in the code because it operates on
1382 SelectionDAGs.</p>
1384 </div>
1386 <!-- _______________________________________________________________________ -->
1389 </div>
1393 <ol>
1397 </ol>
1399 </div>
1401 <!-- ======================================================================= -->
1404 </div>
1407 <!-- ======================================================================= -->
1410 </div>
1416 determine if two or more virtual registers which require the same physical
1417 register are live at the same point in the program (i.e., they conflict).
1420 </div>
1422 <!-- _______________________________________________________________________ -->
1425 </div>
1429 <p>The first step in determining the live intervals of variables is to calculate
1430 the set of registers that are immediately dead after the instruction (i.e.,
1431 the instruction calculates the value, but it is never used) and the set of
1432 registers that are used by the instruction, but are never used after the
1433 instruction (i.e., they are killed). Live variable information is computed
1435 register in the function. This is done in a very efficient manner because it
1436 uses SSA to sparsely compute lifetime information for virtual registers
1437 (which are in SSA form) and only has to track physical registers within a
1438 block. Before register allocation, LLVM can assume that physical registers
1439 are only live within a single basic block. This allows it to do a single,
1440 local analysis to resolve physical register lifetimes within each basic
1441 block. If a physical register is not register allocatable (e.g., a stack
1442 pointer or condition codes), it is not tracked.</p>
1444 <p>Physical registers may be live in to or out of a function. Live in values are
1445 typically arguments in registers. Live out values are typically return values
1446 in registers. Live in values are marked as such, and are given a dummy
1447 "defining" instruction during live intervals analysis. If the last basic
1449 out values in the function.</p>
1452 the live variable information from a depth first traversal of the CFG of the
1455 only the definition is handled, because the uses will be handled in other
1456 basic blocks.</p>
1459 assignment at the end of the current basic block and traverse the successor
1463 of its predecessor basic blocks, until the basic block with the defining
1464 instruction is encountered.</p>
1466 </div>
1468 <!-- _______________________________________________________________________ -->
1471 </div>
1475 <p>We now have the information available to perform the live intervals analysis
1476 and build the live intervals themselves. We start off by numbering the basic
1477 blocks and machine instructions. We then handle the "live-in" values. These
1478 are in physical registers, so the physical register is assumed to be killed
1479 by the end of the basic block. Live intervals for virtual registers are
1486 </div>
1488 <!-- ======================================================================= -->
1491 </div>
1498 number of physical registers. Each target architecture has a different number
1499 of physical registers. If the number of physical registers is not enough to
1500 accommodate all the virtual registers, some of them will have to be mapped
1503 </div>
1505 <!-- _______________________________________________________________________ -->
1509 </div>
1513 <p>In LLVM, physical registers are denoted by integer numbers that normally
1516 architecture. For instance, by
1521 <p>Some architectures contain registers that share the same physical location. A
1522 notable example is the X86 platform. For instance, in the X86 architecture,
1525 particular architecture, you can check which registers are aliased by
1531 Elements in the same register class are functionally equivalent, and can be
1532 interchangeably used. Each virtual register can only be mapped to physical
1533 registers of a particular class. For instance, in the X86 architecture, some
1534 virtuals can only be allocated to 8 bit registers. A register class is
1536 register is compatible with a given physical, this code can be used:</p>
1539 <pre>
1540 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1541 unsigned v_reg,
1542 unsigned p_reg) {
1543 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
1544 "Target register must be physical");
1545 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1546 return trc->contains(p_reg);
1547 }
1548 </pre>
1549 </div>
1551 <p>Sometimes, mostly for debugging purposes, it is useful to change the number
1552 of physical registers available in the target architecture. This must be done
1555 registers. Just commenting some out is one simple way to avoid them being
1556 used. A more polite way is to explicitly exclude some registers from
1559 </p>
1561 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
1562 registers, different virtual registers never share the same number. Whereas
1564 file and cannot be created by the application developer, that is not the case
1565 with virtual registers. In order to create new virtual registers, use the
1569 need to enumerate all virtual registers, use the function
1571 numbers:</p>
1574 <pre>
1576 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1577 stuff(VirtReg);
1578 }
1579 </pre>
1580 </div>
1582 <p>Before register allocation, the operands of an instruction are mostly virtual
1583 registers, although physical registers may also be used. In order to check if
1584 a given machine operand is a register, use the boolean
1590 register is being used by the instruction. The
1592 defined.</p>
1594 <p>We will call physical registers present in the LLVM bitcode before register
1596 many different situations, for instance, to pass parameters of functions
1597 calls, and to store results of particular instructions. There are two types
1600 operands, and can be accessed
1602 which registers are implicitly defined by an instruction, use
1605 difference between explicit and implicit physical registers is that the
1606 latter are defined statically for each instruction, whereas the former may
1607 vary depending on the program being compiled. For example, an instruction
1608 that represents a function call will always implicitly define or use the same
1609 set of physical registers. To read the registers implicitly used by an
1610 instruction,
1612 registers impose constraints on any register allocation algorithm. The
1613 register allocator must make sure that none of them are overwritten by
1614 the values of virtual registers while still alive.</p>
1616 </div>
1618 <!-- _______________________________________________________________________ -->
1622 </div>
1626 <p>There are two ways to map virtual registers to physical registers (or to
1631 and stores sending and getting values to and from memory.</p>
1633 <p>The direct mapping provides more flexibility to the developer of the register
1634 allocator; however, it is more error prone, and demands more implementation
1635 work. Basically, the programmer will have to specify where load and store
1636 instructions should be inserted in the target function being compiled in
1637 order to get and store values in memory. To assign a physical register to a
1638 virtual register present in a given operand,
1643 <p>The indirect mapping shields the application developer from the complexities
1644 of inserting load and store instructions. In order to map a virtual register
1646 order to map a certain virtual register to memory,
1649 necessary to map another virtual register to the same stack slot,
1651 important point to consider when using the indirect mapping, is that even if
1652 a virtual register is mapped to memory, it still needs to be mapped to a
1653 physical register. This physical register is the location where the virtual
1654 register is supposed to be found before being stored or after being
1655 reloaded.</p>
1657 <p>If the indirect strategy is used, after all the virtual registers have been
1658 mapped to physical registers or stack slots, it is necessary to use a spiller
1659 object to place load and store instructions in the code. Every virtual that
1660 has been mapped to a stack slot will be stored to memory after been defined
1661 and will be loaded before being used. The implementation of the spiller tries
1662 to recycle load/store instructions, avoiding unnecessary instructions. For an
1663 example of how to invoke the spiller,
1667 </div>
1669 <!-- _______________________________________________________________________ -->
1672 </div>
1676 <p>With very rare exceptions (e.g., function calls), the LLVM machine code
1677 instructions are three address instructions. That is, each instruction is
1678 expected to define at most one register, and to use at most two registers.
1679 However, some architectures use two address instructions. In this case, the
1680 defined register is also one of the used register. For instance, an
1684 <p>In order to produce correct code, LLVM must convert three address
1685 instructions that represent two address instructions into true two address
1687 this specific purpose. It must be run before register allocation takes
1688 place. After its execution, the resulting code may no longer be in SSA
1689 form. This happens, for instance, in situations where an instruction such
1693 <pre>
1694 %a = MOVE %b
1695 %a = ADD %a %c
1696 </pre>
1697 </div>
1699 <p>Notice that, internally, the second instruction is represented as
1701 used and defined by the instruction.</p>
1703 </div>
1705 <!-- _______________________________________________________________________ -->
1708 </div>
1712 <p>An important transformation that happens during register allocation is called
1714 that are performed on the control flow graph of programs. However,
1715 traditional instruction sets do not implement PHI instructions. Thus, in
1716 order to generate executable code, compilers must replace PHI instructions
1717 with other instructions that preserve their semantics.</p>
1719 <p>There are many ways in which PHI instructions can safely be removed from the
1720 target code. The most traditional PHI deconstruction algorithm replaces PHI
1721 instructions with copy instructions. That is the strategy adopted by
1722 LLVM. The SSA deconstruction algorithm is implemented
1725 of the register allocator.</p>
1727 </div>
1729 <!-- _______________________________________________________________________ -->
1732 </div>
1737 allocation that removes unnecessary copy instructions. For instance, a
1738 sequence of instructions such as:</p>
1741 <pre>
1742 %EBX = LOAD %mem_address
1743 %EAX = COPY %EBX
1744 </pre>
1745 </div>
1750 <pre>
1751 %EAX = LOAD %mem_address
1752 </pre>
1753 </div>
1755 <p>Instructions can be folded with
1757 taken when folding instructions; a folded instruction can be quite different
1758 from the original
1761 use.</p>
1763 </div>
1765 <!-- _______________________________________________________________________ -->
1769 </div>
1773 <p>The LLVM infrastructure provides the application developer with three
1774 different register allocators:</p>
1776 <ul>
1778 well-know linear scan register allocator. Whereas the
1781 uses a spiller in order to place load and stores.</li>
1784 builds. It allocates registers on a basic block level, attempting to keep
1785 values in registers and reusing registers as appropriate.</li>
1788 based register allocator. This allocator works by constructing a PBQP
1789 problem representing the register allocation problem under consideration,
1790 solving this using a PBQP solver, and mapping the solution back to a
1791 register assignment.</li>
1793 </ul>
1799 <pre>
1800 $ llc -regalloc=linearscan file.bc -o ln.s;
1801 $ llc -regalloc=fast file.bc -o fa.s;
1802 $ llc -regalloc=pbqp file.bc -o pbqp.s;
1803 </pre>
1804 </div>
1806 </div>
1808 <!-- ======================================================================= -->
1811 </div>
1813 <!-- ======================================================================= -->
1816 </div>
1819 <!-- ======================================================================= -->
1822 </div>
1826 <p>The code emission step of code generation is responsible for lowering from
1827 the code generator abstractions (like <a
1832 done with a combination of several different classes: the (misnamed)
1833 target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
1834 (such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
1836 <p>Since the MC layer works at the level of abstraction of object files, it
1837 doesn't have a notion of functions, global variables etc. Instead, it thinks
1838 about labels, directives, and instructions. A key class used at this time is
1839 the MCStreamer class. This is an abstract API that is implemented in different
1840 ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
1841 an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
1842 EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
1843 level directives.
1844 </p>
1846 <p>If you are interested in implementing a code generator for a target, there
1847 are three important things that you have to implement for your target:</p>
1849 <ol>
1850 <li>First, you need a subclass of AsmPrinter for your target. This class
1851 implements the general lowering process converting MachineFunction's into MC
1852 label constructs. The AsmPrinter base class provides a number of useful methods
1853 and routines, and also allows you to override the lowering process in some
1854 important ways. You should get much of the lowering for free if you are
1855 implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
1856 class implements much of the common logic.</li>
1858 <li>Second, you need to implement an instruction printer for your target. The
1860 raw_ostream as text. Most of this is automatically generated from the .td file
1861 (when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
1862 instructions), but you need to implement routines to print operands.</li>
1866 "<target>MCInstLower.cpp". This lowering process is often target
1867 specific, and is responsible for turning jump table entries, constant pool
1868 indices, global variable addresses, etc into MCLabels as appropriate. This
1869 translation layer is also responsible for expanding pseudo ops used by the code
1870 generator into the actual machine instructions they correspond to. The MCInsts
1871 that are generated by this are fed into the instruction printer or the encoder.
1872 </li>
1874 </ol>
1876 <p>Finally, at your choosing, you can also implement an subclass of
1877 MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
1878 This is important if you want to support direct .o file emission, or would like
1879 to implement an assembler for your target.</p>
1881 </div>
1884 <!-- *********************************************************************** -->
1887 </div>
1888 <!-- *********************************************************************** -->
1892 <p>Though you're probably reading this because you want to write or maintain a
1893 compiler backend, LLVM also fully supports building a native assemblers too.
1894 We've tried hard to automate the generation of the assembler from the .td files
1895 (in particular the instruction syntax and encodings), which means that a large
1896 part of the manual and repetitive data entry can be factored and shared with the
1897 compiler.</p>
1899 </div>
1901 <!-- ======================================================================= -->
1907 <!-- ======================================================================= -->
1909 Instruction Alias Processing
1910 </div>
1913 <p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
1914 The MatchInstructionImpl function performs alias processing and then does
1915 actual matching.</p>
1917 <p>Alias processing is the phase that canonicalizes different lexical forms of
1918 the same instructions down to one representation. There are several different
1919 kinds of alias that are possible to implement and they are listed below in the
1920 order that they are processed (which is in order from simplest/weakest to most
1921 complex/powerful). Generally you want to use the first alias mechanism that
1922 meets the needs of your instruction, because it will allow a more concise
1923 description.</p>
1925 </div>
1927 <!-- _______________________________________________________________________ -->
1932 <p>The first phase of alias processing is simple instruction mnemonic
1933 remapping for classes of instructions which are allowed with two different
1934 mnemonics. This phase is a simple and unconditionally remapping from one input
1935 mnemonic to one output mnemonic. It isn't possible for this form of alias to
1936 look at the operands at all, so the remapping must apply for all forms of a
1937 given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
1938 </p>
1941 <pre>
1947 </pre>
1948 </div>
1950 <p>... and many others. With a MnemonicAlias definition, the mnemonic is
1951 remapped simply and directly. Though MnemonicAlias's can't look at any aspect
1952 of the instruction (such as the operands) they can depend on global modes (the
1953 same ones supported by the matcher), through a Requires clause:</p>
1956 <pre>
1959 </pre>
1960 </div>
1962 <p>In this example, the mnemonic gets mapped into different a new one depending
1963 on the current instruction set.</p>
1965 </div>
1967 <!-- _______________________________________________________________________ -->
1972 <p>The most general phase of alias processing occurs while matching is
1973 happening: it provides new forms for the matcher to match along with a specific
1974 instruction to generate. An instruction alias has two parts: the string to
1975 match and the instruction to generate. For example:
1976 </p>
1979 <pre>
1987 </pre>
1988 </div>
1990 <p>This shows a powerful example of the instruction aliases, matching the
1991 same mnemonic in multiple different ways depending on what operands are present
1992 in the assembly. The result of instruction aliases can include operands in a
1993 different order than the destination instruction, and can use an input
1994 multiple times, for example:</p>
1997 <pre>
2002 </pre>
2003 </div>
2005 <p>This example also shows that tied operands are only listed once. In the X86
2006 backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2007 to the output). InstAliases take a flattened operand list without duplicates
2008 for tied operands. The result of an instruction alias can also use immediates
2009 and fixed physical registers which are added as simple immediate operands in the
2010 result, for example:</p>
2013 <pre>
2014 // Fixed Immediate operand.
2017 // Fixed register operand.
2020 // Simple alias.
2022 </pre>
2023 </div>
2026 <p>Instruction aliases can also have a Requires clause to make them
2027 subtarget specific.</p>
2029 </div>
2033 <!-- ======================================================================= -->
2041 <!-- *********************************************************************** -->
2044 </div>
2045 <!-- *********************************************************************** -->
2049 <p>This section of the document explains features or design decisions that are
2050 specific to the code generator for a particular target. First we start
2051 with a table that summarizes what features are supported by each target.</p>
2053 </div>
2055 <!-- ======================================================================= -->
2058 </div>
2062 <p>Note that this table does not include the C backend or Cpp backends, since
2063 they do not use the target independent code generator infrastructure. It also
2064 doesn't list features that are not supported fully by any target yet. It
2065 considers a feature to be supported if at least one subtarget supports it. A
2066 feature being supported means that it is useful and works for most cases, it
2067 does not indicate that there are zero known bugs in the implementation. Here
2068 is the key:</p>
2072 <tr>
2077 </tr>
2078 <tr>
2083 </tr>
2084 </table>
2089 <tr><td></td>
2091 </tr>
2092 <tr>
2107 </tr>
2109 <tr>
2124 </tr>
2126 <tr>
2141 </tr>
2143 <tr>
2158 </tr>
2160 <tr>
2175 </tr>
2177 <tr>
2192 </tr>
2194 <tr>
2209 </tr>
2211 <tr>
2226 </tr>
2229 </table>
2231 </div>
2233 <!-- _______________________________________________________________________ -->
2237 <p>This box indicates whether the target is considered to be production quality.
2238 This indicates that the target has been used as a static compiler to
2239 compile large amounts of code by a variety of different people and is in
2240 continuous use.</p>
2241 </div>
2243 <!-- _______________________________________________________________________ -->
2247 <p>This box indicates whether the target supports parsing target specific .s
2248 files by implementing the MCAsmParser interface. This is required for llvm-mc
2249 to be able to act as a native assembler and is required for inline assembly
2250 support in the native .o file writer.</p>
2252 </div>
2255 <!-- _______________________________________________________________________ -->
2259 <p>This box indicates whether the target supports the MCDisassembler API for
2260 disassembling machine opcode bytes into MCInst's.</p>
2262 </div>
2264 <!-- _______________________________________________________________________ -->
2268 <p>This box indicates whether the target supports most popular inline assembly
2269 constraints and modifiers.</p>
2272 constraints relating to the X86 floating point stack.</p>
2274 </div>
2276 <!-- _______________________________________________________________________ -->
2280 <p>This box indicates whether the target supports the JIT compiler through
2281 the ExecutionEngine interface.</p>
2284 in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2286 </div>
2288 <!-- _______________________________________________________________________ -->
2293 <p>This box indicates whether the target supports writing .o files (e.g. MachO,
2294 ELF, and/or COFF) files directly from the target. Note that the target also
2295 must include an assembly parser and general inline assembly support for full
2296 inline assembly support in the .o writer.</p>
2298 <p>Targets that don't support this feature can obviously still write out .o
2299 files, they just rely on having an external assembler to translate from a .s
2300 file to a .o file (as is the case for many C compilers).</p>
2302 </div>
2304 <!-- _______________________________________________________________________ -->
2309 <p>This box indicates whether the target supports guaranteed tail calls. These
2314 </div>
2319 <!-- ======================================================================= -->
2322 </div>
2326 <p>Tail call optimization, callee reusing the stack of the caller, is currently
2329 <ul>
2333 <li>The call is a tail call - in tail position (ret immediately follows call
2334 and ret uses value of call or is void).</li>
2339 </ul>
2343 <ul>
2347 = hidden or protected) are supported.</li>
2348 </ul>
2352 <ul>
2357 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2358 </ul>
2365 <pre>
2366 declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2368 define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2369 %l1 = add i32 %in1, %in2
2370 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2371 ret i32 %tmp
2372 }
2373 </pre>
2374 </div>
2378 <p>To support tail call optimization in situations where the callee has more
2379 arguments than the caller a 'callee pops arguments' convention is used. This
2381 (because one or more of above constraints are not met) to be followed by a
2382 readjustment of the stack. So performance might be worse in such cases.</p>
2384 </div>
2385 <!-- ======================================================================= -->
2388 </div>
2392 <p>Sibling call optimization is a restricted form of tail call optimization.
2393 Unlike tail call optimization described in the previous section, it can be
2395 is not specified.</p>
2398 following constraints are met:</p>
2400 <ul>
2401 <li>Caller and callee have the same calling convention. It can be either
2404 <li>The call is a tail call - in tail position (ret immediately follows call
2405 and ret uses value of call or is void).</li>
2407 <li>Caller and callee have matching return type or the callee result is not
2408 used.
2410 <li>If any of the callee arguments are being passed in stack, they must be
2411 available in caller's own incoming argument stack and the frame offsets
2412 must be the same.
2413 </ul>
2417 <pre>
2418 declare i32 @bar(i32, i32)
2420 define i32 @foo(i32 %a, i32 %b, i32 %c) {
2421 entry:
2422 %0 = tail call i32 @bar(i32 %a, i32 %b)
2423 ret i32 %0
2424 }
2425 </pre>
2426 </div>
2428 </div>
2429 <!-- ======================================================================= -->
2432 </div>
2438 processors, and includes support for ISA extensions such as MMX and SSE.</p>
2440 </div>
2442 <!-- _______________________________________________________________________ -->
2445 </div>
2449 <p>The following are the known target triples that are supported by the X86
2450 backend. This is not an exhaustive list, and it would be useful to add those
2451 that people test.</p>
2453 <ul>
2467 </ul>
2469 </div>
2471 <!-- _______________________________________________________________________ -->
2474 </div>
2481 <ul>
2487 </ul>
2489 </div>
2491 <!-- _______________________________________________________________________ -->
2494 </div>
2498 <p>The x86 has a very flexible way of accessing memory. It is capable of
2499 forming memory addresses of the following expression directly in integer
2500 instructions (which use ModR/M addressing):</p>
2503 <pre>
2505 </pre>
2506 </div>
2509 memory operand of this form. This means that the "load" form of
2513 <pre>
2515 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2516 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
2517 </pre>
2518 </div>
2520 <p>Stores, and all other instructions, treat the four memory operands in the
2521 same way and in the same order. If the segment register is unspecified
2523 have a segment register specified, so they only have 4 operands for their
2524 memory reference.</p>
2526 </div>
2528 <!-- _______________________________________________________________________ -->
2531 </div>
2535 <p>x86 has an experimental feature which provides
2536 the ability to perform loads and stores to different address spaces
2537 via the x86 segment registers. A segment override prefix byte on an
2538 instruction causes the instruction's memory access to go to the specified
2539 segment. LLVM address space 0 is the default address space, which includes
2540 the stack, and any unqualified memory accesses in a program. Address spaces
2542 represented by address space 256, while the FS-segment is represented by
2543 address space 257. Other x86 segments have yet to be allocated address space
2544 numbers.</p>
2546 <p>While these address spaces may seem similar to TLS via the
2548 there are some fundamental differences.</p>
2551 specifies that they are to be allocated in thread-local memory. There are
2552 no type qualifiers involved, and these variables can be pointed to with
2553 normal pointers and accessed with normal loads and stores.
2555 level (though LLVM doesn't yet have implementations of it for some
2556 configurations).<p>
2558 <p>Special address spaces, in contrast, apply to static types. Every
2559 load and store has a particular address space in its address operand type,
2560 and this is what determines which address space is accessed.
2561 LLVM ignores these special address space qualifiers on global variables,
2562 and does not provide a way to directly allocate storage in them.
2563 At the LLVM IR level, the behavior of these special address spaces depends
2564 in part on the underlying OS or runtime environment, and they are specific
2565 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2567 <p>Some operating systems and runtime environments use (or may in the future
2568 use) the FS/GS-segment registers for various low-level purposes, so care
2569 should be taken when considering them.</p>
2571 </div>
2573 <!-- _______________________________________________________________________ -->
2576 </div>
2580 <p>An instruction name consists of the base name, a default operand size, and a
2581 a character per operand with an optional special size. For example:</p>
2584 <pre>
2589 </pre>
2590 </div>
2592 </div>
2594 <!-- ======================================================================= -->
2597 </div>
2601 <p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
2603 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2605 </div>
2607 <!-- _______________________________________________________________________ -->
2610 </div>
2614 <p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
2615 relative (PIC) or static addressing for accessing global values, so no TOC
2616 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2617 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2618 save the frame pointer in the PowerPC linkage area of the caller frame.
2619 Other details of PowerPC ABI can be found at <a href=
2620 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2623 for system use.</p>
2625 </div>
2627 <!-- _______________________________________________________________________ -->
2630 </div>
2634 <p>The size of a PowerPC frame is usually fixed for the duration of a
2635 function's invocation. Since the frame is fixed size, all references
2636 into the frame can be accessed via fixed offsets from the stack pointer. The
2637 exception to this is when dynamic alloca or variable sized arrays are
2638 present, then a base pointer (r31) is used as a proxy for the stack pointer
2639 and stack pointer is free to grow or shrink. A base pointer is also used if
2640 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2641 always aligned to 16 bytes, so that space allocated for altivec vectors will
2642 be properly aligned.</p>
2647 <tr>
2649 </tr>
2650 <tr>
2652 </tr>
2653 <tr>
2655 </tr>
2656 <tr>
2658 </tr>
2659 <tr>
2661 </tr>
2663 <td><br></td>
2664 </tr>
2665 <tr>
2667 </tr>
2668 </table>
2671 to allocating its own frame. Only three entries are relevant to LLVM. The
2672 first entry is the previous stack pointer (sp), aka link. This allows
2673 probing tools like gdb or exception handlers to quickly scan the frames in
2674 the stack. A function epilog can also use the link to pop the frame from the
2675 stack. The third entry in the linkage area is used to save the return
2676 address from the lr register. Finally, as mentioned above, the last entry is
2677 used to save the previous frame pointer (r31.) The entries in the linkage
2684 <tr>
2687 </tr>
2688 <tr>
2691 </tr>
2692 <tr>
2695 </tr>
2696 <tr>
2699 </tr>
2700 <tr>
2703 </tr>
2704 <tr>
2707 </tr>
2708 </table>
2713 <tr>
2716 </tr>
2717 <tr>
2720 </tr>
2721 <tr>
2724 </tr>
2725 <tr>
2728 </tr>
2729 <tr>
2732 </tr>
2733 <tr>
2736 </tr>
2737 </table>
2740 function. Following the PowerPC ABI, the first few arguments are actually
2741 passed in registers, with the space in the parameter area unused. However,
2742 if there are not enough registers or the callee is a thunk or vararg
2743 function, these register arguments can be spilled into the parameter area.
2744 Thus, the parameter area must be large enough to store all the parameters for
2745 the largest call sequence made by the caller. The size must also be
2746 minimally large enough to spill registers r3-r10. This allows callees blind
2747 to the call signature, such as thunks and vararg functions, enough space to
2748 cache the argument registers. Therefore, the parameter area is minimally 32
2750 a fixed offset from the top of the frame, that a callee can access its spilt
2751 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
2753 <p>Combining the information about the linkage, parameter areas and alignment. A
2755 mode.</p>
2758 alloca then space is added to the stack, the linkage and parameter areas are
2759 shifted to top of stack, and the new space is available immediately below the
2760 linkage and parameter areas. The cost of shifting the linkage and parameter
2761 areas is minor since only the link value needs to be copied. The link value
2762 can be easily fetched by adding the original frame size to the base pointer.
2763 Note that allocations in the dynamic space need to observe 16 byte
2764 alignment.</p>
2767 variables.</p>
2770 saved registers on entry to the callee.</p>
2772 </div>
2774 <!-- _______________________________________________________________________ -->
2777 </div>
2781 <p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
2782 the following exceptions. Callee saved registers are spilled after the frame
2783 is created. This allows the llvm epilog/prolog support to be common with
2784 other targets. The base pointer callee saved register r31 is saved in the
2785 TOC slot of linkage area. This simplifies allocation of space for the base
2786 pointer and makes it convenient to locate programatically and during
2787 debugging.</p>
2789 </div>
2791 <!-- _______________________________________________________________________ -->
2794 </div>
2800 </div>
2803 <!-- *********************************************************************** -->
2804 <hr>
2805 <address>
2813 Last modified: $Date$
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2816 </body>
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