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12 The LLVM Target-Independent Code Generator
13 </div>
15 <ol>
17 <ul>
20 generator</a></li>
22 </ul>
23 </li>
25 <ul>
34 </ul>
35 </li>
37 <ul>
40 class</a></li>
42 </ul>
43 </li>
45 <ul>
47 <ul>
50 Process</a></li>
52 Construction</a></li>
56 Phase: the DAG Combiner</a></li>
59 Phase</a></li>
61 SelectionDAG</a></li>
62 </ul></li>
64 <ul>
67 </ul></li>
69 <ul>
71 LLVM</a></li>
73 registers</a></li>
78 </ul></li>
80 <ul>
83 </ul></li>
84 </ul>
85 </li>
87 <ul>
92 <ul>
97 </ul></li>
98 </ul></li>
100 </ol>
106 Pereira</a> and
108 </div>
112 </div>
114 <!-- *********************************************************************** -->
117 </div>
118 <!-- *********************************************************************** -->
122 <p>The LLVM target-independent code generator is a framework that provides a
123 suite of reusable components for translating the LLVM internal representation
124 to the machine code for a specified target—either in assembly form
125 (suitable for a static compiler) or in binary machine code format (usable for
126 a JIT compiler). The LLVM target-independent code generator consists of five
127 main components:</p>
129 <ol>
131 capture important properties about various aspects of the machine,
132 independently of how they will be used. These interfaces are defined in
136 being generated for a target. These classes are intended to be abstract
141 various phases of native code generation (register allocation, scheduling,
142 stack frame representation, etc). This code lives
146 interfaces</a> for particular targets. These machine descriptions make
147 use of the components provided by LLVM, and can optionally provide custom
148 target-specific passes, to build complete code generators for a specific
153 structure to interface for target-specific issues. The code for the
155 </ol>
157 <p>Depending on which part of the code generator you are interested in working
158 on, different pieces of this will be useful to you. In any case, you should
161 want to add a backend for a new target, you will need
164 representation</a>. If you are interested in implementing a
166 depend on the target-description and machine code representation classes,
167 ensuring that it is portable.</p>
169 </div>
171 <!-- ======================================================================= -->
174 </div>
178 <p>The two pieces of the LLVM code generator are the high-level interface to the
179 code generator and the set of reusable components that can be used to build
180 target-specific backends. The two most important interfaces
183 required to be defined for a backend to fit into the LLVM system, but the
184 others must be defined if the reusable code generator components are going to
185 be used.</p>
187 <p>This design has two important implications. The first is that LLVM can
188 support completely non-traditional code generation targets. For example, the
189 C backend does not require register allocation, instruction selection, or any
190 of the other standard components provided by the system. As such, it only
191 implements these two interfaces, and does its own thing. Another example of
192 a code generator like this is a (purely hypothetical) backend that converts
193 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
195 <p>This design also implies that it is possible to design and implement
196 radically different code generators in the LLVM system that do not make use
197 of any of the built-in components. Doing so is not recommended at all, but
198 could be required for radically different targets that do not fit into the
199 LLVM machine description model: FPGAs for example.</p>
201 </div>
203 <!-- ======================================================================= -->
206 </div>
210 <p>The LLVM target-independent code generator is designed to support efficient
211 and quality code generation for standard register-based microprocessors.
212 Code generation in this model is divided into the following stages:</p>
214 <ol>
216 determines an efficient way to express the input LLVM code in the target
217 instruction set. This stage produces the initial code for the program in
218 the target instruction set, then makes use of virtual registers in SSA
219 form and physical registers that represent any required register
220 assignments due to target constraints or calling conventions. This step
221 turns the LLVM code into a DAG of target instructions.</li>
224 This phase takes the DAG of target instructions produced by the
225 instruction selection phase, determines an ordering of the instructions,
226 then emits the instructions
229 selection section</a> because it operates on
233 This optional stage consists of a series of machine-code optimizations
234 that operate on the SSA-form produced by the instruction selector.
235 Optimizations like modulo-scheduling or peephole optimization work
236 here.</li>
239 is transformed from an infinite virtual register file in SSA form to the
240 concrete register file used by the target. This phase introduces spill
241 code and eliminates all virtual register references from the program.</li>
244 the machine code has been generated for the function and the amount of
245 stack space required is known (used for LLVM alloca's and spill slots),
246 the prolog and epilog code for the function can be inserted and "abstract
247 stack location references" can be eliminated. This stage is responsible
248 for implementing optimizations like frame-pointer elimination and stack
249 packing.</li>
252 Optimizations that operate on "final" machine code can go here, such as
253 spill code scheduling and peephole optimizations.</li>
256 actually puts out the code for the current function, either in the target
257 assembler format or in machine code.</li>
258 </ol>
260 <p>The code generator is based on the assumption that the instruction selector
261 will use an optimal pattern matching selector to create high-quality
262 sequences of native instructions. Alternative code generator designs based
263 on pattern expansion and aggressive iterative peephole optimization are much
264 slower. This design permits efficient compilation (important for JIT
265 environments) and aggressive optimization (used when generating code offline)
266 by allowing components of varying levels of sophistication to be used for any
267 step of compilation.</p>
269 <p>In addition to these stages, target implementations can insert arbitrary
270 target-specific passes into the flow. For example, the X86 target uses a
271 special pass to handle the 80x87 floating point stack architecture. Other
272 targets with unusual requirements can be supported with custom passes as
273 needed.</p>
275 </div>
277 <!-- ======================================================================= -->
280 </div>
284 <p>The target description classes require a detailed description of the target
285 architecture. These target descriptions often have a large amount of common
288 commonality to be factored out, the LLVM code generator uses
290 chunks of the target machine, which allows the use of domain-specific and
291 target-specific abstractions to reduce the amount of repetition.</p>
293 <p>As LLVM continues to be developed and refined, we plan to move more and more
295 number of advantages. The most important is that it makes it easier to port
296 LLVM because it reduces the amount of C++ code that has to be written, and
297 the surface area of the code generator that needs to be understood before
298 someone can get something working. Second, it makes it easier to change
299 things. In particular, if tables and other things are all emitted
301 update all of the targets to a new interface.</p>
303 </div>
305 <!-- *********************************************************************** -->
308 </div>
309 <!-- *********************************************************************** -->
313 <p>The LLVM target description classes (located in the
315 the target machine independent of any particular client. These classes are
317 instructions and registers it has), and do not incorporate any particular
318 pieces of code generation algorithms.</p>
320 <p>All of the target description classes (except the
322 subclassed by the concrete target implementation, and have virtual methods
323 implemented. To get to these implementations, the
325 that should be implemented by the target.</p>
327 </div>
329 <!-- ======================================================================= -->
332 </div>
337 access the target-specific implementations of the various target description
340 designed to be specialized by a concrete target implementation
342 methods. The only required target description class is
344 generator components are to be used, the other interfaces should be
345 implemented as well.</p>
347 </div>
349 <!-- ======================================================================= -->
352 </div>
357 and it is the only class that is not extensible (you cannot derived a new
359 target lays out memory for structures, the alignment requirements for various
360 data types, the size of pointers in the target, and whether the target is
361 little-endian or big-endian.</p>
363 </div>
365 <!-- ======================================================================= -->
368 </div>
373 selectors primarily to describe how LLVM code should be lowered to
374 SelectionDAG operations. Among other things, this class indicates:</p>
376 <ul>
385 <li>various high-level characteristics, like whether it is profitable to turn
386 division by a constant into a multiplication sequence</li>
387 </ul>
389 </div>
391 <!-- ======================================================================= -->
394 </div>
399 of the target and any interactions between the registers.</p>
401 <p>Registers in the code generator are represented in the code generator by
402 unsigned integers. Physical registers (those that actually exist in the
403 target description) are unique small numbers, and virtual registers are
406 <p>Each register in the processor description has an associated
408 register (used for assembly output and debugging dumps) and a set of aliases
409 (used to indicate whether one register overlaps with another).</p>
412 class exposes a set of processor specific register classes (instances of the
414 registers that have the same properties (for example, they are all 32-bit
415 integer registers). Each SSA virtual register created by the instruction
416 selector has an associated register class. When the register allocator runs,
417 it replaces virtual registers with a physical register in the set.</p>
419 <p>The target-specific implementations of these classes is auto-generated from
421 register file.</p>
423 </div>
425 <!-- ======================================================================= -->
428 </div>
433 instructions supported by the target. It is essentially an array of
435 instruction the target supports. Descriptors define things like the mnemonic
436 for the opcode, the number of operands, the list of implicit register uses
437 and defs, whether the instruction has certain target-independent properties
438 (accesses memory, is commutable, etc), and holds any target-specific
439 flags.</p>
441 </div>
443 <!-- ======================================================================= -->
446 </div>
451 stack frame layout of the target. It holds the direction of stack growth, the
452 known stack alignment on entry to each function, and the offset to the local
453 area. The offset to the local area is the offset from the stack pointer on
454 function entry to the first location where function data (local variables,
455 spill locations) can be stored.</p>
457 </div>
459 <!-- ======================================================================= -->
462 </div>
467 specific chip set being targeted. A sub-target informs code generation of
468 which instructions are supported, instruction latencies and instruction
469 execution itinerary; i.e., which processing units are used, in what order,
470 and for how long.</p>
472 </div>
475 <!-- ======================================================================= -->
478 </div>
483 Just-In-Time code generator to perform target-specific activities, such as
486 method.</p>
488 </div>
490 <!-- *********************************************************************** -->
493 </div>
494 <!-- *********************************************************************** -->
498 <p>At the high-level, LLVM code is translated to a machine specific
499 representation formed out of
504 agnostic, representing instructions in their most abstract form: an opcode
505 and a series of operands. This representation is designed to support both an
506 SSA representation for machine code, as well as a register allocated, non-SSA
507 form.</p>
509 </div>
511 <!-- ======================================================================= -->
514 </div>
518 <p>Target machine instructions are represented as instances of the
520 representing machine instructions. In particular, it only keeps track of an
521 opcode number and a set of operands.</p>
523 <p>The opcode number is a simple unsigned integer that only has meaning to a
524 specific backend. All of the instructions for a target should be defined in
527 not have any information about how to interpret the instruction (i.e., what
528 the semantics of the instruction are); for that you must refer to the
531 <p>The operands of a machine instruction can be of several different types: a
532 register reference, a constant integer, a basic block reference, etc. In
533 addition, a machine operand should be marked as a def or a use of the value
534 (though only registers are allowed to be defs).</p>
536 <p>By convention, the LLVM code generator orders instruction operands so that
537 all register definitions come before the register uses, even on architectures
538 that are normally printed in other orders. For example, the SPARC add
540 and stores the result into the "%i3" register. In the LLVM code generator,
541 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
542 destination first.</p>
544 <p>Keeping destination (definition) operands at the beginning of the operand
545 list has several advantages. In particular, the debugging printer will print
546 the instruction like this:</p>
549 <pre>
550 %r3 = add %i1, %i2
551 </pre>
552 </div>
557 </div>
559 <!-- _______________________________________________________________________ -->
562 </div>
572 <pre>
574 // instruction. The '1' specifies how many operands will be added.
577 // Create the same instr, but insert it at the end of a basic block.
578 MachineBasicBlock &MBB = ...
581 // Create the same instr, but insert it before a specified iterator point.
582 MachineBasicBlock::iterator MBBI = ...
585 // Create a 'cmp Reg, 0' instruction, no destination reg.
587 // Create an 'sahf' instruction which takes no operands and stores nothing.
588 MI = BuildMI(X86::SAHF, 0);
590 // Create a self looping branch instruction.
592 </pre>
593 </div>
596 have to specify the number of operands that the machine instruction will
597 take. This allows for efficient memory allocation. You also need to specify
598 if operands default to be uses of values, not definitions. If you need to
599 add a definition operand (other than the optional destination register), you
600 must explicitly mark it as such:</p>
603 <pre>
604 MI.addReg(Reg, RegState::Define);
605 </pre>
606 </div>
608 </div>
610 <!-- _______________________________________________________________________ -->
613 </div>
617 <p>One important issue that the code generator needs to be aware of is the
618 presence of fixed registers. In particular, there are often places in the
620 particular value to be in a particular register. This can occur due to
621 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
623 calling conventions. In any case, the instruction selector should emit code
624 that copies a virtual register into or out of a physical register when
625 needed.</p>
630 <pre>
631 define i32 @test(i32 %X, i32 %Y) {
632 %Z = udiv i32 %X, %Y
633 ret i32 %Z
634 }
635 </pre>
636 </div>
640 get this):</p>
643 <pre>
644 ;; Start of div
645 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
646 %reg1027 = sar %reg1024, 31
647 %EDX = mov %reg1027 ;; Sign extend X into EDX
648 idiv %reg1025 ;; Divide by Y (in reg1025)
649 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
651 ;; Start of ret
652 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
653 ret
654 </pre>
655 </div>
657 <p>By the end of code generation, the register allocator has coalesced the
658 registers and deleted the resultant identity moves producing the following
659 code:</p>
662 <pre>
663 ;; X is in EAX, Y is in ECX
664 mov %EAX, %EDX
665 sar %EDX, 31
666 idiv %ECX
667 ret
668 </pre>
669 </div>
671 <p>This approach is extremely general (if it can handle the X86 architecture, it
672 can handle anything!) and allows all of the target specific knowledge about
673 the instruction stream to be isolated in the instruction selector. Note that
674 physical registers should have a short lifetime for good code generation, and
675 all physical registers are assumed dead on entry to and exit from basic
676 blocks (before register allocation). Thus, if you need a value to be live
678 register.</p>
680 </div>
682 <!-- _______________________________________________________________________ -->
685 </div>
690 maintained in SSA-form until register allocation happens. For the most part,
691 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
692 become machine code PHI nodes, and virtual registers are only allowed to have
693 a single definition.</p>
695 <p>After register allocation, machine code is no longer in SSA-form because
696 there are no virtual registers left in the code.</p>
698 </div>
700 <!-- ======================================================================= -->
703 </div>
709 corresponds to the LLVM code input to the instruction selector, but there can
710 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
712 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
713 comes from.</p>
715 </div>
717 <!-- ======================================================================= -->
720 </div>
726 corresponds one-to-one with the LLVM function input to the instruction
727 selector. In addition to a list of basic blocks,
733 </div>
735 <!-- *********************************************************************** -->
738 </div>
739 <!-- *********************************************************************** -->
743 <p>This section documents the phases described in the
745 It explains how they work and some of the rationale behind their design.</p>
747 </div>
749 <!-- ======================================================================= -->
752 </div>
756 <p>Instruction Selection is the process of translating LLVM code presented to
757 the code generator into target-specific machine instructions. There are
758 several well-known ways to do this in the literature. LLVM uses a
759 SelectionDAG based instruction selector.</p>
761 <p>Portions of the DAG instruction selector are generated from the target
764 there are still things that require custom C++ code.</p>
766 </div>
768 <!-- _______________________________________________________________________ -->
771 </div>
775 <p>The SelectionDAG provides an abstraction for code representation in a way
776 that is amenable to instruction selection using automatic techniques
777 (e.g. dynamic-programming based optimal pattern matching selectors). It is
778 also well-suited to other phases of code generation; in particular,
779 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
780 post-selection). Additionally, the SelectionDAG provides a host
781 representation where a large variety of very-low-level (but
783 performed; ones which require extensive information about the instructions
784 efficiently supported by the target.</p>
786 <p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
788 operation code (Opcode) that indicates what operation the node performs and
789 the operands to the operation. The various operation node types are
791 file.</p>
793 <p>Although most operations define a single value, each node in the graph may
794 define multiple values. For example, a combined div/rem operation will
795 define both the dividend and the remainder. Many other situations require
796 multiple values as well. Each node also has some number of operands, which
797 are edges to the node defining the used value. Because nodes may define
800 and result value being used, respectively. Each value produced by
802 indicating what the type of the value is.</p>
804 <p>SelectionDAGs contain two different kinds of values: those that represent
805 data flow and those that represent control flow dependencies. Data values
806 are simple edges with an integer or floating point value type. Control edges
808 These edges provide an ordering between nodes that have side effects (such as
809 loads, stores, calls, returns, etc). All nodes that have side effects should
810 take a token chain as input and produce a new one as output. By convention,
811 token chain inputs are always operand #0, and chain results are always the
812 last value produced by an operation.</p>
816 node is the final side-effecting node in the token chain. For example, in a
817 single basic block function it would be the return node.</p>
820 "illegal" DAG. A legal DAG for a target is one that only uses supported
821 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
822 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
823 uses a SREM or UREM operation. The
826 responsible for turning an illegal DAG into a legal DAG.</p>
828 </div>
830 <!-- _______________________________________________________________________ -->
833 </div>
839 <ol>
841 performs a simple translation from the input LLVM code to an illegal
842 SelectionDAG.</li>
845 stage performs simple optimizations on the SelectionDAG to simplify it,
846 and recognize meta instructions (like rotates
848 operations. This makes the resultant code more efficient and
850 (below) simpler.</li>
853 — This stage transforms SelectionDAG nodes to eliminate any types
854 that are unsupported on the target.</li>
857 SelectionDAG optimizer is run to clean up redundancies exposed by type
858 legalization.</li>
861 This stage transforms SelectionDAG nodes to eliminate any types that are
862 unsupported on the target.</li>
865 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
866 operation legalization.</li>
869 Finally, the target instruction selector matches the DAG operations to
870 target instructions. This process translates the target-independent input
871 DAG into another DAG of target instructions.</li>
874 — The last phase assigns a linear order to the instructions in the
875 target-instruction DAG and emits them into the MachineFunction being
876 compiled. This step uses traditional prepass scheduling techniques.</li>
877 </ol>
879 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
880 rest of the code generation passes are run.</p>
882 <p>One great way to visualize what is going on here is to take advantage of a
883 few LLC command line options. The following options pop up a window
884 displaying the SelectionDAG at specific times (if you only get errors printed
885 to the console while using this, you probably
887 to add support for it).</p>
889 <ul>
891 before the first optimization pass.</li>
896 optimization pass.</li>
901 </ul>
904 This graph is based on the final SelectionDAG, with nodes that must be
905 scheduled together bundled into a single scheduling-unit node, and with
906 immediate operands and other nodes that aren't relevant for scheduling
907 omitted.</p>
909 </div>
911 <!-- _______________________________________________________________________ -->
914 </div>
921 this pass is to expose as much low-level, target-specific details to the
922 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
925 requires target-specific hooks to lower calls, returns, varargs, etc. For
927 interface is used.</p>
929 </div>
931 <!-- _______________________________________________________________________ -->
934 </div>
938 <p>The Legalize phase is in charge of converting a DAG to only use the types
939 that are natively supported by the target.</p>
941 <p>There are two main ways of converting values of unsupported scalar types to
942 values of supported types: converting small types to larger types
943 ("promoting"), and breaking up large integer types into smaller ones
944 ("expanding"). For example, a target might require that all f32 values are
945 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
946 target might require that all i64 values be expanded into pairs of i32
947 values. These changes can insert sign and zero extensions as needed to make
948 sure that the final code has the same behavior as the input.</p>
950 <p>There are two main ways of converting values of unsupported vector types to
951 value of supported types: splitting vector types, multiple times if
952 necessary, until a legal type is found, and extending vector types by adding
953 elements to the end to round them out to legal types ("widening"). If a
954 vector gets split all the way down to single-element parts with no supported
955 vector type being found, the elements are converted to scalars
958 <p>A target implementation tells the legalizer which types are supported (and
959 which register class to use for them) by calling the
962 </div>
964 <!-- _______________________________________________________________________ -->
967 </div>
971 <p>The Legalize phase is in charge of converting a DAG to only use the
972 operations that are natively supported by the target.</p>
974 <p>Targets often have weird constraints, such as not supporting every operation
975 on every supported datatype (e.g. X86 does not support byte conditional moves
976 and PowerPC does not support sign-extending loads from a 16-bit memory
977 location). Legalize takes care of this by open-coding another sequence of
978 operations to emulate the operation ("expansion"), by promoting one type to a
979 larger type that supports the operation ("promotion"), or by using a
982 <p>A target implementation tells the legalizer which operations are not
983 supported (and which of the above three actions to take) by calling the
985 constructor.</p>
987 <p>Prior to the existence of the Legalize passes, we required that every target
989 operator and type even if they are not natively supported. The introduction
990 of the Legalize phases allows all of the canonicalization patterns to be
991 shared across targets, and makes it very easy to optimize the canonicalized
992 code because it is still in the form of a DAG.</p>
994 </div>
996 <!-- _______________________________________________________________________ -->
999 Combiner</a>
1000 </div>
1004 <p>The SelectionDAG optimization phase is run multiple times for code
1005 generation, immediately after the DAG is built and once after each
1006 legalization. The first run of the pass allows the initial code to be
1007 cleaned up (e.g. performing optimizations that depend on knowing that the
1008 operators have restricted type inputs). Subsequent runs of the pass clean up
1009 the messy code generated by the Legalize passes, which allows Legalize to be
1010 very simple (it can focus on making code legal instead of focusing on
1013 <p>One important class of optimizations performed is optimizing inserted sign
1014 and zero extension instructions. We currently use ad-hoc techniques, but
1015 could move to more rigorous techniques in the future. Here are some good
1016 papers on the subject:</p>
1020 Kevin Redwine and Norman Ramsey<br>
1025 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1026 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1027 and Implementation.</p>
1029 </div>
1031 <!-- _______________________________________________________________________ -->
1034 </div>
1038 <p>The Select phase is the bulk of the target-specific code for instruction
1039 selection. This phase takes a legal SelectionDAG as input, pattern matches
1040 the instructions supported by the target to this DAG, and produces a new DAG
1041 of target code. For example, consider the following LLVM fragment:</p>
1044 <pre>
1045 %t1 = fadd float %W, %X
1046 %t2 = fmul float %t1, %Y
1047 %t3 = fadd float %t2, %Z
1048 </pre>
1049 </div>
1051 <p>This LLVM code corresponds to a SelectionDAG that looks basically like
1052 this:</p>
1055 <pre>
1056 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
1057 </pre>
1058 </div>
1060 <p>If a target supports floating point multiply-and-add (FMA) operations, one of
1061 the adds can be merged with the multiply. On the PowerPC, for example, the
1062 output of the instruction selector might look like this DAG:</p>
1065 <pre>
1066 (FMADDS (FADDS W, X), Y, Z)
1067 </pre>
1068 </div>
1071 first two operands and adds the third (as single-precision floating-point
1073 add instruction. To perform this pattern match, the PowerPC backend includes
1074 the following instruction definitions:</p>
1077 <pre>
1079 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1080 "fmadds $FRT, $FRA, $FRC, $FRB",
1081 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1084 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1085 "fadds $FRT, $FRA, $FRB",
1087 </pre>
1088 </div>
1090 <p>The portion of the instruction definition in bold indicates the pattern used
1091 to match the instruction. The DAG operators
1096 <p>The TableGen DAG instruction selector generator reads the instruction
1098 pattern matching code for your target. It has the following strengths:</p>
1100 <ul>
1101 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1102 you if your patterns make sense or not.</li>
1104 <li>It can handle arbitrary constraints on operands for the pattern match. In
1105 particular, it is straight-forward to say things like "match any immediate
1106 that is a 13-bit sign-extended value". For examples, see the
1108 backend.</li>
1110 <li>It knows several important identities for the patterns defined. For
1111 example, it knows that addition is commutative, so it allows the
1113 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1114 to specially handle this case.</li>
1116 <li>It has a full-featured type-inferencing system. In particular, you should
1117 rarely have to explicitly tell the system what type parts of your patterns
1120 It was able to infer and propagate this knowledge from the fact that
1124 Pattern fragments are chunks of reusable patterns that get inlined into
1125 your patterns during compiler-compiler time. For example, the integer
1126 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1127 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1129 short-hand fragments as they see fit. See the definition of
1132 <li>In addition to instructions, targets can specify arbitrary patterns that
1133 map to one or more instructions using the 'Pat' class. For example, the
1134 PowerPC has no way to load an arbitrary integer immediate into a register
1135 in one instruction. To tell tblgen how to do this, it defines:
1136 <br>
1137 <br>
1139 <pre>
1140 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1141 def : Pat<(i32 imm:$imm),
1142 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1143 </pre>
1144 </div>
1145 <br>
1146 If none of the single-instruction patterns for loading an immediate into a
1147 register match, this will be used. This rule says "match an arbitrary i32
1148 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1149 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1150 the left 16 bits') instruction". To make this work, the
1152 the input immediate (in this case, take the high or low 16-bits of the
1153 immediate).</li>
1155 <li>While the system does automate a lot, it still allows you to write custom
1156 C++ code to match special cases if there is something that is hard to
1157 express.</li>
1158 </ul>
1160 <p>While it has many strengths, the system currently has some limitations,
1161 primarily because it is a work in progress and is not yet finished:</p>
1163 <ul>
1164 <li>Overall, there is no way to define or match SelectionDAG nodes that define
1166 etc). This is the biggest reason that you currently still <em>have
1169 <li>There is no great way to support matching complex addressing modes yet.
1170 In the future, we will extend pattern fragments to allow them to define
1172 addressing mode</a>, which are currently matched with custom C++ code).
1173 In addition, we'll extend fragments so that a fragment can match multiple
1174 different patterns.</li>
1178 <li>We don't automatically generate the set of supported registers and
1180 yet.</li>
1183 </ul>
1185 <p>Despite these limitations, the instruction selector generator is still quite
1186 useful for most of the binary and logical operations in typical instruction
1187 sets. If you run into any problems or can't figure out how to do something,
1188 please let Chris know!</p>
1190 </div>
1192 <!-- _______________________________________________________________________ -->
1195 </div>
1199 <p>The scheduling phase takes the DAG of target instructions from the selection
1200 phase and assigns an order. The scheduler can pick an order depending on
1201 various constraints of the machines (i.e. order for minimal register pressure
1202 or try to cover instruction latencies). Once an order is established, the
1203 DAG is converted to a list
1205 destroyed.</p>
1207 <p>Note that this phase is logically separate from the instruction selection
1208 phase, but is tied to it closely in the code because it operates on
1209 SelectionDAGs.</p>
1211 </div>
1213 <!-- _______________________________________________________________________ -->
1216 </div>
1220 <ol>
1224 </ol>
1226 </div>
1228 <!-- ======================================================================= -->
1231 </div>
1234 <!-- ======================================================================= -->
1237 </div>
1243 determine if two or more virtual registers which require the same physical
1244 register are live at the same point in the program (i.e., they conflict).
1247 </div>
1249 <!-- _______________________________________________________________________ -->
1252 </div>
1256 <p>The first step in determining the live intervals of variables is to calculate
1257 the set of registers that are immediately dead after the instruction (i.e.,
1258 the instruction calculates the value, but it is never used) and the set of
1259 registers that are used by the instruction, but are never used after the
1260 instruction (i.e., they are killed). Live variable information is computed
1262 register in the function. This is done in a very efficient manner because it
1263 uses SSA to sparsely compute lifetime information for virtual registers
1264 (which are in SSA form) and only has to track physical registers within a
1265 block. Before register allocation, LLVM can assume that physical registers
1266 are only live within a single basic block. This allows it to do a single,
1267 local analysis to resolve physical register lifetimes within each basic
1268 block. If a physical register is not register allocatable (e.g., a stack
1269 pointer or condition codes), it is not tracked.</p>
1271 <p>Physical registers may be live in to or out of a function. Live in values are
1272 typically arguments in registers. Live out values are typically return values
1273 in registers. Live in values are marked as such, and are given a dummy
1274 "defining" instruction during live intervals analysis. If the last basic
1276 out values in the function.</p>
1279 the live variable information from a depth first traversal of the CFG of the
1282 only the definition is handled, because the uses will be handled in other
1283 basic blocks.</p>
1286 assignment at the end of the current basic block and traverse the successor
1290 of its predecessor basic blocks, until the basic block with the defining
1291 instruction is encountered.</p>
1293 </div>
1295 <!-- _______________________________________________________________________ -->
1298 </div>
1302 <p>We now have the information available to perform the live intervals analysis
1303 and build the live intervals themselves. We start off by numbering the basic
1304 blocks and machine instructions. We then handle the "live-in" values. These
1305 are in physical registers, so the physical register is assumed to be killed
1306 by the end of the basic block. Live intervals for virtual registers are
1313 </div>
1315 <!-- ======================================================================= -->
1318 </div>
1325 number of physical registers. Each target architecture has a different number
1326 of physical registers. If the number of physical registers is not enough to
1327 accommodate all the virtual registers, some of them will have to be mapped
1330 </div>
1332 <!-- _______________________________________________________________________ -->
1336 </div>
1340 <p>In LLVM, physical registers are denoted by integer numbers that normally
1343 architecture. For instance, by
1348 <p>Some architectures contain registers that share the same physical location. A
1349 notable example is the X86 platform. For instance, in the X86 architecture,
1352 particular architecture, you can check which registers are aliased by
1358 Elements in the same register class are functionally equivalent, and can be
1359 interchangeably used. Each virtual register can only be mapped to physical
1360 registers of a particular class. For instance, in the X86 architecture, some
1361 virtuals can only be allocated to 8 bit registers. A register class is
1363 register is compatible with a given physical, this code can be used:</p>
1366 <pre>
1367 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1368 unsigned v_reg,
1369 unsigned p_reg) {
1370 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
1371 "Target register must be physical");
1372 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1373 return trc->contains(p_reg);
1374 }
1375 </pre>
1376 </div>
1378 <p>Sometimes, mostly for debugging purposes, it is useful to change the number
1379 of physical registers available in the target architecture. This must be done
1382 registers. Just commenting some out is one simple way to avoid them being
1383 used. A more polite way is to explicitly exclude some registers from
1386 </p>
1388 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
1389 registers, different virtual registers never share the same number. The
1390 smallest virtual register is normally assigned the number 1024. This may
1391 change, so, in order to know which is the first virtual register, you should
1393 number is greater than or equal
1395 register. Whereas physical registers are statically defined in
1397 application developer, that is not the case with virtual registers. In order
1398 to create new virtual registers, use the
1400 will return a virtual register with the highest code.</p>
1402 <p>Before register allocation, the operands of an instruction are mostly virtual
1403 registers, although physical registers may also be used. In order to check if
1404 a given machine operand is a register, use the boolean
1410 register is being used by the instruction. The
1412 defined.</p>
1414 <p>We will call physical registers present in the LLVM bitcode before register
1416 many different situations, for instance, to pass parameters of functions
1417 calls, and to store results of particular instructions. There are two types
1420 operands, and can be accessed
1422 which registers are implicitly defined by an instruction, use
1425 difference between explicit and implicit physical registers is that the
1426 latter are defined statically for each instruction, whereas the former may
1427 vary depending on the program being compiled. For example, an instruction
1428 that represents a function call will always implicitly define or use the same
1429 set of physical registers. To read the registers implicitly used by an
1430 instruction,
1432 registers impose constraints on any register allocation algorithm. The
1433 register allocator must make sure that none of them are overwritten by
1434 the values of virtual registers while still alive.</p>
1436 </div>
1438 <!-- _______________________________________________________________________ -->
1442 </div>
1446 <p>There are two ways to map virtual registers to physical registers (or to
1451 and stores sending and getting values to and from memory.</p>
1453 <p>The direct mapping provides more flexibility to the developer of the register
1454 allocator; however, it is more error prone, and demands more implementation
1455 work. Basically, the programmer will have to specify where load and store
1456 instructions should be inserted in the target function being compiled in
1457 order to get and store values in memory. To assign a physical register to a
1458 virtual register present in a given operand,
1463 <p>The indirect mapping shields the application developer from the complexities
1464 of inserting load and store instructions. In order to map a virtual register
1466 order to map a certain virtual register to memory,
1469 necessary to map another virtual register to the same stack slot,
1471 important point to consider when using the indirect mapping, is that even if
1472 a virtual register is mapped to memory, it still needs to be mapped to a
1473 physical register. This physical register is the location where the virtual
1474 register is supposed to be found before being stored or after being
1475 reloaded.</p>
1477 <p>If the indirect strategy is used, after all the virtual registers have been
1478 mapped to physical registers or stack slots, it is necessary to use a spiller
1479 object to place load and store instructions in the code. Every virtual that
1480 has been mapped to a stack slot will be stored to memory after been defined
1481 and will be loaded before being used. The implementation of the spiller tries
1482 to recycle load/store instructions, avoiding unnecessary instructions. For an
1483 example of how to invoke the spiller,
1487 </div>
1489 <!-- _______________________________________________________________________ -->
1492 </div>
1496 <p>With very rare exceptions (e.g., function calls), the LLVM machine code
1497 instructions are three address instructions. That is, each instruction is
1498 expected to define at most one register, and to use at most two registers.
1499 However, some architectures use two address instructions. In this case, the
1500 defined register is also one of the used register. For instance, an
1504 <p>In order to produce correct code, LLVM must convert three address
1505 instructions that represent two address instructions into true two address
1507 this specific purpose. It must be run before register allocation takes
1508 place. After its execution, the resulting code may no longer be in SSA
1509 form. This happens, for instance, in situations where an instruction such
1513 <pre>
1514 %a = MOVE %b
1515 %a = ADD %a %c
1516 </pre>
1517 </div>
1519 <p>Notice that, internally, the second instruction is represented as
1521 used and defined by the instruction.</p>
1523 </div>
1525 <!-- _______________________________________________________________________ -->
1528 </div>
1532 <p>An important transformation that happens during register allocation is called
1534 that are performed on the control flow graph of programs. However,
1535 traditional instruction sets do not implement PHI instructions. Thus, in
1536 order to generate executable code, compilers must replace PHI instructions
1537 with other instructions that preserve their semantics.</p>
1539 <p>There are many ways in which PHI instructions can safely be removed from the
1540 target code. The most traditional PHI deconstruction algorithm replaces PHI
1541 instructions with copy instructions. That is the strategy adopted by
1542 LLVM. The SSA deconstruction algorithm is implemented
1545 of the register allocator.</p>
1547 </div>
1549 <!-- _______________________________________________________________________ -->
1552 </div>
1557 allocation that removes unnecessary copy instructions. For instance, a
1558 sequence of instructions such as:</p>
1561 <pre>
1562 %EBX = LOAD %mem_address
1563 %EAX = COPY %EBX
1564 </pre>
1565 </div>
1570 <pre>
1571 %EAX = LOAD %mem_address
1572 </pre>
1573 </div>
1575 <p>Instructions can be folded with
1577 taken when folding instructions; a folded instruction can be quite different
1578 from the original
1581 use.</p>
1583 </div>
1585 <!-- _______________________________________________________________________ -->
1589 </div>
1593 <p>The LLVM infrastructure provides the application developer with three
1594 different register allocators:</p>
1596 <ul>
1598 well-know linear scan register allocator. Whereas the
1601 uses a spiller in order to place load and stores.</li>
1604 builds. It allocates registers on a basic block level, attempting to keep
1605 values in registers and reusing registers as appropriate.</li>
1608 based register allocator. This allocator works by constructing a PBQP
1609 problem representing the register allocation problem under consideration,
1610 solving this using a PBQP solver, and mapping the solution back to a
1611 register assignment.</li>
1613 </ul>
1619 <pre>
1620 $ llc -regalloc=linearscan file.bc -o ln.s;
1621 $ llc -regalloc=fast file.bc -o fa.s;
1622 $ llc -regalloc=pbqp file.bc -o pbqp.s;
1623 </pre>
1624 </div>
1626 </div>
1628 <!-- ======================================================================= -->
1631 </div>
1633 <!-- ======================================================================= -->
1636 </div>
1638 <!-- ======================================================================= -->
1641 </div>
1643 <!-- _______________________________________________________________________ -->
1646 </div>
1648 <!-- _______________________________________________________________________ -->
1651 </div>
1655 </div>
1658 <!-- *********************************************************************** -->
1661 </div>
1662 <!-- *********************************************************************** -->
1666 <p>This section of the document explains features or design decisions that are
1667 specific to the code generator for a particular target.</p>
1669 </div>
1671 <!-- ======================================================================= -->
1674 </div>
1678 <p>Tail call optimization, callee reusing the stack of the caller, is currently
1681 <ul>
1685 <li>The call is a tail call - in tail position (ret immediately follows call
1686 and ret uses value of call or is void).</li>
1691 </ul>
1695 <ul>
1699 = hidden or protected) are supported.</li>
1700 </ul>
1704 <ul>
1709 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
1710 </ul>
1717 <pre>
1718 declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
1720 define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
1721 %l1 = add i32 %in1, %in2
1722 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
1723 ret i32 %tmp
1724 }
1725 </pre>
1726 </div>
1730 <p>To support tail call optimization in situations where the callee has more
1731 arguments than the caller a 'callee pops arguments' convention is used. This
1733 (because one or more of above constraints are not met) to be followed by a
1734 readjustment of the stack. So performance might be worse in such cases.</p>
1736 </div>
1737 <!-- ======================================================================= -->
1740 </div>
1744 <p>Sibling call optimization is a restricted form of tail call optimization.
1745 Unlike tail call optimization described in the previous section, it can be
1747 is not specified.</p>
1750 following constraints are met:</p>
1752 <ul>
1753 <li>Caller and callee have the same calling convention. It can be either
1756 <li>The call is a tail call - in tail position (ret immediately follows call
1757 and ret uses value of call or is void).</li>
1759 <li>Caller and callee have matching return type or the callee result is not
1760 used.
1762 <li>If any of the callee arguments are being passed in stack, they must be
1763 available in caller's own incoming argument stack and the frame offsets
1764 must be the same.
1765 </ul>
1769 <pre>
1770 declare i32 @bar(i32, i32)
1772 define i32 @foo(i32 %a, i32 %b, i32 %c) {
1773 entry:
1774 %0 = tail call i32 @bar(i32 %a, i32 %b)
1775 ret i32 %0
1776 }
1777 </pre>
1778 </div>
1780 </div>
1781 <!-- ======================================================================= -->
1784 </div>
1790 processors, and includes support for ISA extensions such as MMX and SSE.</p>
1792 </div>
1794 <!-- _______________________________________________________________________ -->
1797 </div>
1801 <p>The following are the known target triples that are supported by the X86
1802 backend. This is not an exhaustive list, and it would be useful to add those
1803 that people test.</p>
1805 <ul>
1819 </ul>
1821 </div>
1823 <!-- _______________________________________________________________________ -->
1826 </div>
1833 <ul>
1839 </ul>
1841 </div>
1843 <!-- _______________________________________________________________________ -->
1846 </div>
1850 <p>The x86 has a very flexible way of accessing memory. It is capable of
1851 forming memory addresses of the following expression directly in integer
1852 instructions (which use ModR/M addressing):</p>
1855 <pre>
1857 </pre>
1858 </div>
1861 memory operand of this form. This means that the "load" form of
1865 <pre>
1867 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
1868 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
1869 </pre>
1870 </div>
1872 <p>Stores, and all other instructions, treat the four memory operands in the
1873 same way and in the same order. If the segment register is unspecified
1875 have a segment register specified, so they only have 4 operands for their
1876 memory reference.</p>
1878 </div>
1880 <!-- _______________________________________________________________________ -->
1883 </div>
1887 <p>x86 has an experimental feature which provides
1888 the ability to perform loads and stores to different address spaces
1889 via the x86 segment registers. A segment override prefix byte on an
1890 instruction causes the instruction's memory access to go to the specified
1891 segment. LLVM address space 0 is the default address space, which includes
1892 the stack, and any unqualified memory accesses in a program. Address spaces
1894 represented by address space 256, while the FS-segment is represented by
1895 address space 257. Other x86 segments have yet to be allocated address space
1896 numbers.</p>
1898 <p>While these address spaces may seem similar to TLS via the
1900 there are some fundamental differences.</p>
1903 specifies that they are to be allocated in thread-local memory. There are
1904 no type qualifiers involved, and these variables can be pointed to with
1905 normal pointers and accessed with normal loads and stores.
1907 level (though LLVM doesn't yet have implementations of it for some
1908 configurations).<p>
1910 <p>Special address spaces, in contrast, apply to static types. Every
1911 load and store has a particular address space in its address operand type,
1912 and this is what determines which address space is accessed.
1913 LLVM ignores these special address space qualifiers on global variables,
1914 and does not provide a way to directly allocate storage in them.
1915 At the LLVM IR level, the behavior of these special address spaces depends
1916 in part on the underlying OS or runtime environment, and they are specific
1917 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
1919 <p>Some operating systems and runtime environments use (or may in the future
1920 use) the FS/GS-segment registers for various low-level purposes, so care
1921 should be taken when considering them.</p>
1923 </div>
1925 <!-- _______________________________________________________________________ -->
1928 </div>
1932 <p>An instruction name consists of the base name, a default operand size, and a
1933 a character per operand with an optional special size. For example:</p>
1936 <pre>
1941 </pre>
1942 </div>
1944 </div>
1946 <!-- ======================================================================= -->
1949 </div>
1953 <p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1955 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
1957 </div>
1959 <!-- _______________________________________________________________________ -->
1962 </div>
1966 <p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1967 relative (PIC) or static addressing for accessing global values, so no TOC
1968 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
1969 of a stack frame. LLVM takes advantage of having no TOC to provide space to
1970 save the frame pointer in the PowerPC linkage area of the caller frame.
1971 Other details of PowerPC ABI can be found at <a href=
1972 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1975 for system use.</p>
1977 </div>
1979 <!-- _______________________________________________________________________ -->
1982 </div>
1986 <p>The size of a PowerPC frame is usually fixed for the duration of a
1987 function's invocation. Since the frame is fixed size, all references
1988 into the frame can be accessed via fixed offsets from the stack pointer. The
1989 exception to this is when dynamic alloca or variable sized arrays are
1990 present, then a base pointer (r31) is used as a proxy for the stack pointer
1991 and stack pointer is free to grow or shrink. A base pointer is also used if
1992 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
1993 always aligned to 16 bytes, so that space allocated for altivec vectors will
1994 be properly aligned.</p>
1999 <tr>
2001 </tr>
2002 <tr>
2004 </tr>
2005 <tr>
2007 </tr>
2008 <tr>
2010 </tr>
2011 <tr>
2013 </tr>
2015 <td><br></td>
2016 </tr>
2017 <tr>
2019 </tr>
2020 </table>
2023 to allocating its own frame. Only three entries are relevant to LLVM. The
2024 first entry is the previous stack pointer (sp), aka link. This allows
2025 probing tools like gdb or exception handlers to quickly scan the frames in
2026 the stack. A function epilog can also use the link to pop the frame from the
2027 stack. The third entry in the linkage area is used to save the return
2028 address from the lr register. Finally, as mentioned above, the last entry is
2029 used to save the previous frame pointer (r31.) The entries in the linkage
2036 <tr>
2039 </tr>
2040 <tr>
2043 </tr>
2044 <tr>
2047 </tr>
2048 <tr>
2051 </tr>
2052 <tr>
2055 </tr>
2056 <tr>
2059 </tr>
2060 </table>
2065 <tr>
2068 </tr>
2069 <tr>
2072 </tr>
2073 <tr>
2076 </tr>
2077 <tr>
2080 </tr>
2081 <tr>
2084 </tr>
2085 <tr>
2088 </tr>
2089 </table>
2092 function. Following the PowerPC ABI, the first few arguments are actually
2093 passed in registers, with the space in the parameter area unused. However,
2094 if there are not enough registers or the callee is a thunk or vararg
2095 function, these register arguments can be spilled into the parameter area.
2096 Thus, the parameter area must be large enough to store all the parameters for
2097 the largest call sequence made by the caller. The size must also be
2098 minimally large enough to spill registers r3-r10. This allows callees blind
2099 to the call signature, such as thunks and vararg functions, enough space to
2100 cache the argument registers. Therefore, the parameter area is minimally 32
2102 a fixed offset from the top of the frame, that a callee can access its spilt
2103 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
2105 <p>Combining the information about the linkage, parameter areas and alignment. A
2107 mode.</p>
2110 alloca then space is added to the stack, the linkage and parameter areas are
2111 shifted to top of stack, and the new space is available immediately below the
2112 linkage and parameter areas. The cost of shifting the linkage and parameter
2113 areas is minor since only the link value needs to be copied. The link value
2114 can be easily fetched by adding the original frame size to the base pointer.
2115 Note that allocations in the dynamic space need to observe 16 byte
2116 alignment.</p>
2119 variables.</p>
2122 saved registers on entry to the callee.</p>
2124 </div>
2126 <!-- _______________________________________________________________________ -->
2129 </div>
2133 <p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
2134 the following exceptions. Callee saved registers are spilled after the frame
2135 is created. This allows the llvm epilog/prolog support to be common with
2136 other targets. The base pointer callee saved register r31 is saved in the
2137 TOC slot of linkage area. This simplifies allocation of space for the base
2138 pointer and makes it convenient to locate programatically and during
2139 debugging.</p>
2141 </div>
2143 <!-- _______________________________________________________________________ -->
2146 </div>
2152 </div>
2155 <!-- *********************************************************************** -->
2156 <hr>
2157 <address>
2165 Last modified: $Date$
2166 </address>
2168 </body>
2169 </html>