lib/Target/Blackfin/BlackfinISelLowering.cpp

   1 //===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the interfaces that Blackfin uses to lower LLVM code
  11 // into a selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "BlackfinISelLowering.h"
  16 #include "BlackfinTargetMachine.h"
  17 #include "llvm/Function.h"
  18 #include "llvm/CodeGen/CallingConvLower.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineInstrBuilder.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/CodeGen/PseudoSourceValue.h"
  24 #include "llvm/CodeGen/SelectionDAG.h"
  25 #include "llvm/Target/TargetLoweringObjectFile.h"
  26 #include "llvm/ADT/VectorExtras.h"
  27 #include "llvm/Support/Debug.h"
  28
  29 using namespace llvm;
  30
  31 //===----------------------------------------------------------------------===//
  32 // Calling Convention Implementation
  33 //===----------------------------------------------------------------------===//
  34
  35 #include "BlackfinGenCallingConv.inc"
  36
  37 //===----------------------------------------------------------------------===//
  38 // TargetLowering Implementation
  39 //===----------------------------------------------------------------------===//
  40
  41 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
  42   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
  43   setShiftAmountType(MVT::i16);
  44   setBooleanContents(ZeroOrOneBooleanContent);
  45   setStackPointerRegisterToSaveRestore(BF::SP);
  46   setIntDivIsCheap(false);
  47
  48   // Set up the legal register classes.
  49   addRegisterClass(MVT::i32, BF::DRegisterClass);
  50   addRegisterClass(MVT::i16, BF::D16RegisterClass);
  51
  52   computeRegisterProperties();
  53
  54   // Blackfin doesn't have i1 loads or stores
  55   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
  56   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  57   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  58
  59   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
  60   setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
  61
  62   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
  63   setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
  64   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
  65
  66   // i16 registers don't do much
  67   setOperationAction(ISD::AND,   MVT::i16, Promote);
  68   setOperationAction(ISD::OR,    MVT::i16, Promote);
  69   setOperationAction(ISD::XOR,   MVT::i16, Promote);
  70   setOperationAction(ISD::CTPOP, MVT::i16, Promote);
  71   // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
  72   // immediately.
  73   setOperationAction(ISD::CTLZ,  MVT::i16, Promote);
  74   setOperationAction(ISD::CTTZ,  MVT::i16, Promote);
  75   setOperationAction(ISD::SETCC, MVT::i16, Promote);
  76
  77   // Blackfin has no division
  78   setOperationAction(ISD::SDIV,    MVT::i16, Expand);
  79   setOperationAction(ISD::SDIV,    MVT::i32, Expand);
  80   setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
  81   setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
  82   setOperationAction(ISD::SREM,    MVT::i16, Expand);
  83   setOperationAction(ISD::SREM,    MVT::i32, Expand);
  84   setOperationAction(ISD::UDIV,    MVT::i16, Expand);
  85   setOperationAction(ISD::UDIV,    MVT::i32, Expand);
  86   setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
  87   setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
  88   setOperationAction(ISD::UREM,    MVT::i16, Expand);
  89   setOperationAction(ISD::UREM,    MVT::i32, Expand);
  90
  91   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  92   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
  93   setOperationAction(ISD::MULHU,     MVT::i32, Expand);
  94   setOperationAction(ISD::MULHS,     MVT::i32, Expand);
  95
  96   // No carry-in operations.
  97   setOperationAction(ISD::ADDE, MVT::i32, Custom);
  98   setOperationAction(ISD::SUBE, MVT::i32, Custom);
  99
 100   // Blackfin has no intrinsics for these particular operations.
 101   setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
 102   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 103
 104   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
 105   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
 106   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 107
 108   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 109
 110   // i32 has native CTPOP, but not CTLZ/CTTZ
 111   setOperationAction(ISD::CTLZ, MVT::i32, Expand);
 112   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
 113
 114   // We don't have line number support yet.
 115   setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
 116   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
 117   setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
 118   setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
 119   setOperationAction(ISD::DECLARE, MVT::Other, Expand);
 120
 121   // Use the default implementation.
 122   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
 123   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 124   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
 125   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 126 }
 127
 128 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
 129   switch (Opcode) {
 130   default: return 0;
 131   case BFISD::CALL:     return "BFISD::CALL";
 132   case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
 133   case BFISD::Wrapper:  return "BFISD::Wrapper";
 134   }
 135 }
 136
 137 MVT BlackfinTargetLowering::getSetCCResultType(MVT VT) const {
 138   // SETCC always sets the CC register. Technically that is an i1 register, but
 139   // that type is not legal, so we treat it as an i32 register.
 140   return MVT::i32;
 141 }
 142
 143 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
 144                                                    SelectionDAG &DAG) {
 145   DebugLoc DL = Op.getDebugLoc();
 146   GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 147
 148   Op = DAG.getTargetGlobalAddress(GV, MVT::i32);
 149   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 150 }
 151
 152 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
 153   DebugLoc DL = Op.getDebugLoc();
 154   int JTI = cast<JumpTableSDNode>(Op)->getIndex();
 155
 156   Op = DAG.getTargetJumpTable(JTI, MVT::i32);
 157   return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
 158 }
 159
 160 SDValue
 161 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
 162                                              unsigned CallConv, bool isVarArg,
 163                                             const SmallVectorImpl<ISD::InputArg>
 164                                                &Ins,
 165                                              DebugLoc dl, SelectionDAG &DAG,
 166                                              SmallVectorImpl<SDValue> &InVals) {
 167
 168   MachineFunction &MF = DAG.getMachineFunction();
 169   MachineFrameInfo *MFI = MF.getFrameInfo();
 170
 171   SmallVector<CCValAssign, 16> ArgLocs;
 172   CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
 173                  ArgLocs, *DAG.getContext());
 174   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 175   CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
 176
 177   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 178     CCValAssign &VA = ArgLocs[i];
 179
 180     if (VA.isRegLoc()) {
 181       MVT RegVT = VA.getLocVT();
 182       TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
 183         BF::PRegisterClass : BF::DRegisterClass;
 184       assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
 185       assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
 186
 187       unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
 188       MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
 189       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
 190
 191       // If this is an 8 or 16-bit value, it is really passed promoted to 32
 192       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
 193       // right size.
 194       if (VA.getLocInfo() == CCValAssign::SExt)
 195         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 196                                DAG.getValueType(VA.getValVT()));
 197       else if (VA.getLocInfo() == CCValAssign::ZExt)
 198         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 199                                DAG.getValueType(VA.getValVT()));
 200
 201       if (VA.getLocInfo() != CCValAssign::Full)
 202         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 203
 204       InVals.push_back(ArgValue);
 205     } else {
 206       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 207       unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8;
 208       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
 209       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 210       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
 211     }
 212   }
 213
 214   return Chain;
 215 }
 216
 217 SDValue
 218 BlackfinTargetLowering::LowerReturn(SDValue Chain,
 219                                     unsigned CallConv, bool isVarArg,
 220                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
 221                                     DebugLoc dl, SelectionDAG &DAG) {
 222
 223   // CCValAssign - represent the assignment of the return value to locations.
 224   SmallVector<CCValAssign, 16> RVLocs;
 225
 226   // CCState - Info about the registers and stack slot.
 227   CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
 228                  RVLocs, *DAG.getContext());
 229
 230   // Analize return values.
 231   CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
 232
 233   // If this is the first return lowered for this function, add the regs to the
 234   // liveout set for the function.
 235   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 236     for (unsigned i = 0; i != RVLocs.size(); ++i)
 237       DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 238   }
 239
 240   SDValue Flag;
 241
 242   // Copy the result values into the output registers.
 243   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 244     CCValAssign &VA = RVLocs[i];
 245     assert(VA.isRegLoc() && "Can only return in registers!");
 246     SDValue Opi = Outs[i].Val;
 247
 248     // Expand to i32 if necessary
 249     switch (VA.getLocInfo()) {
 250     default: llvm_unreachable("Unknown loc info!");
 251     case CCValAssign::Full: break;
 252     case CCValAssign::SExt:
 253       Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
 254       break;
 255     case CCValAssign::ZExt:
 256       Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
 257       break;
 258     case CCValAssign::AExt:
 259       Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
 260       break;
 261     }
 262     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
 263     // Guarantee that all emitted copies are stuck together with flags.
 264     Flag = Chain.getValue(1);
 265   }
 266
 267   if (Flag.getNode()) {
 268     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 269   } else {
 270     return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
 271   }
 272 }
 273
 274 SDValue
 275 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
 276                                   unsigned CallConv, bool isVarArg,
 277                                   bool isTailCall,
 278                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 279                                   const SmallVectorImpl<ISD::InputArg> &Ins,
 280                                   DebugLoc dl, SelectionDAG &DAG,
 281                                   SmallVectorImpl<SDValue> &InVals) {
 282
 283   // Analyze operands of the call, assigning locations to each operand.
 284   SmallVector<CCValAssign, 16> ArgLocs;
 285   CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
 286                  *DAG.getContext());
 287   CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
 288   CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
 289
 290   // Get the size of the outgoing arguments stack space requirement.
 291   unsigned ArgsSize = CCInfo.getNextStackOffset();
 292
 293   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
 294   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
 295   SmallVector<SDValue, 8> MemOpChains;
 296
 297   // Walk the register/memloc assignments, inserting copies/loads.
 298   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 299     CCValAssign &VA = ArgLocs[i];
 300     SDValue Arg = Outs[i].Val;
 301
 302     // Promote the value if needed.
 303     switch (VA.getLocInfo()) {
 304     default: llvm_unreachable("Unknown loc info!");
 305     case CCValAssign::Full: break;
 306     case CCValAssign::SExt:
 307       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 308       break;
 309     case CCValAssign::ZExt:
 310       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 311       break;
 312     case CCValAssign::AExt:
 313       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 314       break;
 315     }
 316
 317     // Arguments that can be passed on register must be kept at
 318     // RegsToPass vector
 319     if (VA.isRegLoc()) {
 320       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 321     } else {
 322       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
 323       int Offset = VA.getLocMemOffset();
 324       assert(Offset%4 == 0 && "Unaligned LocMemOffset");
 325       assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
 326       SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
 327       SDValue OffsetN = DAG.getIntPtrConstant(Offset);
 328       OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
 329       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
 330                                          PseudoSourceValue::getStack(),
 331                                          Offset));
 332     }
 333   }
 334
 335   // Transform all store nodes into one single node because
 336   // all store nodes are independent of each other.
 337   if (!MemOpChains.empty())
 338     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 339                         &MemOpChains[0], MemOpChains.size());
 340
 341   // Build a sequence of copy-to-reg nodes chained together with token
 342   // chain and flag operands which copy the outgoing args into registers.
 343   // The InFlag in necessary since all emited instructions must be
 344   // stuck together.
 345   SDValue InFlag;
 346   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 347     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 348                              RegsToPass[i].second, InFlag);
 349     InFlag = Chain.getValue(1);
 350   }
 351
 352   // If the callee is a GlobalAddress node (quite common, every direct call is)
 353   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 354   // Likewise ExternalSymbol -> TargetExternalSymbol.
 355   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 356     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
 357   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 358     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
 359
 360   std::vector<MVT> NodeTys;
 361   NodeTys.push_back(MVT::Other);   // Returns a chain
 362   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
 363   SDValue Ops[] = { Chain, Callee, InFlag };
 364   Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
 365                       InFlag.getNode() ? 3 : 2);
 366   InFlag = Chain.getValue(1);
 367
 368   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
 369                              DAG.getIntPtrConstant(0, true), InFlag);
 370   InFlag = Chain.getValue(1);
 371
 372   // Assign locations to each value returned by this call.
 373   SmallVector<CCValAssign, 16> RVLocs;
 374   CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
 375                  *DAG.getContext());
 376
 377   RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
 378
 379   // Copy all of the result registers out of their specified physreg.
 380   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 381     CCValAssign &RV = RVLocs[i];
 382     unsigned Reg = RV.getLocReg();
 383
 384     Chain = DAG.getCopyFromReg(Chain, dl, Reg,
 385                                RVLocs[i].getLocVT(), InFlag);
 386     SDValue Val = Chain.getValue(0);
 387     InFlag = Chain.getValue(2);
 388     Chain = Chain.getValue(1);
 389
 390     // Callee is responsible for extending any i16 return values.
 391     switch (RV.getLocInfo()) {
 392     case CCValAssign::SExt:
 393       Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
 394                         DAG.getValueType(RV.getValVT()));
 395       break;
 396     case CCValAssign::ZExt:
 397       Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
 398                         DAG.getValueType(RV.getValVT()));
 399       break;
 400     default:
 401       break;
 402     }
 403
 404     // Truncate to valtype
 405     if (RV.getLocInfo() != CCValAssign::Full)
 406       Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
 407     InVals.push_back(Val);
 408   }
 409
 410   return Chain;
 411 }
 412
 413 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
 414 // add-with-carry instructions.
 415 SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) {
 416   // Operands: lhs, rhs, carry-in (AC0 flag)
 417   // Results: sum, carry-out (AC0 flag)
 418   DebugLoc dl = Op.getDebugLoc();
 419
 420   unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
 421
 422   // zext incoming carry flag in AC0 to 32 bits
 423   SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 424                                       /* flag= */ Op.getOperand(2));
 425   CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32,
 426                               SDValue(CarryIn, 0));
 427
 428   // Add operands, produce sum and carry flag
 429   SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
 430                                   Op.getOperand(0), Op.getOperand(1));
 431
 432   // Store intermediate carry from Sum
 433   SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32,
 434                                      /* flag= */ SDValue(Sum, 1));
 435
 436   // Add incoming carry, again producing an output flag
 437   Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
 438                           SDValue(Sum, 0), SDValue(CarryIn, 0));
 439
 440   // Update AC0 with the intermediate carry, producing a flag.
 441   SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag,
 442                                        SDValue(Carry1, 0));
 443
 444   // Compose (i32, flag) pair
 445   SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
 446   return DAG.getMergeValues(ops, 2, dl);
 447 }
 448
 449 SDValue BlackfinTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
 450   switch (Op.getOpcode()) {
 451   default:
 452     Op.getNode()->dump();
 453     llvm_unreachable("Should not custom lower this!");
 454   case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
 455   case ISD::GlobalTLSAddress:
 456     llvm_unreachable("TLS not implemented for Blackfin.");
 457   case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
 458     // Frame & Return address.  Currently unimplemented
 459   case ISD::FRAMEADDR:          return SDValue();
 460   case ISD::RETURNADDR:         return SDValue();
 461   case ISD::ADDE:
 462   case ISD::SUBE:               return LowerADDE(Op, DAG);
 463   }
 464 }
 465
 466 /// getFunctionAlignment - Return the Log2 alignment of this function.
 467 unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
 468   return 2;
 469 }
 470
 471 //===----------------------------------------------------------------------===//
 472 //                         Blackfin Inline Assembly Support
 473 //===----------------------------------------------------------------------===//
 474
 475 /// getConstraintType - Given a constraint letter, return the type of
 476 /// constraint it is for this target.
 477 BlackfinTargetLowering::ConstraintType
 478 BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
 479   if (Constraint.size() != 1)
 480     return TargetLowering::getConstraintType(Constraint);
 481
 482   switch (Constraint[0]) {
 483     // Standard constraints
 484   case 'r':
 485     return C_RegisterClass;
 486
 487     // Blackfin-specific constraints
 488   case 'a':
 489   case 'd':
 490   case 'z':
 491   case 'D':
 492   case 'W':
 493   case 'e':
 494   case 'b':
 495   case 'v':
 496   case 'f':
 497   case 'c':
 498   case 't':
 499   case 'u':
 500   case 'k':
 501   case 'x':
 502   case 'y':
 503   case 'w':
 504     return C_RegisterClass;
 505   case 'A':
 506   case 'B':
 507   case 'C':
 508   case 'Z':
 509   case 'Y':
 510     return C_Register;
 511   }
 512
 513   // Not implemented: q0-q7, qA. Use {R2} etc instead
 514
 515   return TargetLowering::getConstraintType(Constraint);
 516 }
 517
 518 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
 519 /// constraint.
 520 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
 521 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
 522   typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
 523   using namespace BF;
 524
 525   if (Constraint.size() != 1)
 526     return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 527
 528   switch (Constraint[0]) {
 529     // Standard constraints
 530   case 'r':
 531     return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
 532
 533     // Blackfin-specific constraints
 534   case 'a': return Pair(0U, PRegisterClass);
 535   case 'd': return Pair(0U, DRegisterClass);
 536   case 'e': return Pair(0U, AccuRegisterClass);
 537   case 'A': return Pair(A0, AccuRegisterClass);
 538   case 'B': return Pair(A1, AccuRegisterClass);
 539   case 'b': return Pair(0U, IRegisterClass);
 540   case 'v': return Pair(0U, BRegisterClass);
 541   case 'f': return Pair(0U, MRegisterClass);
 542   case 'C': return Pair(CC, JustCCRegisterClass);
 543   case 'x': return Pair(0U, GRRegisterClass);
 544   case 'w': return Pair(0U, ALLRegisterClass);
 545   case 'Z': return Pair(P3, PRegisterClass);
 546   case 'Y': return Pair(P1, PRegisterClass);
 547   }
 548
 549   // Not implemented: q0-q7, qA. Use {R2} etc instead.
 550   // Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
 551   // getRegClassForInlineAsmConstraint()
 552
 553   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
 554 }
 555
 556 std::vector<unsigned> BlackfinTargetLowering::
 557 getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
 558   using namespace BF;
 559
 560   if (Constraint.size() != 1)
 561     return std::vector<unsigned>();
 562
 563   switch (Constraint[0]) {
 564   case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
 565   case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
 566   case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
 567   case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
 568                                          B0, B1, B2, B3,
 569                                          L0, L1, L2, L3, 0);
 570   case 't': return make_vector<unsigned>(LT0, LT1, 0);
 571   case 'u': return make_vector<unsigned>(LB0, LB1, 0);
 572   case 'k': return make_vector<unsigned>(LC0, LC1, 0);
 573   case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
 574                                          ASTAT, SEQSTAT, USP, 0);
 575   }
 576
 577   return std::vector<unsigned>();
 578 }
 579
 580 bool BlackfinTargetLowering::
 581 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
 582   // The Blackfin target isn't yet aware of offsets.
 583   return false;
 584 }