lib/Target/Blackfin/BlackfinRegisterInfo.cpp

   1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Blackfin implementation of the TargetRegisterInfo
  11 // class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "Blackfin.h"
  16 #include "BlackfinRegisterInfo.h"
  17 #include "BlackfinSubtarget.h"
  18 #include "llvm/Support/Debug.h"
  19 #include "llvm/Support/ErrorHandling.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/CodeGen/MachineFunction.h"
  22 #include "llvm/CodeGen/MachineFrameInfo.h"
  23 #include "llvm/CodeGen/MachineLocation.h"
  24 #include "llvm/CodeGen/RegisterScavenging.h"
  25 #include "llvm/Target/TargetFrameInfo.h"
  26 #include "llvm/Target/TargetMachine.h"
  27 #include "llvm/Target/TargetOptions.h"
  28 #include "llvm/Target/TargetInstrInfo.h"
  29 #include "llvm/Type.h"
  30 #include "llvm/ADT/BitVector.h"
  31 #include "llvm/ADT/STLExtras.h"
  32 using namespace llvm;
  33
  34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
  35                                            const TargetInstrInfo &tii)
  36   : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
  37     Subtarget(st),
  38     TII(tii) {}
  39
  40 const unsigned*
  41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
  42   using namespace BF;
  43   static const unsigned CalleeSavedRegs[] = {
  44     FP,
  45     R4, R5, R6, R7,
  46     P3, P4, P5,
  47     0 };
  48   return  CalleeSavedRegs;
  49 }
  50
  51 const TargetRegisterClass* const *BlackfinRegisterInfo::
  52 getCalleeSavedRegClasses(const MachineFunction *MF) const {
  53   using namespace BF;
  54   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
  55     &PRegClass,
  56     &DRegClass, &DRegClass, &DRegClass, &DRegClass,
  57     &PRegClass, &PRegClass, &PRegClass,
  58     0 };
  59   return CalleeSavedRegClasses;
  60 }
  61
  62 BitVector
  63 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  64   using namespace BF;
  65   BitVector Reserved(getNumRegs());
  66   Reserved.set(AZ);
  67   Reserved.set(AN);
  68   Reserved.set(AQ);
  69   Reserved.set(AC0);
  70   Reserved.set(AC1);
  71   Reserved.set(AV0);
  72   Reserved.set(AV0S);
  73   Reserved.set(AV1);
  74   Reserved.set(AV1S);
  75   Reserved.set(V);
  76   Reserved.set(VS);
  77   Reserved.set(L0);
  78   Reserved.set(L1);
  79   Reserved.set(L2);
  80   Reserved.set(L3);
  81   Reserved.set(SP);
  82   Reserved.set(RETS);
  83   if (hasFP(MF))
  84     Reserved.set(FP);
  85   return Reserved;
  86 }
  87
  88 const TargetRegisterClass*
  89 BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
  90   assert(isPhysicalRegister(reg) && "reg must be a physical register");
  91
  92   // Pick the smallest register class of the right type that contains
  93   // this physreg.
  94   const TargetRegisterClass* BestRC = 0;
  95   for (regclass_iterator I = regclass_begin(), E = regclass_end();
  96        I != E; ++I) {
  97     const TargetRegisterClass* RC = *I;
  98     if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
  99         (!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
 100       BestRC = RC;
 101   }
 102
 103   assert(BestRC && "Couldn't find the register class");
 104   return BestRC;
 105 }
 106
 107 // hasFP - Return true if the specified function should have a dedicated frame
 108 // pointer register.  This is true if the function has variable sized allocas or
 109 // if frame pointer elimination is disabled.
 110 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
 111   const MachineFrameInfo *MFI = MF.getFrameInfo();
 112   return NoFramePointerElim || MFI->hasCalls() || MFI->hasVarSizedObjects();
 113 }
 114
 115 bool BlackfinRegisterInfo::
 116 requiresRegisterScavenging(const MachineFunction &MF) const {
 117   return true;
 118 }
 119
 120 // Emit instructions to add delta to D/P register. ScratchReg must be of the
 121 // same class as Reg (P).
 122 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
 123                                           MachineBasicBlock::iterator I,
 124                                           DebugLoc DL,
 125                                           unsigned Reg,
 126                                           unsigned ScratchReg,
 127                                           int delta) const {
 128   if (!delta)
 129     return;
 130   if (isImm<7>(delta)) {
 131     BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
 132       .addReg(Reg)              // No kill on two-addr operand
 133       .addImm(delta);
 134     return;
 135   }
 136
 137   // We must load delta into ScratchReg and add that.
 138   loadConstant(MBB, I, DL, ScratchReg, delta);
 139   if (BF::PRegClass.contains(Reg)) {
 140     assert(BF::PRegClass.contains(ScratchReg) &&
 141            "ScratchReg must be a P register");
 142     BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
 143       .addReg(Reg, RegState::Kill)
 144       .addReg(ScratchReg, RegState::Kill);
 145   } else {
 146     assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
 147     assert(BF::DRegClass.contains(ScratchReg) &&
 148            "ScratchReg must be a D register");
 149     BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
 150       .addReg(Reg, RegState::Kill)
 151       .addReg(ScratchReg, RegState::Kill);
 152   }
 153 }
 154
 155 // Emit instructions to load a constant into D/P register
 156 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
 157                                         MachineBasicBlock::iterator I,
 158                                         DebugLoc DL,
 159                                         unsigned Reg,
 160                                         int value) const {
 161   if (isImm<7>(value)) {
 162     BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
 163     return;
 164   }
 165
 166   if (isUimm<16>(value)) {
 167     BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
 168     return;
 169   }
 170
 171   if (isImm<16>(value)) {
 172     BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
 173     return;
 174   }
 175
 176   // We must split into halves
 177   BuildMI(MBB, I, DL,
 178           TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_hi16))
 179     .addImm((value >> 16) & 0xffff)
 180     .addReg(Reg, RegState::ImplicitDefine);
 181   BuildMI(MBB, I, DL,
 182           TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_lo16))
 183     .addImm(value & 0xffff)
 184     .addReg(Reg, RegState::ImplicitKill)
 185     .addReg(Reg, RegState::ImplicitDefine);
 186 }
 187
 188 void BlackfinRegisterInfo::
 189 eliminateCallFramePseudoInstr(MachineFunction &MF,
 190                               MachineBasicBlock &MBB,
 191                               MachineBasicBlock::iterator I) const {
 192   if (!hasReservedCallFrame(MF)) {
 193     int64_t Amount = I->getOperand(0).getImm();
 194     if (Amount != 0) {
 195       assert(Amount%4 == 0 && "Unaligned call frame size");
 196       if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
 197         adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
 198       } else {
 199         assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
 200                "Unknown call frame pseudo instruction");
 201         adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
 202       }
 203     }
 204   }
 205   MBB.erase(I);
 206 }
 207
 208 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
 209 /// register first and then a spilled callee-saved register if that fails.
 210 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
 211                                     RegScavenger *RS,
 212                                     const TargetRegisterClass *RC,
 213                                     int SPAdj) {
 214   assert(RS && "Register scavenging must be on");
 215   unsigned Reg = RS->FindUnusedReg(RC, true);
 216   if (Reg == 0)
 217     Reg = RS->scavengeRegister(RC, II, SPAdj);
 218   return Reg;
 219 }
 220
 221 void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 222                                                int SPAdj,
 223                                                RegScavenger *RS) const {
 224   MachineInstr &MI = *II;
 225   MachineBasicBlock &MBB = *MI.getParent();
 226   MachineFunction &MF = *MBB.getParent();
 227   DebugLoc DL = MI.getDebugLoc();
 228
 229   unsigned FIPos;
 230   for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
 231     assert(FIPos < MI.getNumOperands() &&
 232            "Instr doesn't have FrameIndex operand!");
 233   }
 234   int FrameIndex = MI.getOperand(FIPos).getIndex();
 235   assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
 236   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
 237     + MI.getOperand(FIPos+1).getImm();
 238   unsigned BaseReg = BF::FP;
 239   if (hasFP(MF)) {
 240     assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
 241   } else {
 242     BaseReg = BF::SP;
 243     Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
 244   }
 245
 246   bool isStore = false;
 247
 248   switch (MI.getOpcode()) {
 249   case BF::STORE32fi:
 250     isStore = true;
 251   case BF::LOAD32fi: {
 252     assert(Offset%4 == 0 && "Unaligned i32 stack access");
 253     assert(FIPos==1 && "Bad frame index operand");
 254     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 255     MI.getOperand(FIPos+1).setImm(Offset);
 256     if (isUimm<6>(Offset)) {
 257       MI.setDesc(TII.get(isStore
 258                          ? BF::STORE32p_uimm6m4
 259                          : BF::LOAD32p_uimm6m4));
 260       return;
 261     }
 262     if (BaseReg == BF::FP && isUimm<7>(-Offset)) {
 263       MI.setDesc(TII.get(isStore
 264                          ? BF::STORE32fp_nimm7m4
 265                          : BF::LOAD32fp_nimm7m4));
 266       MI.getOperand(FIPos+1).setImm(-Offset);
 267       return;
 268     }
 269     if (isImm<18>(Offset)) {
 270       MI.setDesc(TII.get(isStore
 271                          ? BF::STORE32p_imm18m4
 272                          : BF::LOAD32p_imm18m4));
 273       return;
 274     }
 275     // Use RegScavenger to calculate proper offset...
 276     MI.dump();
 277     llvm_unreachable("Stack frame offset too big");
 278     break;
 279   }
 280   case BF::ADDpp: {
 281     assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
 282     unsigned DestReg = MI.getOperand(0).getReg();
 283     // We need to produce a stack offset in a P register. We emit:
 284     // P0 = offset;
 285     // P0 = BR + P0;
 286     assert(FIPos==1 && "Bad frame index operand");
 287     loadConstant(MBB, II, DL, DestReg, Offset);
 288     MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
 289     MI.getOperand(2).ChangeToRegister(BaseReg, false);
 290     break;
 291   }
 292   case BF::STORE16fi:
 293     isStore = true;
 294   case BF::LOAD16fi: {
 295     assert(Offset%2 == 0 && "Unaligned i16 stack access");
 296     assert(FIPos==1 && "Bad frame index operand");
 297     // We need a P register to use as an address
 298     unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
 299     assert(ScratchReg && "Could not scavenge register");
 300     loadConstant(MBB, II, DL, ScratchReg, Offset);
 301     BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
 302       .addReg(ScratchReg, RegState::Kill)
 303       .addReg(BaseReg);
 304     MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
 305     MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
 306     MI.RemoveOperand(2);
 307     break;
 308   }
 309   case BF::STORE8fi: {
 310     // This is an AnyCC spill, we need a scratch register.
 311     assert(FIPos==1 && "Bad frame index operand");
 312     MachineOperand SpillReg = MI.getOperand(0);
 313     unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
 314     assert(ScratchReg && "Could not scavenge register");
 315     if (SpillReg.getReg()==BF::NCC) {
 316       BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
 317         .addOperand(SpillReg);
 318       BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
 319         .addReg(ScratchReg).addImm(0);
 320     } else {
 321       BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
 322         .addOperand(SpillReg);
 323     }
 324     // STORE D
 325     MI.setDesc(TII.get(BF::STORE8p_imm16));
 326     MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
 327     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 328     MI.getOperand(FIPos+1).setImm(Offset);
 329     break;
 330   }
 331   case BF::LOAD8fi: {
 332     // This is an restore, we need a scratch register.
 333     assert(FIPos==1 && "Bad frame index operand");
 334     MachineOperand SpillReg = MI.getOperand(0);
 335     unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
 336     assert(ScratchReg && "Could not scavenge register");
 337     MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
 338     MI.getOperand(0).ChangeToRegister(ScratchReg, true);
 339     MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
 340     MI.getOperand(FIPos+1).setImm(Offset);
 341     ++II;
 342     if (SpillReg.getReg()==BF::CC) {
 343       // CC = D
 344       BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
 345         .addReg(ScratchReg, RegState::Kill);
 346     } else {
 347       // Restore NCC (CC = D==0)
 348       BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
 349         .addReg(ScratchReg, RegState::Kill)
 350         .addImm(0);
 351     }
 352     break;
 353   }
 354   default:
 355     llvm_unreachable("Cannot eliminate frame index");
 356     break;
 357   }
 358 }
 359
 360 void BlackfinRegisterInfo::
 361 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 362                                      RegScavenger *RS) const {
 363   MachineFrameInfo *MFI = MF.getFrameInfo();
 364   const TargetRegisterClass *RC = BF::DPRegisterClass;
 365   if (requiresRegisterScavenging(MF)) {
 366     // Reserve a slot close to SP or frame pointer.
 367     RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
 368                                                        RC->getAlignment()));
 369   }
 370 }
 371
 372 void BlackfinRegisterInfo::
 373 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
 374 }
 375
 376 // Emit a prologue that sets up a stack frame.
 377 // On function entry, R0-R2 and P0 may hold arguments.
 378 // R3, P1, and P2 may be used as scratch registers
 379 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
 380   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 381   MachineBasicBlock::iterator MBBI = MBB.begin();
 382   MachineFrameInfo *MFI = MF.getFrameInfo();
 383   DebugLoc dl = (MBBI != MBB.end()
 384                  ? MBBI->getDebugLoc()
 385                  : DebugLoc::getUnknownLoc());
 386
 387   int FrameSize = MFI->getStackSize();
 388   if (FrameSize%4) {
 389     FrameSize = (FrameSize+3) & ~3;
 390     MFI->setStackSize(FrameSize);
 391   }
 392
 393   if (!hasFP(MF)) {
 394     assert(!MFI->hasCalls() &&
 395            "FP elimination on a non-leaf function is not supported");
 396     adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
 397     return;
 398   }
 399
 400   // emit a LINK instruction
 401   if (FrameSize <= 0x3ffff) {
 402     BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
 403     return;
 404   }
 405
 406   // Frame is too big, do a manual LINK:
 407   // [--SP] = RETS;
 408   // [--SP] = FP;
 409   // FP = SP;
 410   // P1 = -FrameSize;
 411   // SP = SP + P1;
 412   BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
 413     .addReg(BF::RETS, RegState::Kill);
 414   BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
 415     .addReg(BF::FP, RegState::Kill);
 416   BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
 417     .addReg(BF::SP);
 418   loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
 419   BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
 420     .addReg(BF::SP, RegState::Kill)
 421     .addReg(BF::P1, RegState::Kill);
 422
 423 }
 424
 425 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
 426                                         MachineBasicBlock &MBB) const {
 427   MachineFrameInfo *MFI = MF.getFrameInfo();
 428   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 429   DebugLoc dl = MBBI->getDebugLoc();
 430
 431   int FrameSize = MFI->getStackSize();
 432   assert(FrameSize%4 == 0 && "Misaligned frame size");
 433
 434   if (!hasFP(MF)) {
 435     assert(!MFI->hasCalls() &&
 436            "FP elimination on a non-leaf function is not supported");
 437     adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
 438     return;
 439   }
 440
 441   // emit an UNLINK instruction
 442   BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
 443 }
 444
 445 unsigned BlackfinRegisterInfo::getRARegister() const {
 446   return BF::RETS;
 447 }
 448
 449 unsigned BlackfinRegisterInfo::getFrameRegister(MachineFunction &MF) const {
 450   return hasFP(MF) ? BF::FP : BF::SP;
 451 }
 452
 453 int
 454 BlackfinRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
 455   const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
 456   MachineFrameInfo *MFI = MF.getFrameInfo();
 457   return MFI->getObjectOffset(FI) + MFI->getStackSize() -
 458     TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
 459 }
 460
 461 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
 462   llvm_unreachable("What is the exception register");
 463   return 0;
 464 }
 465
 466 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
 467   llvm_unreachable("What is the exception handler register");
 468   return 0;
 469 }
 470
 471 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 472   llvm_unreachable("What is the dwarf register number");
 473   return -1;
 474 }
 475
 476 #include "BlackfinGenRegisterInfo.inc"
 477