lib/Target/XCore/XCoreISelLowering.h

   1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that XCore uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef XCOREISELLOWERING_H
  16 #define XCOREISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "XCore.h"
  21
  22 namespace llvm {
  23
  24   // Forward delcarations
  25   class XCoreSubtarget;
  26   class XCoreTargetMachine;
  27
  28   namespace XCoreISD {
  29     enum NodeType {
  30       // Start the numbering where the builtin ops and target ops leave off.
  31       FIRST_NUMBER = ISD::BUILTIN_OP_END+XCore::INSTRUCTION_LIST_END,
  32
  33       // Branch and link (call)
  34       BL,
  35
  36       // pc relative address
  37       PCRelativeWrapper,
  38
  39       // dp relative address
  40       DPRelativeWrapper,
  41
  42       // cp relative address
  43       CPRelativeWrapper,
  44
  45       // Store word to stack
  46       STWSP,
  47
  48       // Corresponds to retsp instruction
  49       RETSP,
  50
  51       // Corresponds to LADD instruction
  52       LADD,
  53
  54       // Corresponds to LSUB instruction
  55       LSUB
  56     };
  57   }
  58
  59   //===--------------------------------------------------------------------===//
  60   // TargetLowering Implementation
  61   //===--------------------------------------------------------------------===//
  62   class XCoreTargetLowering : public TargetLowering
  63   {
  64   public:
  65
  66     explicit XCoreTargetLowering(XCoreTargetMachine &TM);
  67
  68     /// LowerOperation - Provide custom lowering hooks for some operations.
  69     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
  70
  71     /// ReplaceNodeResults - Replace the results of node with an illegal result
  72     /// type with new values built out of custom code.
  73     ///
  74     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
  75                                     SelectionDAG &DAG);
  76
  77     /// getTargetNodeName - This method returns the name of a target specific
  78     //  DAG node.
  79     virtual const char *getTargetNodeName(unsigned Opcode) const;
  80
  81     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
  82                                                   MachineBasicBlock *MBB) const;
  83
  84     virtual bool isLegalAddressingMode(const AddrMode &AM,
  85                                        const Type *Ty) const;
  86
  87     /// getFunctionAlignment - Return the Log2 alignment of this function.
  88     virtual unsigned getFunctionAlignment(const Function *F) const;
  89
  90   private:
  91     const XCoreTargetMachine &TM;
  92     const XCoreSubtarget &Subtarget;
  93
  94     // Lower Operand helpers
  95     SDValue LowerCCCArguments(SDValue Chain,
  96                               unsigned CallConv,
  97                               bool isVarArg,
  98                               const SmallVectorImpl<ISD::InputArg> &Ins,
  99                               DebugLoc dl, SelectionDAG &DAG,
 100                               SmallVectorImpl<SDValue> &InVals);
 101     SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
 102                            unsigned CallConv, bool isVarArg,
 103                            bool isTailCall,
 104                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 105                            const SmallVectorImpl<ISD::InputArg> &Ins,
 106                            DebugLoc dl, SelectionDAG &DAG,
 107                            SmallVectorImpl<SDValue> &InVals);
 108     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 109                             unsigned CallConv, bool isVarArg,
 110                             const SmallVectorImpl<ISD::InputArg> &Ins,
 111                             DebugLoc dl, SelectionDAG &DAG,
 112                             SmallVectorImpl<SDValue> &InVals);
 113     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
 114     SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
 115                                     SelectionDAG &DAG);
 116
 117     // Lower Operand specifics
 118     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG);
 119     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);
 120     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
 121     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
 122     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
 123     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
 124     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
 125     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
 126     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
 127     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
 128
 129     // Inline asm support
 130     std::vector<unsigned>
 131     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 132               MVT VT) const;
 133
 134     // Expand specifics
 135     SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
 136
 137     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 138
 139     virtual SDValue
 140       LowerFormalArguments(SDValue Chain,
 141                            unsigned CallConv,
 142                            bool isVarArg,
 143                            const SmallVectorImpl<ISD::InputArg> &Ins,
 144                            DebugLoc dl, SelectionDAG &DAG,
 145                            SmallVectorImpl<SDValue> &InVals);
 146
 147     virtual SDValue
 148       LowerCall(SDValue Chain, SDValue Callee,
 149                 unsigned CallConv, bool isVarArg,
 150                 bool isTailCall,
 151                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 152                 const SmallVectorImpl<ISD::InputArg> &Ins,
 153                 DebugLoc dl, SelectionDAG &DAG,
 154                 SmallVectorImpl<SDValue> &InVals);
 155
 156     virtual SDValue
 157       LowerReturn(SDValue Chain,
 158                   unsigned CallConv, bool isVarArg,
 159                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 160                   DebugLoc dl, SelectionDAG &DAG);
 161   };
 162 }
 163
 164 #endif // XCOREISELLOWERING_H