lib/Target/Sparc/SparcRegisterInfo.cpp

   1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Sparc.h"
  15 #include "SparcRegisterInfo.h"
  16 #include "SparcSubtarget.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineLocation.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Target/TargetInstrInfo.h"
  23 #include "llvm/Type.h"
  24 #include "llvm/ADT/BitVector.h"
  25 #include "llvm/ADT/STLExtras.h"
  26 using namespace llvm;
  27
  28 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
  29                                      const TargetInstrInfo &tii)
  30   : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
  31     Subtarget(st), TII(tii) {
  32 }
  33
  34 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  35                                                                          const {
  36   static const unsigned CalleeSavedRegs[] = { 0 };
  37   return CalleeSavedRegs;
  38 }
  39
  40 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  41   BitVector Reserved(getNumRegs());
  42   Reserved.set(SP::G2);
  43   Reserved.set(SP::G3);
  44   Reserved.set(SP::G4);
  45   Reserved.set(SP::O6);
  46   Reserved.set(SP::I6);
  47   Reserved.set(SP::I7);
  48   Reserved.set(SP::G0);
  49   Reserved.set(SP::G5);
  50   Reserved.set(SP::G6);
  51   Reserved.set(SP::G7);
  52   return Reserved;
  53 }
  54
  55
  56 const TargetRegisterClass* const*
  57 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
  58   static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
  59   return CalleeSavedRegClasses;
  60 }
  61
  62 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
  63   return false;
  64 }
  65
  66 void SparcRegisterInfo::
  67 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
  68                               MachineBasicBlock::iterator I) const {
  69   MachineInstr &MI = *I;
  70   DebugLoc dl = MI.getDebugLoc();
  71   int Size = MI.getOperand(0).getImm();
  72   if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
  73     Size = -Size;
  74   if (Size)
  75     BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
  76   MBB.erase(I);
  77 }
  78
  79 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
  80                                             int SPAdj, RegScavenger *RS) const {
  81   assert(SPAdj == 0 && "Unexpected");
  82
  83   unsigned i = 0;
  84   MachineInstr &MI = *II;
  85   DebugLoc dl = MI.getDebugLoc();
  86   while (!MI.getOperand(i).isFI()) {
  87     ++i;
  88     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
  89   }
  90
  91   int FrameIndex = MI.getOperand(i).getIndex();
  92
  93   // Addressable stack objects are accessed using neg. offsets from %fp
  94   MachineFunction &MF = *MI.getParent()->getParent();
  95   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
  96                MI.getOperand(i+1).getImm();
  97
  98   // Replace frame index with a frame pointer reference.
  99   if (Offset >= -4096 && Offset <= 4095) {
 100     // If the offset is small enough to fit in the immediate field, directly
 101     // encode it.
 102     MI.getOperand(i).ChangeToRegister(SP::I6, false);
 103     MI.getOperand(i+1).ChangeToImmediate(Offset);
 104   } else {
 105     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
 106     // scavenge a register here instead of reserving G1 all of the time.
 107     unsigned OffHi = (unsigned)Offset >> 10U;
 108     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 109     // Emit G1 = G1 + I6
 110     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
 111       .addReg(SP::I6);
 112     // Insert: G1+%lo(offset) into the user.
 113     MI.getOperand(i).ChangeToRegister(SP::G1, false);
 114     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
 115   }
 116 }
 117
 118 void SparcRegisterInfo::
 119 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 120
 121 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
 122   MachineBasicBlock &MBB = MF.front();
 123   MachineFrameInfo *MFI = MF.getFrameInfo();
 124   MachineBasicBlock::iterator MBBI = MBB.begin();
 125   DebugLoc dl = (MBBI != MBB.end() ?
 126                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
 127
 128   // Get the number of bytes to allocate from the FrameInfo
 129   int NumBytes = (int) MFI->getStackSize();
 130
 131   // Emit the correct save instruction based on the number of bytes in
 132   // the frame. Minimum stack frame size according to V8 ABI is:
 133   //   16 words for register window spill
 134   //    1 word for address of returned aggregate-value
 135   // +  6 words for passing parameters on the stack
 136   // ----------
 137   //   23 words * 4 bytes per word = 92 bytes
 138   NumBytes += 92;
 139
 140   // Round up to next doubleword boundary -- a double-word boundary
 141   // is required by the ABI.
 142   NumBytes = (NumBytes + 7) & ~7;
 143   NumBytes = -NumBytes;
 144
 145   if (NumBytes >= -4096) {
 146     BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
 147       .addReg(SP::O6).addImm(NumBytes);
 148   } else {
 149     // Emit this the hard way.  This clobbers G1 which we always know is
 150     // available here.
 151     unsigned OffHi = (unsigned)NumBytes >> 10U;
 152     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 153     // Emit G1 = G1 + I6
 154     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
 155       .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
 156     BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
 157       .addReg(SP::O6).addReg(SP::G1);
 158   }
 159 }
 160
 161 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
 162                                      MachineBasicBlock &MBB) const {
 163   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 164   DebugLoc dl = MBBI->getDebugLoc();
 165   assert(MBBI->getOpcode() == SP::RETL &&
 166          "Can only put epilog before 'retl' instruction!");
 167   BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
 168     .addReg(SP::G0);
 169 }
 170
 171 unsigned SparcRegisterInfo::getRARegister() const {
 172   return SP::I7;
 173 }
 174
 175 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
 176   return SP::I6;
 177 }
 178
 179 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
 180   llvm_unreachable("What is the exception register");
 181   return 0;
 182 }
 183
 184 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
 185   llvm_unreachable("What is the exception handler register");
 186   return 0;
 187 }
 188
 189 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 190   return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
 191 }
 192
 193 #include "SparcGenRegisterInfo.inc"
 194