Added the LAR (load segment access rights)
[llvm/avr.git] / lib / Target / X86 / AsmPrinter / X86ATTInstPrinter.cpp
blob7576ab371d021128518f870b1eb98a7b088baab7
1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as AT&T-style
11 // assembly.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86ATTInstPrinter.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/FormattedStream.h"
22 using namespace llvm;
24 // Include the auto-generated portion of the assembly writer.
25 #define MachineInstr MCInst
26 #define NO_ASM_WRITER_BOILERPLATE
27 #include "X86GenAsmWriter.inc"
28 #undef MachineInstr
30 void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
32 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) {
33 switch (MI->getOperand(Op).getImm()) {
34 default: llvm_unreachable("Invalid ssecc argument!");
35 case 0: O << "eq"; break;
36 case 1: O << "lt"; break;
37 case 2: O << "le"; break;
38 case 3: O << "unord"; break;
39 case 4: O << "neq"; break;
40 case 5: O << "nlt"; break;
41 case 6: O << "nle"; break;
42 case 7: O << "ord"; break;
46 void X86ATTInstPrinter::printPICLabel(const MCInst *MI, unsigned Op) {
47 llvm_unreachable("This is only used for MOVPC32r,"
48 "should lower before instruction printing!");
51 /// print_pcrel_imm - This is used to print an immediate value that ends up
52 /// being encoded as a pc-relative value. These print slightly differently, for
53 /// example, a $ is not emitted.
54 void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
55 const MCOperand &Op = MI->getOperand(OpNo);
56 if (Op.isImm())
57 O << Op.getImm();
58 else {
59 assert(Op.isExpr() && "unknown pcrel immediate operand");
60 Op.getExpr()->print(O, &MAI);
64 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
65 const char *Modifier) {
66 assert(Modifier == 0 && "Modifiers should not be used");
68 const MCOperand &Op = MI->getOperand(OpNo);
69 if (Op.isReg()) {
70 O << '%' << getRegisterName(Op.getReg());
71 } else if (Op.isImm()) {
72 O << '$' << Op.getImm();
73 } else {
74 assert(Op.isExpr() && "unknown operand kind in printOperand");
75 O << '$';
76 Op.getExpr()->print(O, &MAI);
80 void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
81 const MCOperand &BaseReg = MI->getOperand(Op);
82 const MCOperand &IndexReg = MI->getOperand(Op+2);
83 const MCOperand &DispSpec = MI->getOperand(Op+3);
85 if (DispSpec.isImm()) {
86 int64_t DispVal = DispSpec.getImm();
87 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
88 O << DispVal;
89 } else {
90 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
91 DispSpec.getExpr()->print(O, &MAI);
94 if (IndexReg.getReg() || BaseReg.getReg()) {
95 O << '(';
96 if (BaseReg.getReg())
97 printOperand(MI, Op);
99 if (IndexReg.getReg()) {
100 O << ',';
101 printOperand(MI, Op+2);
102 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
103 if (ScaleVal != 1)
104 O << ',' << ScaleVal;
106 O << ')';
110 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op) {
111 // If this has a segment register, print it.
112 if (MI->getOperand(Op+4).getReg()) {
113 printOperand(MI, Op+4);
114 O << ':';
116 printLeaMemReference(MI, Op);