| blob | e6588f6bd0169a6bb5201e0c9a06acf172042f71 |
1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
13 //
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
18 //
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
24 // pc relative.
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
27 }
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
33 }
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
39 }
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
46 }
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
50 //
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
53 X86WrapperRIP], []>;
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
59 // Pattern fragments.
60 //
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
66 }]>;
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
72 }]>;
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
78 }]>;
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
96 //
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
105 "#ADJCALLSTACKDOWN",
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
109 "#ADJCALLSTACKUP",
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
112 }
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
116 //
117 let isCall = 1 in
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
127 Uses = [RSP] in {
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
134 "call\t$dst", []>,
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
145 }
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
148 let isCall = 1 in
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
157 Uses = [RSP] in {
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
160 "call\t$dst", []>,
161 Requires<[IsWin64]>;
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
163 "call\t{*}$dst",
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
166 "call\t{*}$dst",
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
168 }
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
173 variable_ops),
174 "#TC_RETURN $dst $offset",
175 []>;
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
179 variable_ops),
180 "#TC_RETURN $dst $offset",
181 []>;
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
187 []>;
189 // Branches
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
197 }
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
201 //
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
203 hasCtrlDep = 1 in {
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
208 }
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
212 //
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
217 let mayLoad = 1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
222 }
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
228 }
229 }
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
238 }
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
257 "bswap{q}\t$dst",
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
277 } // Defs = [EFLAGS]
279 // Repeat string ops
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
289 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
291 // Fast system-call instructions
292 def SYSEXIT64 : RI<0x35, RawFrm,
293 (outs), (ins), "sysexit", []>, TB;
295 //===----------------------------------------------------------------------===//
296 // Move Instructions...
297 //
299 let neverHasSideEffects = 1 in
300 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
301 "mov{q}\t{$src, $dst|$dst, $src}", []>;
303 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
304 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
305 "movabs{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, imm:$src)]>;
307 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
308 "mov{q}\t{$src, $dst|$dst, $src}",
309 [(set GR64:$dst, i64immSExt32:$src)]>;
310 }
312 let canFoldAsLoad = 1 in
313 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}",
315 [(set GR64:$dst, (load addr:$src))]>;
317 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
318 "mov{q}\t{$src, $dst|$dst, $src}",
319 [(store GR64:$src, addr:$dst)]>;
320 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
321 "mov{q}\t{$src, $dst|$dst, $src}",
322 [(store i64immSExt32:$src, addr:$dst)]>;
324 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
325 "mov{q}\t{$src, %rax|%rax, $src}", []>;
326 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
327 "mov{q}\t{$src, %rax|%rax, $src}", []>;
328 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
329 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
330 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
331 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
333 // Moves to and from segment registers
334 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
335 "mov{w}\t{$src, $dst|$dst, $src}", []>;
336 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
337 "mov{w}\t{$src, $dst|$dst, $src}", []>;
338 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
339 "mov{w}\t{$src, $dst|$dst, $src}", []>;
340 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
341 "mov{w}\t{$src, $dst|$dst, $src}", []>;
343 // Sign/Zero extenders
345 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
346 // operand, which makes it a rare instruction with an 8-bit register
347 // operand that can never access an h register. If support for h registers
348 // were generalized, this would require a special register class.
349 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
350 "movs{bq|x}\t{$src, $dst|$dst, $src}",
351 [(set GR64:$dst, (sext GR8:$src))]>, TB;
352 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
353 "movs{bq|x}\t{$src, $dst|$dst, $src}",
354 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
355 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
356 "movs{wq|x}\t{$src, $dst|$dst, $src}",
357 [(set GR64:$dst, (sext GR16:$src))]>, TB;
358 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
359 "movs{wq|x}\t{$src, $dst|$dst, $src}",
360 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
361 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
362 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
363 [(set GR64:$dst, (sext GR32:$src))]>;
364 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
365 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
366 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
368 // Use movzbl instead of movzbq when the destination is a register; it's
369 // equivalent due to implicit zero-extending, and it has a smaller encoding.
370 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
371 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
372 [(set GR64:$dst, (zext GR8:$src))]>, TB;
373 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
374 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
375 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
376 // Use movzwl instead of movzwq when the destination is a register; it's
377 // equivalent due to implicit zero-extending, and it has a smaller encoding.
378 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
379 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
380 [(set GR64:$dst, (zext GR16:$src))]>, TB;
381 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
382 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
383 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
385 // There's no movzlq instruction, but movl can be used for this purpose, using
386 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
387 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
388 // zero-extension, however this isn't possible when the 32-bit value is
389 // defined by a truncate or is copied from something where the high bits aren't
390 // necessarily all zero. In such cases, we fall back to these explicit zext
391 // instructions.
392 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
393 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
394 [(set GR64:$dst, (zext GR32:$src))]>;
395 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
396 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
397 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
399 // Any instruction that defines a 32-bit result leaves the high half of the
400 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
401 // be copying from a truncate. And x86's cmov doesn't do anything if the
402 // condition is false. But any other 32-bit operation will zero-extend
403 // up to 64 bits.
404 def def32 : PatLeaf<(i32 GR32:$src), [{
405 return N->getOpcode() != ISD::TRUNCATE &&
406 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
407 N->getOpcode() != ISD::CopyFromReg &&
408 N->getOpcode() != X86ISD::CMOV;
409 }]>;
411 // In the case of a 32-bit def that is known to implicitly zero-extend,
412 // we can use a SUBREG_TO_REG.
413 def : Pat<(i64 (zext def32:$src)),
414 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
416 let neverHasSideEffects = 1 in {
417 let Defs = [RAX], Uses = [EAX] in
418 def CDQE : RI<0x98, RawFrm, (outs), (ins),
419 "{cltq|cdqe}", []>; // RAX = signext(EAX)
421 let Defs = [RAX,RDX], Uses = [RAX] in
422 def CQO : RI<0x99, RawFrm, (outs), (ins),
423 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
424 }
426 //===----------------------------------------------------------------------===//
427 // Arithmetic Instructions...
428 //
430 let Defs = [EFLAGS] in {
432 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
433 "add{q}\t{$src, %rax|%rax, $src}", []>;
435 let isTwoAddress = 1 in {
436 let isConvertibleToThreeAddress = 1 in {
437 let isCommutable = 1 in
438 // Register-Register Addition
439 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
440 "add{q}\t{$src2, $dst|$dst, $src2}",
441 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
442 (implicit EFLAGS)]>;
444 // Register-Integer Addition
445 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
446 "add{q}\t{$src2, $dst|$dst, $src2}",
447 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
448 (implicit EFLAGS)]>;
449 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
450 "add{q}\t{$src2, $dst|$dst, $src2}",
451 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
452 (implicit EFLAGS)]>;
453 } // isConvertibleToThreeAddress
455 // Register-Memory Addition
456 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
457 "add{q}\t{$src2, $dst|$dst, $src2}",
458 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
459 (implicit EFLAGS)]>;
461 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
462 // differently encoded.
463 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
464 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
466 } // isTwoAddress
468 // Memory-Register Addition
469 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
470 "add{q}\t{$src2, $dst|$dst, $src2}",
471 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
472 (implicit EFLAGS)]>;
473 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
474 "add{q}\t{$src2, $dst|$dst, $src2}",
475 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
476 (implicit EFLAGS)]>;
477 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
478 "add{q}\t{$src2, $dst|$dst, $src2}",
479 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
480 (implicit EFLAGS)]>;
482 let Uses = [EFLAGS] in {
484 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
485 "adc{q}\t{$src, %rax|%rax, $src}", []>;
487 let isTwoAddress = 1 in {
488 let isCommutable = 1 in
489 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
490 "adc{q}\t{$src2, $dst|$dst, $src2}",
491 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
493 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
494 "adc{q}\t{$src2, $dst|$dst, $src2}",
495 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
497 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
498 "adc{q}\t{$src2, $dst|$dst, $src2}",
499 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
500 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
501 "adc{q}\t{$src2, $dst|$dst, $src2}",
502 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
503 } // isTwoAddress
505 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
506 "adc{q}\t{$src2, $dst|$dst, $src2}",
507 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
508 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
509 "adc{q}\t{$src2, $dst|$dst, $src2}",
510 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
511 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
512 "adc{q}\t{$src2, $dst|$dst, $src2}",
513 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
514 } // Uses = [EFLAGS]
516 let isTwoAddress = 1 in {
517 // Register-Register Subtraction
518 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
519 "sub{q}\t{$src2, $dst|$dst, $src2}",
520 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
521 (implicit EFLAGS)]>;
523 // Register-Memory Subtraction
524 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
525 "sub{q}\t{$src2, $dst|$dst, $src2}",
526 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
527 (implicit EFLAGS)]>;
529 // Register-Integer Subtraction
530 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
531 (ins GR64:$src1, i64i8imm:$src2),
532 "sub{q}\t{$src2, $dst|$dst, $src2}",
533 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
534 (implicit EFLAGS)]>;
535 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
536 (ins GR64:$src1, i64i32imm:$src2),
537 "sub{q}\t{$src2, $dst|$dst, $src2}",
538 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
539 (implicit EFLAGS)]>;
540 } // isTwoAddress
542 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
543 "sub{q}\t{$src, %rax|%rax, $src}", []>;
545 // Memory-Register Subtraction
546 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
547 "sub{q}\t{$src2, $dst|$dst, $src2}",
548 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
549 (implicit EFLAGS)]>;
551 // Memory-Integer Subtraction
552 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
553 "sub{q}\t{$src2, $dst|$dst, $src2}",
554 [(store (sub (load addr:$dst), i64immSExt8:$src2),
555 addr:$dst),
556 (implicit EFLAGS)]>;
557 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
558 "sub{q}\t{$src2, $dst|$dst, $src2}",
559 [(store (sub (load addr:$dst), i64immSExt32:$src2),
560 addr:$dst),
561 (implicit EFLAGS)]>;
563 let Uses = [EFLAGS] in {
564 let isTwoAddress = 1 in {
565 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
566 "sbb{q}\t{$src2, $dst|$dst, $src2}",
567 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
569 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
570 "sbb{q}\t{$src2, $dst|$dst, $src2}",
571 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
573 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
574 "sbb{q}\t{$src2, $dst|$dst, $src2}",
575 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
576 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
577 "sbb{q}\t{$src2, $dst|$dst, $src2}",
578 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
579 } // isTwoAddress
581 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
582 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
584 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
585 "sbb{q}\t{$src2, $dst|$dst, $src2}",
586 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
587 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
588 "sbb{q}\t{$src2, $dst|$dst, $src2}",
589 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
590 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
591 "sbb{q}\t{$src2, $dst|$dst, $src2}",
592 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
593 } // Uses = [EFLAGS]
594 } // Defs = [EFLAGS]
596 // Unsigned multiplication
597 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
598 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
599 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
600 let mayLoad = 1 in
601 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
602 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
604 // Signed multiplication
605 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
606 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
607 let mayLoad = 1 in
608 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
609 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
610 }
612 let Defs = [EFLAGS] in {
613 let isTwoAddress = 1 in {
614 let isCommutable = 1 in
615 // Register-Register Signed Integer Multiplication
616 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
617 (ins GR64:$src1, GR64:$src2),
618 "imul{q}\t{$src2, $dst|$dst, $src2}",
619 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
620 (implicit EFLAGS)]>, TB;
622 // Register-Memory Signed Integer Multiplication
623 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
624 (ins GR64:$src1, i64mem:$src2),
625 "imul{q}\t{$src2, $dst|$dst, $src2}",
626 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
627 (implicit EFLAGS)]>, TB;
628 } // isTwoAddress
630 // Suprisingly enough, these are not two address instructions!
632 // Register-Integer Signed Integer Multiplication
633 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
634 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
635 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
636 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
637 (implicit EFLAGS)]>;
638 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
639 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
640 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
641 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
642 (implicit EFLAGS)]>;
644 // Memory-Integer Signed Integer Multiplication
645 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
646 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
647 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
648 [(set GR64:$dst, (mul (load addr:$src1),
649 i64immSExt8:$src2)),
650 (implicit EFLAGS)]>;
651 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
652 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
653 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
654 [(set GR64:$dst, (mul (load addr:$src1),
655 i64immSExt32:$src2)),
656 (implicit EFLAGS)]>;
657 } // Defs = [EFLAGS]
659 // Unsigned division / remainder
660 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
661 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
662 "div{q}\t$src", []>;
663 // Signed division / remainder
664 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
665 "idiv{q}\t$src", []>;
666 let mayLoad = 1 in {
667 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
668 "div{q}\t$src", []>;
669 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
670 "idiv{q}\t$src", []>;
671 }
672 }
674 // Unary instructions
675 let Defs = [EFLAGS], CodeSize = 2 in {
676 let isTwoAddress = 1 in
677 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
678 [(set GR64:$dst, (ineg GR64:$src)),
679 (implicit EFLAGS)]>;
680 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
681 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
682 (implicit EFLAGS)]>;
684 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
685 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
686 [(set GR64:$dst, (add GR64:$src, 1)),
687 (implicit EFLAGS)]>;
688 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
689 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
690 (implicit EFLAGS)]>;
692 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
693 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
694 [(set GR64:$dst, (add GR64:$src, -1)),
695 (implicit EFLAGS)]>;
696 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
697 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
698 (implicit EFLAGS)]>;
700 // In 64-bit mode, single byte INC and DEC cannot be encoded.
701 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
702 // Can transform into LEA.
703 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
704 [(set GR16:$dst, (add GR16:$src, 1)),
705 (implicit EFLAGS)]>,
706 OpSize, Requires<[In64BitMode]>;
707 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
708 [(set GR32:$dst, (add GR32:$src, 1)),
709 (implicit EFLAGS)]>,
710 Requires<[In64BitMode]>;
711 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
712 [(set GR16:$dst, (add GR16:$src, -1)),
713 (implicit EFLAGS)]>,
714 OpSize, Requires<[In64BitMode]>;
715 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
716 [(set GR32:$dst, (add GR32:$src, -1)),
717 (implicit EFLAGS)]>,
718 Requires<[In64BitMode]>;
719 } // isConvertibleToThreeAddress
721 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
722 // how to unfold them.
723 let isTwoAddress = 0, CodeSize = 2 in {
724 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
725 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
726 (implicit EFLAGS)]>,
727 OpSize, Requires<[In64BitMode]>;
728 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
729 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
730 (implicit EFLAGS)]>,
731 Requires<[In64BitMode]>;
732 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
733 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
734 (implicit EFLAGS)]>,
735 OpSize, Requires<[In64BitMode]>;
736 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
737 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
738 (implicit EFLAGS)]>,
739 Requires<[In64BitMode]>;
740 }
741 } // Defs = [EFLAGS], CodeSize
744 let Defs = [EFLAGS] in {
745 // Shift instructions
746 let isTwoAddress = 1 in {
747 let Uses = [CL] in
748 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
749 "shl{q}\t{%cl, $dst|$dst, %CL}",
750 [(set GR64:$dst, (shl GR64:$src, CL))]>;
751 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
752 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
753 "shl{q}\t{$src2, $dst|$dst, $src2}",
754 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
755 // NOTE: We don't include patterns for shifts of a register by one, because
756 // 'add reg,reg' is cheaper.
757 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
758 "shr{q}\t$dst", []>;
759 } // isTwoAddress
761 let Uses = [CL] in
762 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
763 "shl{q}\t{%cl, $dst|$dst, %CL}",
764 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
765 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
766 "shl{q}\t{$src, $dst|$dst, $src}",
767 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
768 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
769 "shl{q}\t$dst",
770 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
772 let isTwoAddress = 1 in {
773 let Uses = [CL] in
774 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
775 "shr{q}\t{%cl, $dst|$dst, %CL}",
776 [(set GR64:$dst, (srl GR64:$src, CL))]>;
777 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
778 "shr{q}\t{$src2, $dst|$dst, $src2}",
779 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
780 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
781 "shr{q}\t$dst",
782 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
783 } // isTwoAddress
785 let Uses = [CL] in
786 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
787 "shr{q}\t{%cl, $dst|$dst, %CL}",
788 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
789 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
790 "shr{q}\t{$src, $dst|$dst, $src}",
791 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
792 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
793 "shr{q}\t$dst",
794 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
796 let isTwoAddress = 1 in {
797 let Uses = [CL] in
798 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
799 "sar{q}\t{%cl, $dst|$dst, %CL}",
800 [(set GR64:$dst, (sra GR64:$src, CL))]>;
801 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
802 "sar{q}\t{$src2, $dst|$dst, $src2}",
803 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
804 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
805 "sar{q}\t$dst",
806 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
807 } // isTwoAddress
809 let Uses = [CL] in
810 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
811 "sar{q}\t{%cl, $dst|$dst, %CL}",
812 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
813 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
814 "sar{q}\t{$src, $dst|$dst, $src}",
815 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
816 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
817 "sar{q}\t$dst",
818 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
820 // Rotate instructions
821 let isTwoAddress = 1 in {
822 let Uses = [CL] in
823 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
824 "rol{q}\t{%cl, $dst|$dst, %CL}",
825 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
826 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
827 "rol{q}\t{$src2, $dst|$dst, $src2}",
828 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
829 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
830 "rol{q}\t$dst",
831 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
832 } // isTwoAddress
834 let Uses = [CL] in
835 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
836 "rol{q}\t{%cl, $dst|$dst, %CL}",
837 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
838 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
839 "rol{q}\t{$src, $dst|$dst, $src}",
840 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
841 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
842 "rol{q}\t$dst",
843 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
845 let isTwoAddress = 1 in {
846 let Uses = [CL] in
847 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
848 "ror{q}\t{%cl, $dst|$dst, %CL}",
849 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
850 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
851 "ror{q}\t{$src2, $dst|$dst, $src2}",
852 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
853 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
854 "ror{q}\t$dst",
855 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
856 } // isTwoAddress
858 let Uses = [CL] in
859 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
860 "ror{q}\t{%cl, $dst|$dst, %CL}",
861 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
862 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
863 "ror{q}\t{$src, $dst|$dst, $src}",
864 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
865 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
866 "ror{q}\t$dst",
867 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
869 // Double shift instructions (generalizations of rotate)
870 let isTwoAddress = 1 in {
871 let Uses = [CL] in {
872 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
873 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
874 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
875 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
876 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
877 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
878 }
880 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
881 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
882 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
883 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
884 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
885 (i8 imm:$src3)))]>,
886 TB;
887 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
888 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
889 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
890 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
891 (i8 imm:$src3)))]>,
892 TB;
893 } // isCommutable
894 } // isTwoAddress
896 let Uses = [CL] in {
897 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
898 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
899 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
900 addr:$dst)]>, TB;
901 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
902 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
903 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
904 addr:$dst)]>, TB;
905 }
906 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
907 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
908 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
909 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
910 (i8 imm:$src3)), addr:$dst)]>,
911 TB;
912 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
913 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
914 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
915 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
916 (i8 imm:$src3)), addr:$dst)]>,
917 TB;
918 } // Defs = [EFLAGS]
920 //===----------------------------------------------------------------------===//
921 // Logical Instructions...
922 //
924 let isTwoAddress = 1 , AddedComplexity = 15 in
925 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
926 [(set GR64:$dst, (not GR64:$src))]>;
927 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
928 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
930 let Defs = [EFLAGS] in {
931 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
932 "and{q}\t{$src, %rax|%rax, $src}", []>;
934 let isTwoAddress = 1 in {
935 let isCommutable = 1 in
936 def AND64rr : RI<0x21, MRMDestReg,
937 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
938 "and{q}\t{$src2, $dst|$dst, $src2}",
939 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
940 (implicit EFLAGS)]>;
941 def AND64rm : RI<0x23, MRMSrcMem,
942 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
943 "and{q}\t{$src2, $dst|$dst, $src2}",
944 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
945 (implicit EFLAGS)]>;
946 def AND64ri8 : RIi8<0x83, MRM4r,
947 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
948 "and{q}\t{$src2, $dst|$dst, $src2}",
949 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
950 (implicit EFLAGS)]>;
951 def AND64ri32 : RIi32<0x81, MRM4r,
952 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
953 "and{q}\t{$src2, $dst|$dst, $src2}",
954 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
955 (implicit EFLAGS)]>;
956 } // isTwoAddress
958 def AND64mr : RI<0x21, MRMDestMem,
959 (outs), (ins i64mem:$dst, GR64:$src),
960 "and{q}\t{$src, $dst|$dst, $src}",
961 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
962 (implicit EFLAGS)]>;
963 def AND64mi8 : RIi8<0x83, MRM4m,
964 (outs), (ins i64mem:$dst, i64i8imm :$src),
965 "and{q}\t{$src, $dst|$dst, $src}",
966 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
967 (implicit EFLAGS)]>;
968 def AND64mi32 : RIi32<0x81, MRM4m,
969 (outs), (ins i64mem:$dst, i64i32imm:$src),
970 "and{q}\t{$src, $dst|$dst, $src}",
971 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
972 (implicit EFLAGS)]>;
974 let isTwoAddress = 1 in {
975 let isCommutable = 1 in
976 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
977 "or{q}\t{$src2, $dst|$dst, $src2}",
978 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
979 (implicit EFLAGS)]>;
980 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
981 "or{q}\t{$src2, $dst|$dst, $src2}",
982 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
983 (implicit EFLAGS)]>;
984 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
985 "or{q}\t{$src2, $dst|$dst, $src2}",
986 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
987 (implicit EFLAGS)]>;
988 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
989 "or{q}\t{$src2, $dst|$dst, $src2}",
990 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
991 (implicit EFLAGS)]>;
992 } // isTwoAddress
994 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
995 "or{q}\t{$src, $dst|$dst, $src}",
996 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
997 (implicit EFLAGS)]>;
998 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
999 "or{q}\t{$src, $dst|$dst, $src}",
1000 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
1001 (implicit EFLAGS)]>;
1002 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1003 "or{q}\t{$src, $dst|$dst, $src}",
1004 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1005 (implicit EFLAGS)]>;
1007 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
1008 "or{q}\t{$src, %rax|%rax, $src}", []>;
1010 let isTwoAddress = 1 in {
1011 let isCommutable = 1 in
1012 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1013 "xor{q}\t{$src2, $dst|$dst, $src2}",
1014 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
1015 (implicit EFLAGS)]>;
1016 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1017 "xor{q}\t{$src2, $dst|$dst, $src2}",
1018 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
1019 (implicit EFLAGS)]>;
1020 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1021 "xor{q}\t{$src2, $dst|$dst, $src2}",
1022 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1023 (implicit EFLAGS)]>;
1024 def XOR64ri32 : RIi32<0x81, MRM6r,
1025 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1026 "xor{q}\t{$src2, $dst|$dst, $src2}",
1027 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1028 (implicit EFLAGS)]>;
1029 } // isTwoAddress
1031 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1032 "xor{q}\t{$src, $dst|$dst, $src}",
1033 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1034 (implicit EFLAGS)]>;
1035 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1036 "xor{q}\t{$src, $dst|$dst, $src}",
1037 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1038 (implicit EFLAGS)]>;
1039 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1040 "xor{q}\t{$src, $dst|$dst, $src}",
1041 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1042 (implicit EFLAGS)]>;
1044 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1045 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1047 } // Defs = [EFLAGS]
1049 //===----------------------------------------------------------------------===//
1050 // Comparison Instructions...
1051 //
1053 // Integer comparison
1054 let Defs = [EFLAGS] in {
1055 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1056 "test{q}\t{$src, %rax|%rax, $src}", []>;
1057 let isCommutable = 1 in
1058 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1059 "test{q}\t{$src2, $src1|$src1, $src2}",
1060 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1061 (implicit EFLAGS)]>;
1062 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1063 "test{q}\t{$src2, $src1|$src1, $src2}",
1064 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1065 (implicit EFLAGS)]>;
1066 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1067 (ins GR64:$src1, i64i32imm:$src2),
1068 "test{q}\t{$src2, $src1|$src1, $src2}",
1069 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1070 (implicit EFLAGS)]>;
1071 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1072 (ins i64mem:$src1, i64i32imm:$src2),
1073 "test{q}\t{$src2, $src1|$src1, $src2}",
1074 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1075 (implicit EFLAGS)]>;
1078 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1079 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1080 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1081 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1082 [(X86cmp GR64:$src1, GR64:$src2),
1083 (implicit EFLAGS)]>;
1084 def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1085 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1086 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1087 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1088 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1089 (implicit EFLAGS)]>;
1090 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1091 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1092 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1093 (implicit EFLAGS)]>;
1094 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1095 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1096 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1097 (implicit EFLAGS)]>;
1098 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1099 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1100 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1101 (implicit EFLAGS)]>;
1102 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1103 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1104 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1105 (implicit EFLAGS)]>;
1106 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1107 (ins i64mem:$src1, i64i32imm:$src2),
1108 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1109 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1110 (implicit EFLAGS)]>;
1111 } // Defs = [EFLAGS]
1113 // Bit tests.
1114 // TODO: BTC, BTR, and BTS
1115 let Defs = [EFLAGS] in {
1116 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1117 "bt{q}\t{$src2, $src1|$src1, $src2}",
1118 [(X86bt GR64:$src1, GR64:$src2),
1119 (implicit EFLAGS)]>, TB;
1121 // Unlike with the register+register form, the memory+register form of the
1122 // bt instruction does not ignore the high bits of the index. From ISel's
1123 // perspective, this is pretty bizarre. Disable these instructions for now.
1124 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1125 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1126 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1127 // (implicit EFLAGS)]>, TB;
1129 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1130 "bt{q}\t{$src2, $src1|$src1, $src2}",
1131 [(X86bt GR64:$src1, i64immSExt8:$src2),
1132 (implicit EFLAGS)]>, TB;
1133 // Note that these instructions don't need FastBTMem because that
1134 // only applies when the other operand is in a register. When it's
1135 // an immediate, bt is still fast.
1136 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1137 "bt{q}\t{$src2, $src1|$src1, $src2}",
1138 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1139 (implicit EFLAGS)]>, TB;
1140 } // Defs = [EFLAGS]
1142 // Conditional moves
1143 let Uses = [EFLAGS], isTwoAddress = 1 in {
1144 let isCommutable = 1 in {
1145 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1146 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1147 "cmovb\t{$src2, $dst|$dst, $src2}",
1148 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1149 X86_COND_B, EFLAGS))]>, TB;
1150 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1151 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1152 "cmovae\t{$src2, $dst|$dst, $src2}",
1153 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1154 X86_COND_AE, EFLAGS))]>, TB;
1155 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1156 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1157 "cmove\t{$src2, $dst|$dst, $src2}",
1158 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1159 X86_COND_E, EFLAGS))]>, TB;
1160 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1161 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1162 "cmovne\t{$src2, $dst|$dst, $src2}",
1163 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1164 X86_COND_NE, EFLAGS))]>, TB;
1165 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1166 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1167 "cmovbe\t{$src2, $dst|$dst, $src2}",
1168 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1169 X86_COND_BE, EFLAGS))]>, TB;
1170 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1171 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1172 "cmova\t{$src2, $dst|$dst, $src2}",
1173 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1174 X86_COND_A, EFLAGS))]>, TB;
1175 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1176 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1177 "cmovl\t{$src2, $dst|$dst, $src2}",
1178 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1179 X86_COND_L, EFLAGS))]>, TB;
1180 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1181 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1182 "cmovge\t{$src2, $dst|$dst, $src2}",
1183 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1184 X86_COND_GE, EFLAGS))]>, TB;
1185 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1186 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1187 "cmovle\t{$src2, $dst|$dst, $src2}",
1188 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1189 X86_COND_LE, EFLAGS))]>, TB;
1190 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1191 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1192 "cmovg\t{$src2, $dst|$dst, $src2}",
1193 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1194 X86_COND_G, EFLAGS))]>, TB;
1195 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1196 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1197 "cmovs\t{$src2, $dst|$dst, $src2}",
1198 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1199 X86_COND_S, EFLAGS))]>, TB;
1200 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1201 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1202 "cmovns\t{$src2, $dst|$dst, $src2}",
1203 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1204 X86_COND_NS, EFLAGS))]>, TB;
1205 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1206 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1207 "cmovp\t{$src2, $dst|$dst, $src2}",
1208 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1209 X86_COND_P, EFLAGS))]>, TB;
1210 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1211 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1212 "cmovnp\t{$src2, $dst|$dst, $src2}",
1213 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1214 X86_COND_NP, EFLAGS))]>, TB;
1215 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1216 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1217 "cmovo\t{$src2, $dst|$dst, $src2}",
1218 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1219 X86_COND_O, EFLAGS))]>, TB;
1220 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1221 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1222 "cmovno\t{$src2, $dst|$dst, $src2}",
1223 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1224 X86_COND_NO, EFLAGS))]>, TB;
1225 } // isCommutable = 1
1227 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1228 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1229 "cmovb\t{$src2, $dst|$dst, $src2}",
1230 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1231 X86_COND_B, EFLAGS))]>, TB;
1232 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1233 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1234 "cmovae\t{$src2, $dst|$dst, $src2}",
1235 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1236 X86_COND_AE, EFLAGS))]>, TB;
1237 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1238 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1239 "cmove\t{$src2, $dst|$dst, $src2}",
1240 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1241 X86_COND_E, EFLAGS))]>, TB;
1242 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1243 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1244 "cmovne\t{$src2, $dst|$dst, $src2}",
1245 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1246 X86_COND_NE, EFLAGS))]>, TB;
1247 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1248 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1249 "cmovbe\t{$src2, $dst|$dst, $src2}",
1250 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1251 X86_COND_BE, EFLAGS))]>, TB;
1252 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1253 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1254 "cmova\t{$src2, $dst|$dst, $src2}",
1255 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1256 X86_COND_A, EFLAGS))]>, TB;
1257 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1258 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1259 "cmovl\t{$src2, $dst|$dst, $src2}",
1260 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1261 X86_COND_L, EFLAGS))]>, TB;
1262 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1263 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1264 "cmovge\t{$src2, $dst|$dst, $src2}",
1265 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1266 X86_COND_GE, EFLAGS))]>, TB;
1267 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1268 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1269 "cmovle\t{$src2, $dst|$dst, $src2}",
1270 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1271 X86_COND_LE, EFLAGS))]>, TB;
1272 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1273 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1274 "cmovg\t{$src2, $dst|$dst, $src2}",
1275 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1276 X86_COND_G, EFLAGS))]>, TB;
1277 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1278 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1279 "cmovs\t{$src2, $dst|$dst, $src2}",
1280 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1281 X86_COND_S, EFLAGS))]>, TB;
1282 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1283 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1284 "cmovns\t{$src2, $dst|$dst, $src2}",
1285 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1286 X86_COND_NS, EFLAGS))]>, TB;
1287 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1288 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1289 "cmovp\t{$src2, $dst|$dst, $src2}",
1290 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1291 X86_COND_P, EFLAGS))]>, TB;
1292 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1293 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1294 "cmovnp\t{$src2, $dst|$dst, $src2}",
1295 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1296 X86_COND_NP, EFLAGS))]>, TB;
1297 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1298 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1299 "cmovo\t{$src2, $dst|$dst, $src2}",
1300 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1301 X86_COND_O, EFLAGS))]>, TB;
1302 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1303 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1304 "cmovno\t{$src2, $dst|$dst, $src2}",
1305 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1306 X86_COND_NO, EFLAGS))]>, TB;
1307 } // isTwoAddress
1309 //===----------------------------------------------------------------------===//
1310 // Conversion Instructions...
1311 //
1313 // f64 -> signed i64
1314 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1315 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1316 [(set GR64:$dst,
1317 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1318 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1319 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1320 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1321 (load addr:$src)))]>;
1322 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1323 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1324 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1325 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1326 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1327 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1328 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1329 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1330 [(set GR64:$dst,
1331 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1332 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1333 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1334 [(set GR64:$dst,
1335 (int_x86_sse2_cvttsd2si64
1336 (load addr:$src)))]>;
1338 // Signed i64 -> f64
1339 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1340 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1341 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1342 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1343 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1344 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1346 let isTwoAddress = 1 in {
1347 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1348 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1349 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1350 [(set VR128:$dst,
1351 (int_x86_sse2_cvtsi642sd VR128:$src1,
1352 GR64:$src2))]>;
1353 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1354 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1355 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1356 [(set VR128:$dst,
1357 (int_x86_sse2_cvtsi642sd VR128:$src1,
1358 (loadi64 addr:$src2)))]>;
1359 } // isTwoAddress
1361 // Signed i64 -> f32
1362 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1363 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1364 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1365 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1366 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1367 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1369 let isTwoAddress = 1 in {
1370 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1371 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1372 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1373 [(set VR128:$dst,
1374 (int_x86_sse_cvtsi642ss VR128:$src1,
1375 GR64:$src2))]>;
1376 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1377 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1378 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1379 [(set VR128:$dst,
1380 (int_x86_sse_cvtsi642ss VR128:$src1,
1381 (loadi64 addr:$src2)))]>;
1382 }
1384 // f32 -> signed i64
1385 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1386 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1387 [(set GR64:$dst,
1388 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1389 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1390 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1391 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1392 (load addr:$src)))]>;
1393 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1394 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1395 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1396 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1397 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1398 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1399 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1400 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1401 [(set GR64:$dst,
1402 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1403 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1404 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1405 [(set GR64:$dst,
1406 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1408 //===----------------------------------------------------------------------===//
1409 // Alias Instructions
1410 //===----------------------------------------------------------------------===//
1412 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1413 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1414 // encoding.
1415 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1416 // when we have a better way to specify isel priority.
1417 let AddedComplexity = 1 in
1418 def : Pat<(i64 0),
1419 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1422 // Materialize i64 constant where top 32-bits are zero.
1423 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1424 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1425 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1426 [(set GR64:$dst, i64immZExt32:$src)]>;
1428 //===----------------------------------------------------------------------===//
1429 // Thread Local Storage Instructions
1430 //===----------------------------------------------------------------------===//
1432 // All calls clobber the non-callee saved registers. RSP is marked as
1433 // a use to prevent stack-pointer assignments that appear immediately
1434 // before calls from potentially appearing dead.
1435 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1436 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1437 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1438 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1439 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1440 Uses = [RSP] in
1441 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1442 ".byte\t0x66; "
1443 "leaq\t$sym(%rip), %rdi; "
1444 ".word\t0x6666; "
1445 "rex64; "
1446 "call\t__tls_get_addr@PLT",
1447 [(X86tlsaddr tls64addr:$sym)]>,
1448 Requires<[In64BitMode]>;
1450 let AddedComplexity = 5, isCodeGenOnly = 1 in
1451 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1452 "movq\t%gs:$src, $dst",
1453 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1455 let AddedComplexity = 5, isCodeGenOnly = 1 in
1456 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1457 "movq\t%fs:$src, $dst",
1458 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1460 //===----------------------------------------------------------------------===//
1461 // Atomic Instructions
1462 //===----------------------------------------------------------------------===//
1464 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1465 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1466 "lock\n\t"
1467 "cmpxchgq\t$swap,$ptr",
1468 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1469 }
1471 let Constraints = "$val = $dst" in {
1472 let Defs = [EFLAGS] in
1473 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1474 "lock\n\t"
1475 "xadd\t$val, $ptr",
1476 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1477 TB, LOCK;
1479 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1480 "xchg\t$val, $ptr",
1481 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1482 }
1484 // Optimized codegen when the non-memory output is not used.
1485 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1486 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1487 "lock\n\t"
1488 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1489 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1490 (ins i64mem:$dst, i64i8imm :$src2),
1491 "lock\n\t"
1492 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1493 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1494 (ins i64mem:$dst, i64i32imm :$src2),
1495 "lock\n\t"
1496 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1497 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1498 "lock\n\t"
1499 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1500 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1501 (ins i64mem:$dst, i64i8imm :$src2),
1502 "lock\n\t"
1503 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1504 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1505 (ins i64mem:$dst, i64i32imm:$src2),
1506 "lock\n\t"
1507 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1508 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1509 "lock\n\t"
1510 "inc{q}\t$dst", []>, LOCK;
1511 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1512 "lock\n\t"
1513 "dec{q}\t$dst", []>, LOCK;
1515 // Atomic exchange, and, or, xor
1516 let Constraints = "$val = $dst", Defs = [EFLAGS],
1517 usesCustomDAGSchedInserter = 1 in {
1518 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1519 "#ATOMAND64 PSEUDO!",
1520 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1521 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1522 "#ATOMOR64 PSEUDO!",
1523 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1524 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1525 "#ATOMXOR64 PSEUDO!",
1526 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1527 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1528 "#ATOMNAND64 PSEUDO!",
1529 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1530 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1531 "#ATOMMIN64 PSEUDO!",
1532 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1533 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1534 "#ATOMMAX64 PSEUDO!",
1535 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1536 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1537 "#ATOMUMIN64 PSEUDO!",
1538 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1539 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1540 "#ATOMUMAX64 PSEUDO!",
1541 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1542 }
1544 // Segmentation support instructions
1546 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
1547 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
1548 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1549 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
1550 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
1552 //===----------------------------------------------------------------------===//
1553 // Non-Instruction Patterns
1554 //===----------------------------------------------------------------------===//
1556 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1557 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1558 // 'movabs' predicate should handle this sort of thing.
1559 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1560 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1561 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1562 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1563 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1564 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1565 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1566 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1568 // In static codegen with small code model, we can get the address of a label
1569 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1570 // the MOV64ri64i32 should accept these.
1571 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1572 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1573 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1574 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1575 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1576 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1577 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1578 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1580 // In kernel code model, we can get the address of a label
1581 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1582 // the MOV64ri32 should accept these.
1583 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1584 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1585 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1586 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1587 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1588 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1589 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1590 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1592 // If we have small model and -static mode, it is safe to store global addresses
1593 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1594 // for MOV64mi32 should handle this sort of thing.
1595 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1596 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1597 Requires<[NearData, IsStatic]>;
1598 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1599 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1600 Requires<[NearData, IsStatic]>;
1601 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1602 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1603 Requires<[NearData, IsStatic]>;
1604 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1605 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1606 Requires<[NearData, IsStatic]>;
1608 // Calls
1609 // Direct PC relative function call for small code model. 32-bit displacement
1610 // sign extended to 64-bit.
1611 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1612 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1613 def : Pat<(X86call (i64 texternalsym:$dst)),
1614 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1616 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1617 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1618 def : Pat<(X86call (i64 texternalsym:$dst)),
1619 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1621 // tailcall stuff
1622 def : Pat<(X86tcret GR64:$dst, imm:$off),
1623 (TCRETURNri64 GR64:$dst, imm:$off)>;
1625 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1626 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1628 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1629 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1631 // Comparisons.
1633 // TEST R,R is smaller than CMP R,0
1634 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1635 (TEST64rr GR64:$src1, GR64:$src1)>;
1637 // Conditional moves with folded loads with operands swapped and conditions
1638 // inverted.
1639 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1640 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1641 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1642 (CMOVB64rm GR64:$src2, addr:$src1)>;
1643 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1644 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1645 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1646 (CMOVE64rm GR64:$src2, addr:$src1)>;
1647 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1648 (CMOVA64rm GR64:$src2, addr:$src1)>;
1649 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1650 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1651 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1652 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1653 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1654 (CMOVL64rm GR64:$src2, addr:$src1)>;
1655 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1656 (CMOVG64rm GR64:$src2, addr:$src1)>;
1657 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1658 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1659 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1660 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1661 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1662 (CMOVP64rm GR64:$src2, addr:$src1)>;
1663 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1664 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1665 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1666 (CMOVS64rm GR64:$src2, addr:$src1)>;
1667 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1668 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1669 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1670 (CMOVO64rm GR64:$src2, addr:$src1)>;
1672 // zextload bool -> zextload byte
1673 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1675 // extload
1676 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1677 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1678 // partial-register updates.
1679 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1680 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1681 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1682 // For other extloads, use subregs, since the high contents of the register are
1683 // defined after an extload.
1684 def : Pat<(extloadi64i32 addr:$src),
1685 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1686 x86_subreg_32bit)>;
1688 // anyext. Define these to do an explicit zero-extend to
1689 // avoid partial-register updates.
1690 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1691 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1692 def : Pat<(i64 (anyext GR32:$src)),
1693 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1695 //===----------------------------------------------------------------------===//
1696 // Some peepholes
1697 //===----------------------------------------------------------------------===//
1699 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1700 // +128 doesn't, so in this special case use a sub instead of an add.
1701 def : Pat<(add GR64:$src1, 128),
1702 (SUB64ri8 GR64:$src1, -128)>;
1703 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1704 (SUB64mi8 addr:$dst, -128)>;
1706 // The same trick applies for 32-bit immediate fields in 64-bit
1707 // instructions.
1708 def : Pat<(add GR64:$src1, 0x0000000080000000),
1709 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1710 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1711 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1713 // r & (2^32-1) ==> movz
1714 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1715 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1716 // r & (2^16-1) ==> movz
1717 def : Pat<(and GR64:$src, 0xffff),
1718 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1719 // r & (2^8-1) ==> movz
1720 def : Pat<(and GR64:$src, 0xff),
1721 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1722 // r & (2^8-1) ==> movz
1723 def : Pat<(and GR32:$src1, 0xff),
1724 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1725 Requires<[In64BitMode]>;
1726 // r & (2^8-1) ==> movz
1727 def : Pat<(and GR16:$src1, 0xff),
1728 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1729 Requires<[In64BitMode]>;
1731 // sext_inreg patterns
1732 def : Pat<(sext_inreg GR64:$src, i32),
1733 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1734 def : Pat<(sext_inreg GR64:$src, i16),
1735 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1736 def : Pat<(sext_inreg GR64:$src, i8),
1737 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1738 def : Pat<(sext_inreg GR32:$src, i8),
1739 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1740 Requires<[In64BitMode]>;
1741 def : Pat<(sext_inreg GR16:$src, i8),
1742 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1743 Requires<[In64BitMode]>;
1745 // trunc patterns
1746 def : Pat<(i32 (trunc GR64:$src)),
1747 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1748 def : Pat<(i16 (trunc GR64:$src)),
1749 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1750 def : Pat<(i8 (trunc GR64:$src)),
1751 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1752 def : Pat<(i8 (trunc GR32:$src)),
1753 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1754 Requires<[In64BitMode]>;
1755 def : Pat<(i8 (trunc GR16:$src)),
1756 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1757 Requires<[In64BitMode]>;
1759 // h-register tricks.
1760 // For now, be conservative on x86-64 and use an h-register extract only if the
1761 // value is immediately zero-extended or stored, which are somewhat common
1762 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1763 // from being allocated in the same instruction as the h register, as there's
1764 // currently no way to describe this requirement to the register allocator.
1766 // h-register extract and zero-extend.
1767 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1768 (SUBREG_TO_REG
1769 (i64 0),
1770 (MOVZX32_NOREXrr8
1771 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1772 x86_subreg_8bit_hi)),
1773 x86_subreg_32bit)>;
1774 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1775 (MOVZX32_NOREXrr8
1776 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1777 x86_subreg_8bit_hi))>,
1778 Requires<[In64BitMode]>;
1779 def : Pat<(srl_su GR16:$src, (i8 8)),
1780 (EXTRACT_SUBREG
1781 (MOVZX32_NOREXrr8
1782 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1783 x86_subreg_8bit_hi)),
1784 x86_subreg_16bit)>,
1785 Requires<[In64BitMode]>;
1786 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1787 (MOVZX32_NOREXrr8
1788 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1789 x86_subreg_8bit_hi))>,
1790 Requires<[In64BitMode]>;
1791 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1792 (MOVZX32_NOREXrr8
1793 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1794 x86_subreg_8bit_hi))>,
1795 Requires<[In64BitMode]>;
1796 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1797 (SUBREG_TO_REG
1798 (i64 0),
1799 (MOVZX32_NOREXrr8
1800 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1801 x86_subreg_8bit_hi)),
1802 x86_subreg_32bit)>;
1803 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1804 (SUBREG_TO_REG
1805 (i64 0),
1806 (MOVZX32_NOREXrr8
1807 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1808 x86_subreg_8bit_hi)),
1809 x86_subreg_32bit)>;
1811 // h-register extract and store.
1812 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1813 (MOV8mr_NOREX
1814 addr:$dst,
1815 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1816 x86_subreg_8bit_hi))>;
1817 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1818 (MOV8mr_NOREX
1819 addr:$dst,
1820 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1821 x86_subreg_8bit_hi))>,
1822 Requires<[In64BitMode]>;
1823 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1824 (MOV8mr_NOREX
1825 addr:$dst,
1826 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1827 x86_subreg_8bit_hi))>,
1828 Requires<[In64BitMode]>;
1830 // (shl x, 1) ==> (add x, x)
1831 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1833 // (shl x (and y, 63)) ==> (shl x, y)
1834 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1835 (SHL64rCL GR64:$src1)>;
1836 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1837 (SHL64mCL addr:$dst)>;
1839 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1840 (SHR64rCL GR64:$src1)>;
1841 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1842 (SHR64mCL addr:$dst)>;
1844 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1845 (SAR64rCL GR64:$src1)>;
1846 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1847 (SAR64mCL addr:$dst)>;
1849 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1850 def : Pat<(or (srl GR64:$src1, CL:$amt),
1851 (shl GR64:$src2, (sub 64, CL:$amt))),
1852 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1854 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1855 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1856 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1858 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1859 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1860 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1862 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1863 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1864 addr:$dst),
1865 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1867 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1868 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1870 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1871 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1872 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1874 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1875 def : Pat<(or (shl GR64:$src1, CL:$amt),
1876 (srl GR64:$src2, (sub 64, CL:$amt))),
1877 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1879 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1880 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1881 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1883 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1884 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1885 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1887 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1888 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1889 addr:$dst),
1890 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1892 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1893 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1895 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1896 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1897 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1899 // X86 specific add which produces a flag.
1900 def : Pat<(addc GR64:$src1, GR64:$src2),
1901 (ADD64rr GR64:$src1, GR64:$src2)>;
1902 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1903 (ADD64rm GR64:$src1, addr:$src2)>;
1904 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1905 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1906 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1907 (ADD64ri32 GR64:$src1, imm:$src2)>;
1909 def : Pat<(subc GR64:$src1, GR64:$src2),
1910 (SUB64rr GR64:$src1, GR64:$src2)>;
1911 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1912 (SUB64rm GR64:$src1, addr:$src2)>;
1913 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1914 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1915 def : Pat<(subc GR64:$src1, imm:$src2),
1916 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1918 //===----------------------------------------------------------------------===//
1919 // EFLAGS-defining Patterns
1920 //===----------------------------------------------------------------------===//
1922 // Register-Register Addition with EFLAGS result
1923 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1924 (implicit EFLAGS)),
1925 (ADD64rr GR64:$src1, GR64:$src2)>;
1927 // Register-Integer Addition with EFLAGS result
1928 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1929 (implicit EFLAGS)),
1930 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1931 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1932 (implicit EFLAGS)),
1933 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1935 // Register-Memory Addition with EFLAGS result
1936 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1937 (implicit EFLAGS)),
1938 (ADD64rm GR64:$src1, addr:$src2)>;
1940 // Memory-Register Addition with EFLAGS result
1941 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1942 addr:$dst),
1943 (implicit EFLAGS)),
1944 (ADD64mr addr:$dst, GR64:$src2)>;
1945 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1946 addr:$dst),
1947 (implicit EFLAGS)),
1948 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1949 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1950 addr:$dst),
1951 (implicit EFLAGS)),
1952 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1954 // Register-Register Subtraction with EFLAGS result
1955 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1956 (implicit EFLAGS)),
1957 (SUB64rr GR64:$src1, GR64:$src2)>;
1959 // Register-Memory Subtraction with EFLAGS result
1960 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1961 (implicit EFLAGS)),
1962 (SUB64rm GR64:$src1, addr:$src2)>;
1964 // Register-Integer Subtraction with EFLAGS result
1965 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1966 (implicit EFLAGS)),
1967 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1968 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1969 (implicit EFLAGS)),
1970 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1972 // Memory-Register Subtraction with EFLAGS result
1973 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1974 addr:$dst),
1975 (implicit EFLAGS)),
1976 (SUB64mr addr:$dst, GR64:$src2)>;
1978 // Memory-Integer Subtraction with EFLAGS result
1979 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1980 addr:$dst),
1981 (implicit EFLAGS)),
1982 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1983 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1984 addr:$dst),
1985 (implicit EFLAGS)),
1986 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1988 // Register-Register Signed Integer Multiplication with EFLAGS result
1989 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1990 (implicit EFLAGS)),
1991 (IMUL64rr GR64:$src1, GR64:$src2)>;
1993 // Register-Memory Signed Integer Multiplication with EFLAGS result
1994 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1995 (implicit EFLAGS)),
1996 (IMUL64rm GR64:$src1, addr:$src2)>;
1998 // Register-Integer Signed Integer Multiplication with EFLAGS result
1999 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
2000 (implicit EFLAGS)),
2001 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
2002 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
2003 (implicit EFLAGS)),
2004 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
2006 // Memory-Integer Signed Integer Multiplication with EFLAGS result
2007 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
2008 (implicit EFLAGS)),
2009 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
2010 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
2011 (implicit EFLAGS)),
2012 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
2014 // INC and DEC with EFLAGS result. Note that these do not set CF.
2015 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
2016 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2017 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
2018 (implicit EFLAGS)),
2019 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2020 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
2021 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
2022 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
2023 (implicit EFLAGS)),
2024 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
2026 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
2027 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2028 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
2029 (implicit EFLAGS)),
2030 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2031 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2032 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2033 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2034 (implicit EFLAGS)),
2035 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2037 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2038 (INC64r GR64:$src)>;
2039 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2040 (implicit EFLAGS)),
2041 (INC64m addr:$dst)>;
2042 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2043 (DEC64r GR64:$src)>;
2044 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2045 (implicit EFLAGS)),
2046 (DEC64m addr:$dst)>;
2048 //===----------------------------------------------------------------------===//
2049 // X86-64 SSE Instructions
2050 //===----------------------------------------------------------------------===//
2052 // Move instructions...
2054 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2055 "mov{d|q}\t{$src, $dst|$dst, $src}",
2056 [(set VR128:$dst,
2057 (v2i64 (scalar_to_vector GR64:$src)))]>;
2058 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2059 "mov{d|q}\t{$src, $dst|$dst, $src}",
2060 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2061 (iPTR 0)))]>;
2063 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2064 "mov{d|q}\t{$src, $dst|$dst, $src}",
2065 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2066 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2067 "movq\t{$src, $dst|$dst, $src}",
2068 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2070 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2071 "mov{d|q}\t{$src, $dst|$dst, $src}",
2072 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2073 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2074 "movq\t{$src, $dst|$dst, $src}",
2075 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2077 //===----------------------------------------------------------------------===//
2078 // X86-64 SSE4.1 Instructions
2079 //===----------------------------------------------------------------------===//
2081 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2082 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2083 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2084 (ins VR128:$src1, i32i8imm:$src2),
2085 !strconcat(OpcodeStr,
2086 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2087 [(set GR64:$dst,
2088 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2089 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2090 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2091 !strconcat(OpcodeStr,
2092 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2093 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2094 addr:$dst)]>, OpSize, REX_W;
2095 }
2097 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2099 let isTwoAddress = 1 in {
2100 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2101 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2102 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2103 !strconcat(OpcodeStr,
2104 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2105 [(set VR128:$dst,
2106 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2107 OpSize, REX_W;
2108 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2109 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2110 !strconcat(OpcodeStr,
2111 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2112 [(set VR128:$dst,
2113 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2114 imm:$src3)))]>, OpSize, REX_W;
2115 }
2116 }
2118 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2120 // -disable-16bit support.
2121 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2122 (MOV16mi addr:$dst, imm:$src)>;
2123 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2124 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2125 def : Pat<(i64 (sextloadi16 addr:$dst)),
2126 (MOVSX64rm16 addr:$dst)>;
2127 def : Pat<(i64 (zextloadi16 addr:$dst)),
2128 (MOVZX64rm16 addr:$dst)>;
2129 def : Pat<(i64 (extloadi16 addr:$dst)),
2130 (MOVZX64rm16 addr:$dst)>;