Fix comment for consistency sake.
[llvm/avr.git] / lib / CodeGen / DeadMachineInstructionElim.cpp
blobe104d8cec0e415eeb2895e25f46068ecc604e988
1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/Passes.h"
15 #include "llvm/Pass.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 using namespace llvm;
25 namespace {
26 class VISIBILITY_HIDDEN DeadMachineInstructionElim :
27 public MachineFunctionPass {
28 virtual bool runOnMachineFunction(MachineFunction &MF);
30 const TargetRegisterInfo *TRI;
31 const MachineRegisterInfo *MRI;
32 const TargetInstrInfo *TII;
33 BitVector LivePhysRegs;
35 public:
36 static char ID; // Pass identification, replacement for typeid
37 DeadMachineInstructionElim() : MachineFunctionPass(&ID) {}
39 private:
40 bool isDead(const MachineInstr *MI) const;
43 char DeadMachineInstructionElim::ID = 0;
45 static RegisterPass<DeadMachineInstructionElim>
46 Y("dead-mi-elimination",
47 "Remove dead machine instructions");
49 FunctionPass *llvm::createDeadMachineInstructionElimPass() {
50 return new DeadMachineInstructionElim();
53 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
54 // Don't delete instructions with side effects.
55 bool SawStore = false;
56 if (!MI->isSafeToMove(TII, SawStore))
57 return false;
59 // Examine each operand.
60 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
61 const MachineOperand &MO = MI->getOperand(i);
62 if (MO.isReg() && MO.isDef()) {
63 unsigned Reg = MO.getReg();
64 if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
65 LivePhysRegs[Reg] : !MRI->use_empty(Reg)) {
66 // This def has a use. Don't delete the instruction!
67 return false;
72 // If there are no defs with uses, the instruction is dead.
73 return true;
76 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
77 bool AnyChanges = false;
78 MRI = &MF.getRegInfo();
79 TRI = MF.getTarget().getRegisterInfo();
80 TII = MF.getTarget().getInstrInfo();
82 // Compute a bitvector to represent all non-allocatable physregs.
83 BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
84 NonAllocatableRegs.flip();
86 // Loop over all instructions in all blocks, from bottom to top, so that it's
87 // more likely that chains of dependent but ultimately dead instructions will
88 // be cleaned up.
89 for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
90 I != E; ++I) {
91 MachineBasicBlock *MBB = &*I;
93 // Start out assuming that all non-allocatable registers are live
94 // out of this block.
95 LivePhysRegs = NonAllocatableRegs;
97 // Also add any explicit live-out physregs for this block.
98 if (!MBB->empty() && MBB->back().getDesc().isReturn())
99 for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
100 LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
101 unsigned Reg = *LOI;
102 if (TargetRegisterInfo::isPhysicalRegister(Reg))
103 LivePhysRegs.set(Reg);
106 // Now scan the instructions and delete dead ones, tracking physreg
107 // liveness as we go.
108 for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
109 MIE = MBB->rend(); MII != MIE; ) {
110 MachineInstr *MI = &*MII;
112 // If the instruction is dead, delete it!
113 if (isDead(MI)) {
114 DEBUG(errs() << "DeadMachineInstructionElim: DELETING: " << *MI);
115 AnyChanges = true;
116 MI->eraseFromParent();
117 MIE = MBB->rend();
118 // MII is now pointing to the next instruction to process,
119 // so don't increment it.
120 continue;
123 // Record the physreg defs.
124 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
125 const MachineOperand &MO = MI->getOperand(i);
126 if (MO.isReg() && MO.isDef()) {
127 unsigned Reg = MO.getReg();
128 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
129 LivePhysRegs.reset(Reg);
130 // Check the subreg set, not the alias set, because a def
131 // of a super-register may still be partially live after
132 // this def.
133 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
134 *SubRegs; ++SubRegs)
135 LivePhysRegs.reset(*SubRegs);
139 // Record the physreg uses, after the defs, in case a physreg is
140 // both defined and used in the same instruction.
141 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
142 const MachineOperand &MO = MI->getOperand(i);
143 if (MO.isReg() && MO.isUse()) {
144 unsigned Reg = MO.getReg();
145 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
146 LivePhysRegs.set(Reg);
147 for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
148 *AliasSet; ++AliasSet)
149 LivePhysRegs.set(*AliasSet);
154 // We didn't delete the current instruction, so increment MII to
155 // the next one.
156 ++MII;
160 LivePhysRegs.clear();
161 return AnyChanges;