lib/CodeGen/MachineVerifier.cpp

   1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Pass to verify generated machine code. The following is checked:
  11 //
  12 // Operand counts: All explicit operands must be present.
  13 //
  14 // Register classes: All physical and virtual register operands must be
  15 // compatible with the register class required by the instruction descriptor.
  16 //
  17 // Register live intervals: Registers must be defined only once, and must be
  18 // defined before use.
  19 //
  20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
  21 // command-line option -verify-machineinstrs, or by defining the environment
  22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
  23 // the verifier errors.
  24 //===----------------------------------------------------------------------===//
  25
  26 #include "llvm/Function.h"
  27 #include "llvm/CodeGen/LiveVariables.h"
  28 #include "llvm/CodeGen/MachineFunctionPass.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/CodeGen/Passes.h"
  32 #include "llvm/Target/TargetMachine.h"
  33 #include "llvm/Target/TargetRegisterInfo.h"
  34 #include "llvm/Target/TargetInstrInfo.h"
  35 #include "llvm/ADT/DenseSet.h"
  36 #include "llvm/ADT/SetOperations.h"
  37 #include "llvm/ADT/SmallVector.h"
  38 #include "llvm/Support/Compiler.h"
  39 #include "llvm/Support/Debug.h"
  40 #include "llvm/Support/ErrorHandling.h"
  41 #include "llvm/Support/raw_ostream.h"
  42 using namespace llvm;
  43
  44 namespace {
  45   struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
  46     static char ID; // Pass ID, replacement for typeid
  47
  48     MachineVerifier(bool allowDoubleDefs = false) :
  49       MachineFunctionPass(&ID),
  50       allowVirtDoubleDefs(allowDoubleDefs),
  51       allowPhysDoubleDefs(allowDoubleDefs),
  52       OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
  53         {}
  54
  55     void getAnalysisUsage(AnalysisUsage &AU) const {
  56       AU.setPreservesAll();
  57       MachineFunctionPass::getAnalysisUsage(AU);
  58     }
  59
  60     bool runOnMachineFunction(MachineFunction &MF);
  61
  62     const bool allowVirtDoubleDefs;
  63     const bool allowPhysDoubleDefs;
  64
  65     const char *const OutFileName;
  66     raw_ostream *OS;
  67     const MachineFunction *MF;
  68     const TargetMachine *TM;
  69     const TargetRegisterInfo *TRI;
  70     const MachineRegisterInfo *MRI;
  71
  72     unsigned foundErrors;
  73
  74     typedef SmallVector<unsigned, 16> RegVector;
  75     typedef DenseSet<unsigned> RegSet;
  76     typedef DenseMap<unsigned, const MachineInstr*> RegMap;
  77
  78     BitVector regsReserved;
  79     RegSet regsLive;
  80     RegVector regsDefined, regsDead, regsKilled;
  81     RegSet regsLiveInButUnused;
  82
  83     // Add Reg and any sub-registers to RV
  84     void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
  85       RV.push_back(Reg);
  86       if (TargetRegisterInfo::isPhysicalRegister(Reg))
  87         for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
  88           RV.push_back(*R);
  89     }
  90
  91     struct BBInfo {
  92       // Is this MBB reachable from the MF entry point?
  93       bool reachable;
  94
  95       // Vregs that must be live in because they are used without being
  96       // defined. Map value is the user.
  97       RegMap vregsLiveIn;
  98
  99       // Vregs that must be dead in because they are defined without being
 100       // killed first. Map value is the defining instruction.
 101       RegMap vregsDeadIn;
 102
 103       // Regs killed in MBB. They may be defined again, and will then be in both
 104       // regsKilled and regsLiveOut.
 105       RegSet regsKilled;
 106
 107       // Regs defined in MBB and live out. Note that vregs passing through may
 108       // be live out without being mentioned here.
 109       RegSet regsLiveOut;
 110
 111       // Vregs that pass through MBB untouched. This set is disjoint from
 112       // regsKilled and regsLiveOut.
 113       RegSet vregsPassed;
 114
 115       BBInfo() : reachable(false) {}
 116
 117       // Add register to vregsPassed if it belongs there. Return true if
 118       // anything changed.
 119       bool addPassed(unsigned Reg) {
 120         if (!TargetRegisterInfo::isVirtualRegister(Reg))
 121           return false;
 122         if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
 123           return false;
 124         return vregsPassed.insert(Reg).second;
 125       }
 126
 127       // Same for a full set.
 128       bool addPassed(const RegSet &RS) {
 129         bool changed = false;
 130         for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
 131           if (addPassed(*I))
 132             changed = true;
 133         return changed;
 134       }
 135
 136       // Live-out registers are either in regsLiveOut or vregsPassed.
 137       bool isLiveOut(unsigned Reg) const {
 138         return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
 139       }
 140     };
 141
 142     // Extra register info per MBB.
 143     DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
 144
 145     bool isReserved(unsigned Reg) {
 146       return Reg < regsReserved.size() && regsReserved.test(Reg);
 147     }
 148
 149     void visitMachineFunctionBefore();
 150     void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
 151     void visitMachineInstrBefore(const MachineInstr *MI);
 152     void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
 153     void visitMachineInstrAfter(const MachineInstr *MI);
 154     void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
 155     void visitMachineFunctionAfter();
 156
 157     void report(const char *msg, const MachineFunction *MF);
 158     void report(const char *msg, const MachineBasicBlock *MBB);
 159     void report(const char *msg, const MachineInstr *MI);
 160     void report(const char *msg, const MachineOperand *MO, unsigned MONum);
 161
 162     void markReachable(const MachineBasicBlock *MBB);
 163     void calcMaxRegsPassed();
 164     void calcMinRegsPassed();
 165     void checkPHIOps(const MachineBasicBlock *MBB);
 166   };
 167 }
 168
 169 char MachineVerifier::ID = 0;
 170 static RegisterPass<MachineVerifier>
 171 MachineVer("machineverifier", "Verify generated machine code");
 172 static const PassInfo *const MachineVerifyID = &MachineVer;
 173
 174 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
 175   return new MachineVerifier(allowPhysDoubleDefs);
 176 }
 177
 178 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
 179   raw_ostream *OutFile = 0;
 180   if (OutFileName) {
 181     std::string ErrorInfo;
 182     OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
 183                                  raw_fd_ostream::F_Append);
 184     if (!ErrorInfo.empty()) {
 185       errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
 186       exit(1);
 187     }
 188
 189     OS = OutFile;
 190   } else {
 191     OS = &errs();
 192   }
 193
 194   foundErrors = 0;
 195
 196   this->MF = &MF;
 197   TM = &MF.getTarget();
 198   TRI = TM->getRegisterInfo();
 199   MRI = &MF.getRegInfo();
 200
 201   visitMachineFunctionBefore();
 202   for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
 203        MFI!=MFE; ++MFI) {
 204     visitMachineBasicBlockBefore(MFI);
 205     for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
 206            MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
 207       visitMachineInstrBefore(MBBI);
 208       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
 209         visitMachineOperand(&MBBI->getOperand(I), I);
 210       visitMachineInstrAfter(MBBI);
 211     }
 212     visitMachineBasicBlockAfter(MFI);
 213   }
 214   visitMachineFunctionAfter();
 215
 216   if (OutFile)
 217     delete OutFile;
 218   else if (foundErrors)
 219     llvm_report_error("Found "+Twine(foundErrors)+" machine code errors.");
 220
 221   // Clean up.
 222   regsLive.clear();
 223   regsDefined.clear();
 224   regsDead.clear();
 225   regsKilled.clear();
 226   regsLiveInButUnused.clear();
 227   MBBInfoMap.clear();
 228
 229   return false;                 // no changes
 230 }
 231
 232 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
 233   assert(MF);
 234   *OS << '\n';
 235   if (!foundErrors++)
 236     MF->print(*OS);
 237   *OS << "*** Bad machine code: " << msg << " ***\n"
 238       << "- function:    " << MF->getFunction()->getNameStr() << "\n";
 239 }
 240
 241 void
 242 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
 243 {
 244   assert(MBB);
 245   report(msg, MBB->getParent());
 246   *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
 247       << " " << (void*)MBB
 248       << " (#" << MBB->getNumber() << ")\n";
 249 }
 250
 251 void
 252 MachineVerifier::report(const char *msg, const MachineInstr *MI)
 253 {
 254   assert(MI);
 255   report(msg, MI->getParent());
 256   *OS << "- instruction: ";
 257   MI->print(*OS, TM);
 258 }
 259
 260 void
 261 MachineVerifier::report(const char *msg,
 262                         const MachineOperand *MO, unsigned MONum)
 263 {
 264   assert(MO);
 265   report(msg, MO->getParent());
 266   *OS << "- operand " << MONum << ":   ";
 267   MO->print(*OS, TM);
 268   *OS << "\n";
 269 }
 270
 271 void
 272 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
 273 {
 274   BBInfo &MInfo = MBBInfoMap[MBB];
 275   if (!MInfo.reachable) {
 276     MInfo.reachable = true;
 277     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
 278            SuE = MBB->succ_end(); SuI != SuE; ++SuI)
 279       markReachable(*SuI);
 280   }
 281 }
 282
 283 void
 284 MachineVerifier::visitMachineFunctionBefore()
 285 {
 286   regsReserved = TRI->getReservedRegs(*MF);
 287
 288   // A sub-register of a reserved register is also reserved
 289   for (int Reg = regsReserved.find_first(); Reg>=0;
 290        Reg = regsReserved.find_next(Reg)) {
 291     for (const unsigned *Sub = TRI->getSubRegisters(Reg); *Sub; ++Sub) {
 292       // FIXME: This should probably be:
 293       // assert(regsReserved.test(*Sub) && "Non-reserved sub-register");
 294       regsReserved.set(*Sub);
 295     }
 296   }
 297   markReachable(&MF->front());
 298 }
 299
 300 void
 301 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
 302 {
 303   const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
 304
 305   // Start with minimal CFG sanity checks.
 306   MachineFunction::const_iterator MBBI = MBB;
 307   ++MBBI;
 308   if (MBBI != MF->end()) {
 309     // Block is not last in function.
 310     if (!MBB->isSuccessor(MBBI)) {
 311       // Block does not fall through.
 312       if (MBB->empty()) {
 313         report("MBB doesn't fall through but is empty!", MBB);
 314       }
 315     }
 316     if (TII->BlockHasNoFallThrough(*MBB)) {
 317       if (MBB->empty()) {
 318         report("TargetInstrInfo says the block has no fall through, but the "
 319                "block is empty!", MBB);
 320       } else if (!MBB->back().getDesc().isBarrier()) {
 321         report("TargetInstrInfo says the block has no fall through, but the "
 322                "block does not end in a barrier!", MBB);
 323       }
 324     }
 325   } else {
 326     // Block is last in function.
 327     if (MBB->empty()) {
 328       report("MBB is last in function but is empty!", MBB);
 329     }
 330   }
 331
 332   // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
 333   MachineBasicBlock *TBB = 0, *FBB = 0;
 334   SmallVector<MachineOperand, 4> Cond;
 335   if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
 336                           TBB, FBB, Cond)) {
 337     // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
 338     // check whether its answers match up with reality.
 339     if (!TBB && !FBB) {
 340       // Block falls through to its successor.
 341       MachineFunction::const_iterator MBBI = MBB;
 342       ++MBBI;
 343       if (MBBI == MF->end()) {
 344         // It's possible that the block legitimately ends with a noreturn
 345         // call or an unreachable, in which case it won't actually fall
 346         // out the bottom of the function.
 347       } else if (MBB->succ_empty()) {
 348         // It's possible that the block legitimately ends with a noreturn
 349         // call or an unreachable, in which case it won't actuall fall
 350         // out of the block.
 351       } else if (MBB->succ_size() != 1) {
 352         report("MBB exits via unconditional fall-through but doesn't have "
 353                "exactly one CFG successor!", MBB);
 354       } else if (MBB->succ_begin()[0] != MBBI) {
 355         report("MBB exits via unconditional fall-through but its successor "
 356                "differs from its CFG successor!", MBB);
 357       }
 358       if (!MBB->empty() && MBB->back().getDesc().isBarrier()) {
 359         report("MBB exits via unconditional fall-through but ends with a "
 360                "barrier instruction!", MBB);
 361       }
 362       if (!Cond.empty()) {
 363         report("MBB exits via unconditional fall-through but has a condition!",
 364                MBB);
 365       }
 366     } else if (TBB && !FBB && Cond.empty()) {
 367       // Block unconditionally branches somewhere.
 368       if (MBB->succ_size() != 1) {
 369         report("MBB exits via unconditional branch but doesn't have "
 370                "exactly one CFG successor!", MBB);
 371       } else if (MBB->succ_begin()[0] != TBB) {
 372         report("MBB exits via unconditional branch but the CFG "
 373                "successor doesn't match the actual successor!", MBB);
 374       }
 375       if (MBB->empty()) {
 376         report("MBB exits via unconditional branch but doesn't contain "
 377                "any instructions!", MBB);
 378       } else if (!MBB->back().getDesc().isBarrier()) {
 379         report("MBB exits via unconditional branch but doesn't end with a "
 380                "barrier instruction!", MBB);
 381       } else if (!MBB->back().getDesc().isTerminator()) {
 382         report("MBB exits via unconditional branch but the branch isn't a "
 383                "terminator instruction!", MBB);
 384       }
 385     } else if (TBB && !FBB && !Cond.empty()) {
 386       // Block conditionally branches somewhere, otherwise falls through.
 387       MachineFunction::const_iterator MBBI = MBB;
 388       ++MBBI;
 389       if (MBBI == MF->end()) {
 390         report("MBB conditionally falls through out of function!", MBB);
 391       } if (MBB->succ_size() != 2) {
 392         report("MBB exits via conditional branch/fall-through but doesn't have "
 393                "exactly two CFG successors!", MBB);
 394       } else if ((MBB->succ_begin()[0] == TBB && MBB->succ_end()[1] == MBBI) ||
 395                  (MBB->succ_begin()[1] == TBB && MBB->succ_end()[0] == MBBI)) {
 396         report("MBB exits via conditional branch/fall-through but the CFG "
 397                "successors don't match the actual successors!", MBB);
 398       }
 399       if (MBB->empty()) {
 400         report("MBB exits via conditional branch/fall-through but doesn't "
 401                "contain any instructions!", MBB);
 402       } else if (MBB->back().getDesc().isBarrier()) {
 403         report("MBB exits via conditional branch/fall-through but ends with a "
 404                "barrier instruction!", MBB);
 405       } else if (!MBB->back().getDesc().isTerminator()) {
 406         report("MBB exits via conditional branch/fall-through but the branch "
 407                "isn't a terminator instruction!", MBB);
 408       }
 409     } else if (TBB && FBB) {
 410       // Block conditionally branches somewhere, otherwise branches
 411       // somewhere else.
 412       if (MBB->succ_size() != 2) {
 413         report("MBB exits via conditional branch/branch but doesn't have "
 414                "exactly two CFG successors!", MBB);
 415       } else if ((MBB->succ_begin()[0] == TBB && MBB->succ_end()[1] == FBB) ||
 416                  (MBB->succ_begin()[1] == TBB && MBB->succ_end()[0] == FBB)) {
 417         report("MBB exits via conditional branch/branch but the CFG "
 418                "successors don't match the actual successors!", MBB);
 419       }
 420       if (MBB->empty()) {
 421         report("MBB exits via conditional branch/branch but doesn't "
 422                "contain any instructions!", MBB);
 423       } else if (!MBB->back().getDesc().isBarrier()) {
 424         report("MBB exits via conditional branch/branch but doesn't end with a "
 425                "barrier instruction!", MBB);
 426       } else if (!MBB->back().getDesc().isTerminator()) {
 427         report("MBB exits via conditional branch/branch but the branch "
 428                "isn't a terminator instruction!", MBB);
 429       }
 430       if (Cond.empty()) {
 431         report("MBB exits via conditinal branch/branch but there's no "
 432                "condition!", MBB);
 433       }
 434     } else {
 435       report("AnalyzeBranch returned invalid data!", MBB);
 436     }
 437   }
 438
 439   regsLive.clear();
 440   for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
 441          E = MBB->livein_end(); I != E; ++I) {
 442     if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
 443       report("MBB live-in list contains non-physical register", MBB);
 444       continue;
 445     }
 446     regsLive.insert(*I);
 447     for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
 448       regsLive.insert(*R);
 449   }
 450   regsLiveInButUnused = regsLive;
 451
 452   const MachineFrameInfo *MFI = MF->getFrameInfo();
 453   assert(MFI && "Function has no frame info");
 454   BitVector PR = MFI->getPristineRegs(MBB);
 455   for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
 456     regsLive.insert(I);
 457     for (const unsigned *R = TRI->getSubRegisters(I); *R; R++)
 458       regsLive.insert(*R);
 459   }
 460
 461   regsKilled.clear();
 462   regsDefined.clear();
 463 }
 464
 465 void
 466 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
 467 {
 468   const TargetInstrDesc &TI = MI->getDesc();
 469   if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
 470     report("Too few operands", MI);
 471     *OS << TI.getNumOperands() << " operands expected, but "
 472         << MI->getNumExplicitOperands() << " given.\n";
 473   }
 474   if (!TI.isVariadic()) {
 475     if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
 476       report("Too many operands", MI);
 477       *OS << TI.getNumOperands() << " operands expected, but "
 478           << MI->getNumExplicitOperands() << " given.\n";
 479     }
 480   }
 481 }
 482
 483 void
 484 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
 485 {
 486   const MachineInstr *MI = MO->getParent();
 487   const TargetInstrDesc &TI = MI->getDesc();
 488
 489   // The first TI.NumDefs operands must be explicit register defines
 490   if (MONum < TI.getNumDefs()) {
 491     if (!MO->isReg())
 492       report("Explicit definition must be a register", MO, MONum);
 493     else if (!MO->isDef())
 494       report("Explicit definition marked as use", MO, MONum);
 495     else if (MO->isImplicit())
 496       report("Explicit definition marked as implicit", MO, MONum);
 497   }
 498
 499   switch (MO->getType()) {
 500   case MachineOperand::MO_Register: {
 501     const unsigned Reg = MO->getReg();
 502     if (!Reg)
 503       return;
 504
 505     // Check Live Variables.
 506     if (MO->isUndef()) {
 507       // An <undef> doesn't refer to any register, so just skip it.
 508     } else if (MO->isUse()) {
 509       regsLiveInButUnused.erase(Reg);
 510
 511       if (MO->isKill()) {
 512         addRegWithSubRegs(regsKilled, Reg);
 513         // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
 514         if (MI->isRegTiedToDefOperand(MONum))
 515             report("Illegal kill flag on two-address instruction operand",
 516                    MO, MONum);
 517       } else {
 518         // TwoAddress instr modifying a reg is treated as kill+def.
 519         unsigned defIdx;
 520         if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
 521             MI->getOperand(defIdx).getReg() == Reg)
 522           addRegWithSubRegs(regsKilled, Reg);
 523       }
 524       // Use of a dead register.
 525       if (!regsLive.count(Reg)) {
 526         if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 527           // Reserved registers may be used even when 'dead'.
 528           if (!isReserved(Reg))
 529             report("Using an undefined physical register", MO, MONum);
 530         } else {
 531           BBInfo &MInfo = MBBInfoMap[MI->getParent()];
 532           // We don't know which virtual registers are live in, so only complain
 533           // if vreg was killed in this MBB. Otherwise keep track of vregs that
 534           // must be live in. PHI instructions are handled separately.
 535           if (MInfo.regsKilled.count(Reg))
 536             report("Using a killed virtual register", MO, MONum);
 537           else if (MI->getOpcode() != TargetInstrInfo::PHI)
 538             MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
 539         }
 540       }
 541     } else {
 542       assert(MO->isDef());
 543       // Register defined.
 544       // TODO: verify that earlyclobber ops are not used.
 545       if (MO->isDead())
 546         addRegWithSubRegs(regsDead, Reg);
 547       else
 548         addRegWithSubRegs(regsDefined, Reg);
 549     }
 550
 551     // Check register classes.
 552     if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
 553       const TargetOperandInfo &TOI = TI.OpInfo[MONum];
 554       unsigned SubIdx = MO->getSubReg();
 555
 556       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 557         unsigned sr = Reg;
 558         if (SubIdx) {
 559           unsigned s = TRI->getSubReg(Reg, SubIdx);
 560           if (!s) {
 561             report("Invalid subregister index for physical register",
 562                    MO, MONum);
 563             return;
 564           }
 565           sr = s;
 566         }
 567         if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
 568           if (!DRC->contains(sr)) {
 569             report("Illegal physical register for instruction", MO, MONum);
 570             *OS << TRI->getName(sr) << " is not a "
 571                 << DRC->getName() << " register.\n";
 572           }
 573         }
 574       } else {
 575         // Virtual register.
 576         const TargetRegisterClass *RC = MRI->getRegClass(Reg);
 577         if (SubIdx) {
 578           if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
 579             report("Invalid subregister index for virtual register", MO, MONum);
 580             return;
 581           }
 582           RC = *(RC->subregclasses_begin()+SubIdx);
 583         }
 584         if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
 585           if (RC != DRC && !RC->hasSuperClass(DRC)) {
 586             report("Illegal virtual register for instruction", MO, MONum);
 587             *OS << "Expected a " << DRC->getName() << " register, but got a "
 588                 << RC->getName() << " register\n";
 589           }
 590         }
 591       }
 592     }
 593     break;
 594   }
 595     // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
 596     // case MachineOperand::MO_MachineBasicBlock:
 597     //   if (MI->getOpcode() == TargetInstrInfo::PHI) {
 598     //     if (!MO->getMBB()->isSuccessor(MI->getParent()))
 599     //       report("PHI operand is not in the CFG", MO, MONum);
 600     //   }
 601     //   break;
 602   default:
 603     break;
 604   }
 605 }
 606
 607 void
 608 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
 609 {
 610   BBInfo &MInfo = MBBInfoMap[MI->getParent()];
 611   set_union(MInfo.regsKilled, regsKilled);
 612   set_subtract(regsLive, regsKilled);
 613   regsKilled.clear();
 614
 615   // Verify that both <def> and <def,dead> operands refer to dead registers.
 616   RegVector defs(regsDefined);
 617   defs.append(regsDead.begin(), regsDead.end());
 618
 619   for (RegVector::const_iterator I = defs.begin(), E = defs.end();
 620        I != E; ++I) {
 621     if (regsLive.count(*I)) {
 622       if (TargetRegisterInfo::isPhysicalRegister(*I)) {
 623         if (!allowPhysDoubleDefs && !isReserved(*I) &&
 624             !regsLiveInButUnused.count(*I)) {
 625           report("Redefining a live physical register", MI);
 626           *OS << "Register " << TRI->getName(*I)
 627               << " was defined but already live.\n";
 628         }
 629       } else {
 630         if (!allowVirtDoubleDefs) {
 631           report("Redefining a live virtual register", MI);
 632           *OS << "Virtual register %reg" << *I
 633               << " was defined but already live.\n";
 634         }
 635       }
 636     } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
 637                !MInfo.regsKilled.count(*I)) {
 638       // Virtual register defined without being killed first must be dead on
 639       // entry.
 640       MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
 641     }
 642   }
 643
 644   set_subtract(regsLive, regsDead); regsDead.clear();
 645   set_union(regsLive, regsDefined); regsDefined.clear();
 646 }
 647
 648 void
 649 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
 650 {
 651   MBBInfoMap[MBB].regsLiveOut = regsLive;
 652   regsLive.clear();
 653 }
 654
 655 // Calculate the largest possible vregsPassed sets. These are the registers that
 656 // can pass through an MBB live, but may not be live every time. It is assumed
 657 // that all vregsPassed sets are empty before the call.
 658 void
 659 MachineVerifier::calcMaxRegsPassed()
 660 {
 661   // First push live-out regs to successors' vregsPassed. Remember the MBBs that
 662   // have any vregsPassed.
 663   DenseSet<const MachineBasicBlock*> todo;
 664   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 665        MFI != MFE; ++MFI) {
 666     const MachineBasicBlock &MBB(*MFI);
 667     BBInfo &MInfo = MBBInfoMap[&MBB];
 668     if (!MInfo.reachable)
 669       continue;
 670     for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
 671            SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
 672       BBInfo &SInfo = MBBInfoMap[*SuI];
 673       if (SInfo.addPassed(MInfo.regsLiveOut))
 674         todo.insert(*SuI);
 675     }
 676   }
 677
 678   // Iteratively push vregsPassed to successors. This will converge to the same
 679   // final state regardless of DenseSet iteration order.
 680   while (!todo.empty()) {
 681     const MachineBasicBlock *MBB = *todo.begin();
 682     todo.erase(MBB);
 683     BBInfo &MInfo = MBBInfoMap[MBB];
 684     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
 685            SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
 686       if (*SuI == MBB)
 687         continue;
 688       BBInfo &SInfo = MBBInfoMap[*SuI];
 689       if (SInfo.addPassed(MInfo.vregsPassed))
 690         todo.insert(*SuI);
 691     }
 692   }
 693 }
 694
 695 // Calculate the minimum vregsPassed set. These are the registers that always
 696 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
 697 // been called earlier.
 698 void
 699 MachineVerifier::calcMinRegsPassed()
 700 {
 701   DenseSet<const MachineBasicBlock*> todo;
 702   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 703        MFI != MFE; ++MFI)
 704     todo.insert(MFI);
 705
 706   while (!todo.empty()) {
 707     const MachineBasicBlock *MBB = *todo.begin();
 708     todo.erase(MBB);
 709     BBInfo &MInfo = MBBInfoMap[MBB];
 710
 711     // Remove entries from vRegsPassed that are not live out from all
 712     // reachable predecessors.
 713     RegSet dead;
 714     for (RegSet::iterator I = MInfo.vregsPassed.begin(),
 715            E = MInfo.vregsPassed.end(); I != E; ++I) {
 716       for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
 717              PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
 718         BBInfo &PrInfo = MBBInfoMap[*PrI];
 719         if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
 720           dead.insert(*I);
 721           break;
 722         }
 723       }
 724     }
 725     // If any regs removed, we need to recheck successors.
 726     if (!dead.empty()) {
 727       set_subtract(MInfo.vregsPassed, dead);
 728       todo.insert(MBB->succ_begin(), MBB->succ_end());
 729     }
 730   }
 731 }
 732
 733 // Check PHI instructions at the beginning of MBB. It is assumed that
 734 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
 735 void
 736 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
 737 {
 738   for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
 739        BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
 740     DenseSet<const MachineBasicBlock*> seen;
 741
 742     for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
 743       unsigned Reg = BBI->getOperand(i).getReg();
 744       const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
 745       if (!Pre->isSuccessor(MBB))
 746         continue;
 747       seen.insert(Pre);
 748       BBInfo &PrInfo = MBBInfoMap[Pre];
 749       if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
 750         report("PHI operand is not live-out from predecessor",
 751                &BBI->getOperand(i), i);
 752     }
 753
 754     // Did we see all predecessors?
 755     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
 756            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
 757       if (!seen.count(*PrI)) {
 758         report("Missing PHI operand", BBI);
 759         *OS << "MBB #" << (*PrI)->getNumber()
 760             << " is a predecessor according to the CFG.\n";
 761       }
 762     }
 763   }
 764 }
 765
 766 void
 767 MachineVerifier::visitMachineFunctionAfter()
 768 {
 769   calcMaxRegsPassed();
 770
 771   // With the maximal set of vregsPassed we can verify dead-in registers.
 772   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 773        MFI != MFE; ++MFI) {
 774     BBInfo &MInfo = MBBInfoMap[MFI];
 775
 776     // Skip unreachable MBBs.
 777     if (!MInfo.reachable)
 778       continue;
 779
 780     for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
 781            PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
 782       BBInfo &PrInfo = MBBInfoMap[*PrI];
 783       if (!PrInfo.reachable)
 784         continue;
 785
 786       // Verify physical live-ins. EH landing pads have magic live-ins so we
 787       // ignore them.
 788       if (!MFI->isLandingPad()) {
 789         for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
 790                E = MFI->livein_end(); I != E; ++I) {
 791           if (TargetRegisterInfo::isPhysicalRegister(*I) &&
 792               !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
 793             report("Live-in physical register is not live-out from predecessor",
 794                    MFI);
 795             *OS << "Register " << TRI->getName(*I)
 796                 << " is not live-out from MBB #" << (*PrI)->getNumber()
 797                 << ".\n";
 798           }
 799         }
 800       }
 801
 802
 803       // Verify dead-in virtual registers.
 804       if (!allowVirtDoubleDefs) {
 805         for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
 806                E = MInfo.vregsDeadIn.end(); I != E; ++I) {
 807           // DeadIn register must be in neither regsLiveOut or vregsPassed of
 808           // any predecessor.
 809           if (PrInfo.isLiveOut(I->first)) {
 810             report("Live-in virtual register redefined", I->second);
 811             *OS << "Register %reg" << I->first
 812                 << " was live-out from predecessor MBB #"
 813                 << (*PrI)->getNumber() << ".\n";
 814           }
 815         }
 816       }
 817     }
 818   }
 819
 820   calcMinRegsPassed();
 821
 822   // With the minimal set of vregsPassed we can verify live-in virtual
 823   // registers, including PHI instructions.
 824   for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
 825        MFI != MFE; ++MFI) {
 826     BBInfo &MInfo = MBBInfoMap[MFI];
 827
 828     // Skip unreachable MBBs.
 829     if (!MInfo.reachable)
 830       continue;
 831
 832     checkPHIOps(MFI);
 833
 834     for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
 835            PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
 836       BBInfo &PrInfo = MBBInfoMap[*PrI];
 837       if (!PrInfo.reachable)
 838         continue;
 839
 840       for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
 841              E = MInfo.vregsLiveIn.end(); I != E; ++I) {
 842         if (!PrInfo.isLiveOut(I->first)) {
 843           report("Used virtual register is not live-in", I->second);
 844           *OS << "Register %reg" << I->first
 845               << " is not live-out from predecessor MBB #"
 846               << (*PrI)->getNumber()
 847               << ".\n";
 848         }
 849       }
 850     }
 851   }
 852 }