1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
32 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
33 /// implicit physical register output.
34 void ScheduleDAGSDNodes::
35 EmitCopyFromReg(SDNode
*Node
, unsigned ResNo
, bool IsClone
, bool IsCloned
,
36 unsigned SrcReg
, DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
38 if (TargetRegisterInfo::isVirtualRegister(SrcReg
)) {
39 // Just use the input register directly!
40 SDValue
Op(Node
, ResNo
);
43 bool isNew
= VRBaseMap
.insert(std::make_pair(Op
, SrcReg
)).second
;
44 isNew
= isNew
; // Silence compiler warning.
45 assert(isNew
&& "Node emitted out of order - early");
49 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
50 // the CopyToReg'd destination register instead of creating a new vreg.
52 const TargetRegisterClass
*UseRC
= NULL
;
53 if (!IsClone
&& !IsCloned
)
54 for (SDNode::use_iterator UI
= Node
->use_begin(), E
= Node
->use_end();
58 if (User
->getOpcode() == ISD::CopyToReg
&&
59 User
->getOperand(2).getNode() == Node
&&
60 User
->getOperand(2).getResNo() == ResNo
) {
61 unsigned DestReg
= cast
<RegisterSDNode
>(User
->getOperand(1))->getReg();
62 if (TargetRegisterInfo::isVirtualRegister(DestReg
)) {
65 } else if (DestReg
!= SrcReg
)
68 for (unsigned i
= 0, e
= User
->getNumOperands(); i
!= e
; ++i
) {
69 SDValue Op
= User
->getOperand(i
);
70 if (Op
.getNode() != Node
|| Op
.getResNo() != ResNo
)
72 EVT VT
= Node
->getValueType(Op
.getResNo());
73 if (VT
== MVT::Other
|| VT
== MVT::Flag
)
76 if (User
->isMachineOpcode()) {
77 const TargetInstrDesc
&II
= TII
->get(User
->getMachineOpcode());
78 const TargetRegisterClass
*RC
= 0;
79 if (i
+II
.getNumDefs() < II
.getNumOperands())
80 RC
= II
.OpInfo
[i
+II
.getNumDefs()].getRegClass(TRI
);
84 const TargetRegisterClass
*ComRC
= getCommonSubClass(UseRC
, RC
);
85 // If multiple uses expect disjoint register classes, we emit
86 // copies in AddRegisterOperand.
98 EVT VT
= Node
->getValueType(ResNo
);
99 const TargetRegisterClass
*SrcRC
= 0, *DstRC
= 0;
100 SrcRC
= TRI
->getPhysicalRegisterRegClass(SrcReg
, VT
);
102 // Figure out the register class to create for the destreg.
104 DstRC
= MRI
.getRegClass(VRBase
);
106 assert(UseRC
->hasType(VT
) && "Incompatible phys register def and uses!");
109 DstRC
= TLI
->getRegClassFor(VT
);
112 // If all uses are reading from the src physical register and copying the
113 // register is either impossible or very expensive, then don't create a copy.
114 if (MatchReg
&& SrcRC
->getCopyCost() < 0) {
117 // Create the reg, emit the copy.
118 VRBase
= MRI
.createVirtualRegister(DstRC
);
119 bool Emitted
= TII
->copyRegToReg(*BB
, InsertPos
, VRBase
, SrcReg
,
122 assert(Emitted
&& "Unable to issue a copy instruction!\n");
126 SDValue
Op(Node
, ResNo
);
129 bool isNew
= VRBaseMap
.insert(std::make_pair(Op
, VRBase
)).second
;
130 isNew
= isNew
; // Silence compiler warning.
131 assert(isNew
&& "Node emitted out of order - early");
134 /// getDstOfCopyToRegUse - If the only use of the specified result number of
135 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
136 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode
*Node
,
137 unsigned ResNo
) const {
138 if (!Node
->hasOneUse())
141 SDNode
*User
= *Node
->use_begin();
142 if (User
->getOpcode() == ISD::CopyToReg
&&
143 User
->getOperand(2).getNode() == Node
&&
144 User
->getOperand(2).getResNo() == ResNo
) {
145 unsigned Reg
= cast
<RegisterSDNode
>(User
->getOperand(1))->getReg();
146 if (TargetRegisterInfo::isVirtualRegister(Reg
))
152 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode
*Node
, MachineInstr
*MI
,
153 const TargetInstrDesc
&II
,
154 bool IsClone
, bool IsCloned
,
155 DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
156 assert(Node
->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF
&&
157 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
159 for (unsigned i
= 0; i
< II
.getNumDefs(); ++i
) {
160 // If the specific node value is only used by a CopyToReg and the dest reg
161 // is a vreg in the same register class, use the CopyToReg'd destination
162 // register instead of creating a new vreg.
164 const TargetRegisterClass
*RC
= II
.OpInfo
[i
].getRegClass(TRI
);
165 if (II
.OpInfo
[i
].isOptionalDef()) {
166 // Optional def must be a physical register.
167 unsigned NumResults
= CountResults(Node
);
168 VRBase
= cast
<RegisterSDNode
>(Node
->getOperand(i
-NumResults
))->getReg();
169 assert(TargetRegisterInfo::isPhysicalRegister(VRBase
));
170 MI
->addOperand(MachineOperand::CreateReg(VRBase
, true));
173 if (!VRBase
&& !IsClone
&& !IsCloned
)
174 for (SDNode::use_iterator UI
= Node
->use_begin(), E
= Node
->use_end();
177 if (User
->getOpcode() == ISD::CopyToReg
&&
178 User
->getOperand(2).getNode() == Node
&&
179 User
->getOperand(2).getResNo() == i
) {
180 unsigned Reg
= cast
<RegisterSDNode
>(User
->getOperand(1))->getReg();
181 if (TargetRegisterInfo::isVirtualRegister(Reg
)) {
182 const TargetRegisterClass
*RegRC
= MRI
.getRegClass(Reg
);
185 MI
->addOperand(MachineOperand::CreateReg(Reg
, true));
192 // Create the result registers for this node and add the result regs to
193 // the machine instruction.
195 assert(RC
&& "Isn't a register operand!");
196 VRBase
= MRI
.createVirtualRegister(RC
);
197 MI
->addOperand(MachineOperand::CreateReg(VRBase
, true));
203 bool isNew
= VRBaseMap
.insert(std::make_pair(Op
, VRBase
)).second
;
204 isNew
= isNew
; // Silence compiler warning.
205 assert(isNew
&& "Node emitted out of order - early");
209 /// getVR - Return the virtual register corresponding to the specified result
210 /// of the specified node.
211 unsigned ScheduleDAGSDNodes::getVR(SDValue Op
,
212 DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
213 if (Op
.isMachineOpcode() &&
214 Op
.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF
) {
215 // Add an IMPLICIT_DEF instruction before every use.
216 unsigned VReg
= getDstOfOnlyCopyToRegUse(Op
.getNode(), Op
.getResNo());
217 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
218 // does not include operand register class info.
220 const TargetRegisterClass
*RC
= TLI
->getRegClassFor(Op
.getValueType());
221 VReg
= MRI
.createVirtualRegister(RC
);
223 BuildMI(BB
, Op
.getDebugLoc(), TII
->get(TargetInstrInfo::IMPLICIT_DEF
),VReg
);
227 DenseMap
<SDValue
, unsigned>::iterator I
= VRBaseMap
.find(Op
);
228 assert(I
!= VRBaseMap
.end() && "Node emitted out of order - late");
233 /// AddRegisterOperand - Add the specified register as an operand to the
234 /// specified machine instr. Insert register copies if the register is
235 /// not in the required register class.
237 ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr
*MI
, SDValue Op
,
239 const TargetInstrDesc
*II
,
240 DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
241 assert(Op
.getValueType() != MVT::Other
&&
242 Op
.getValueType() != MVT::Flag
&&
243 "Chain and flag operands should occur at end of operand list!");
244 // Get/emit the operand.
245 unsigned VReg
= getVR(Op
, VRBaseMap
);
246 assert(TargetRegisterInfo::isVirtualRegister(VReg
) && "Not a vreg?");
248 const TargetInstrDesc
&TID
= MI
->getDesc();
249 bool isOptDef
= IIOpNum
< TID
.getNumOperands() &&
250 TID
.OpInfo
[IIOpNum
].isOptionalDef();
252 // If the instruction requires a register in a different class, create
253 // a new virtual register and copy the value into it.
255 const TargetRegisterClass
*SrcRC
= MRI
.getRegClass(VReg
);
256 const TargetRegisterClass
*DstRC
= 0;
257 if (IIOpNum
< II
->getNumOperands())
258 DstRC
= II
->OpInfo
[IIOpNum
].getRegClass(TRI
);
259 assert((DstRC
|| (TID
.isVariadic() && IIOpNum
>= TID
.getNumOperands())) &&
260 "Don't have operand info for this instruction!");
261 if (DstRC
&& SrcRC
!= DstRC
&& !SrcRC
->hasSuperClass(DstRC
)) {
262 unsigned NewVReg
= MRI
.createVirtualRegister(DstRC
);
263 bool Emitted
= TII
->copyRegToReg(*BB
, InsertPos
, NewVReg
, VReg
,
265 assert(Emitted
&& "Unable to issue a copy instruction!\n");
271 MI
->addOperand(MachineOperand::CreateReg(VReg
, isOptDef
));
274 /// AddOperand - Add the specified operand to the specified machine instr. II
275 /// specifies the instruction information for the node, and IIOpNum is the
276 /// operand number (in the II) that we are adding. IIOpNum and II are used for
278 void ScheduleDAGSDNodes::AddOperand(MachineInstr
*MI
, SDValue Op
,
280 const TargetInstrDesc
*II
,
281 DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
282 if (Op
.isMachineOpcode()) {
283 AddRegisterOperand(MI
, Op
, IIOpNum
, II
, VRBaseMap
);
284 } else if (ConstantSDNode
*C
= dyn_cast
<ConstantSDNode
>(Op
)) {
285 MI
->addOperand(MachineOperand::CreateImm(C
->getZExtValue()));
286 } else if (ConstantFPSDNode
*F
= dyn_cast
<ConstantFPSDNode
>(Op
)) {
287 const ConstantFP
*CFP
= F
->getConstantFPValue();
288 MI
->addOperand(MachineOperand::CreateFPImm(CFP
));
289 } else if (RegisterSDNode
*R
= dyn_cast
<RegisterSDNode
>(Op
)) {
290 MI
->addOperand(MachineOperand::CreateReg(R
->getReg(), false));
291 } else if (GlobalAddressSDNode
*TGA
= dyn_cast
<GlobalAddressSDNode
>(Op
)) {
292 MI
->addOperand(MachineOperand::CreateGA(TGA
->getGlobal(), TGA
->getOffset(),
293 TGA
->getTargetFlags()));
294 } else if (BasicBlockSDNode
*BBNode
= dyn_cast
<BasicBlockSDNode
>(Op
)) {
295 MI
->addOperand(MachineOperand::CreateMBB(BBNode
->getBasicBlock()));
296 } else if (FrameIndexSDNode
*FI
= dyn_cast
<FrameIndexSDNode
>(Op
)) {
297 MI
->addOperand(MachineOperand::CreateFI(FI
->getIndex()));
298 } else if (JumpTableSDNode
*JT
= dyn_cast
<JumpTableSDNode
>(Op
)) {
299 MI
->addOperand(MachineOperand::CreateJTI(JT
->getIndex(),
300 JT
->getTargetFlags()));
301 } else if (ConstantPoolSDNode
*CP
= dyn_cast
<ConstantPoolSDNode
>(Op
)) {
302 int Offset
= CP
->getOffset();
303 unsigned Align
= CP
->getAlignment();
304 const Type
*Type
= CP
->getType();
305 // MachineConstantPool wants an explicit alignment.
307 Align
= TM
.getTargetData()->getPrefTypeAlignment(Type
);
309 // Alignment of vector types. FIXME!
310 Align
= TM
.getTargetData()->getTypeAllocSize(Type
);
315 if (CP
->isMachineConstantPoolEntry())
316 Idx
= ConstPool
->getConstantPoolIndex(CP
->getMachineCPVal(), Align
);
318 Idx
= ConstPool
->getConstantPoolIndex(CP
->getConstVal(), Align
);
319 MI
->addOperand(MachineOperand::CreateCPI(Idx
, Offset
,
320 CP
->getTargetFlags()));
321 } else if (ExternalSymbolSDNode
*ES
= dyn_cast
<ExternalSymbolSDNode
>(Op
)) {
322 MI
->addOperand(MachineOperand::CreateES(ES
->getSymbol(),
323 ES
->getTargetFlags()));
325 assert(Op
.getValueType() != MVT::Other
&&
326 Op
.getValueType() != MVT::Flag
&&
327 "Chain and flag operands should occur at end of operand list!");
328 AddRegisterOperand(MI
, Op
, IIOpNum
, II
, VRBaseMap
);
332 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
333 /// "SubIdx"'th sub-register class is the specified register class and whose
334 /// type matches the specified type.
335 static const TargetRegisterClass
*
336 getSuperRegisterRegClass(const TargetRegisterClass
*TRC
,
337 unsigned SubIdx
, EVT VT
) {
338 // Pick the register class of the superegister for this type
339 for (TargetRegisterInfo::regclass_iterator I
= TRC
->superregclasses_begin(),
340 E
= TRC
->superregclasses_end(); I
!= E
; ++I
)
341 if ((*I
)->hasType(VT
) && (*I
)->getSubRegisterRegClass(SubIdx
) == TRC
)
343 assert(false && "Couldn't find the register class");
347 /// EmitSubregNode - Generate machine code for subreg nodes.
349 void ScheduleDAGSDNodes::EmitSubregNode(SDNode
*Node
,
350 DenseMap
<SDValue
, unsigned> &VRBaseMap
){
352 unsigned Opc
= Node
->getMachineOpcode();
354 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
355 // the CopyToReg'd destination register instead of creating a new vreg.
356 for (SDNode::use_iterator UI
= Node
->use_begin(), E
= Node
->use_end();
359 if (User
->getOpcode() == ISD::CopyToReg
&&
360 User
->getOperand(2).getNode() == Node
) {
361 unsigned DestReg
= cast
<RegisterSDNode
>(User
->getOperand(1))->getReg();
362 if (TargetRegisterInfo::isVirtualRegister(DestReg
)) {
369 if (Opc
== TargetInstrInfo::EXTRACT_SUBREG
) {
370 unsigned SubIdx
= cast
<ConstantSDNode
>(Node
->getOperand(1))->getZExtValue();
372 // Create the extract_subreg machine instruction.
373 MachineInstr
*MI
= BuildMI(MF
, Node
->getDebugLoc(),
374 TII
->get(TargetInstrInfo::EXTRACT_SUBREG
));
376 // Figure out the register class to create for the destreg.
377 unsigned VReg
= getVR(Node
->getOperand(0), VRBaseMap
);
378 const TargetRegisterClass
*TRC
= MRI
.getRegClass(VReg
);
379 const TargetRegisterClass
*SRC
= TRC
->getSubRegisterRegClass(SubIdx
);
380 assert(SRC
&& "Invalid subregister index in EXTRACT_SUBREG");
382 // Figure out the register class to create for the destreg.
383 // Note that if we're going to directly use an existing register,
384 // it must be precisely the required class, and not a subclass
386 if (VRBase
== 0 || SRC
!= MRI
.getRegClass(VRBase
)) {
388 assert(SRC
&& "Couldn't find source register class");
389 VRBase
= MRI
.createVirtualRegister(SRC
);
392 // Add def, source, and subreg index
393 MI
->addOperand(MachineOperand::CreateReg(VRBase
, true));
394 AddOperand(MI
, Node
->getOperand(0), 0, 0, VRBaseMap
);
395 MI
->addOperand(MachineOperand::CreateImm(SubIdx
));
396 BB
->insert(InsertPos
, MI
);
397 } else if (Opc
== TargetInstrInfo::INSERT_SUBREG
||
398 Opc
== TargetInstrInfo::SUBREG_TO_REG
) {
399 SDValue N0
= Node
->getOperand(0);
400 SDValue N1
= Node
->getOperand(1);
401 SDValue N2
= Node
->getOperand(2);
402 unsigned SubReg
= getVR(N1
, VRBaseMap
);
403 unsigned SubIdx
= cast
<ConstantSDNode
>(N2
)->getZExtValue();
404 const TargetRegisterClass
*TRC
= MRI
.getRegClass(SubReg
);
405 const TargetRegisterClass
*SRC
=
406 getSuperRegisterRegClass(TRC
, SubIdx
,
407 Node
->getValueType(0));
409 // Figure out the register class to create for the destreg.
410 // Note that if we're going to directly use an existing register,
411 // it must be precisely the required class, and not a subclass
413 if (VRBase
== 0 || SRC
!= MRI
.getRegClass(VRBase
)) {
415 assert(SRC
&& "Couldn't find source register class");
416 VRBase
= MRI
.createVirtualRegister(SRC
);
419 // Create the insert_subreg or subreg_to_reg machine instruction.
420 MachineInstr
*MI
= BuildMI(MF
, Node
->getDebugLoc(), TII
->get(Opc
));
421 MI
->addOperand(MachineOperand::CreateReg(VRBase
, true));
423 // If creating a subreg_to_reg, then the first input operand
424 // is an implicit value immediate, otherwise it's a register
425 if (Opc
== TargetInstrInfo::SUBREG_TO_REG
) {
426 const ConstantSDNode
*SD
= cast
<ConstantSDNode
>(N0
);
427 MI
->addOperand(MachineOperand::CreateImm(SD
->getZExtValue()));
429 AddOperand(MI
, N0
, 0, 0, VRBaseMap
);
430 // Add the subregster being inserted
431 AddOperand(MI
, N1
, 0, 0, VRBaseMap
);
432 MI
->addOperand(MachineOperand::CreateImm(SubIdx
));
433 BB
->insert(InsertPos
, MI
);
435 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
438 bool isNew
= VRBaseMap
.insert(std::make_pair(Op
, VRBase
)).second
;
439 isNew
= isNew
; // Silence compiler warning.
440 assert(isNew
&& "Node emitted out of order - early");
443 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
444 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
445 /// register is constrained to be in a particular register class.
448 ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode
*Node
,
449 DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
450 unsigned VReg
= getVR(Node
->getOperand(0), VRBaseMap
);
451 const TargetRegisterClass
*SrcRC
= MRI
.getRegClass(VReg
);
453 unsigned DstRCIdx
= cast
<ConstantSDNode
>(Node
->getOperand(1))->getZExtValue();
454 const TargetRegisterClass
*DstRC
= TRI
->getRegClass(DstRCIdx
);
456 // Create the new VReg in the destination class and emit a copy.
457 unsigned NewVReg
= MRI
.createVirtualRegister(DstRC
);
458 bool Emitted
= TII
->copyRegToReg(*BB
, InsertPos
, NewVReg
, VReg
,
461 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
465 bool isNew
= VRBaseMap
.insert(std::make_pair(Op
, NewVReg
)).second
;
466 isNew
= isNew
; // Silence compiler warning.
467 assert(isNew
&& "Node emitted out of order - early");
470 /// EmitNode - Generate machine code for an node and needed dependencies.
472 void ScheduleDAGSDNodes::EmitNode(SDNode
*Node
, bool IsClone
, bool IsCloned
,
473 DenseMap
<SDValue
, unsigned> &VRBaseMap
) {
474 // If machine instruction
475 if (Node
->isMachineOpcode()) {
476 unsigned Opc
= Node
->getMachineOpcode();
478 // Handle subreg insert/extract specially
479 if (Opc
== TargetInstrInfo::EXTRACT_SUBREG
||
480 Opc
== TargetInstrInfo::INSERT_SUBREG
||
481 Opc
== TargetInstrInfo::SUBREG_TO_REG
) {
482 EmitSubregNode(Node
, VRBaseMap
);
486 // Handle COPY_TO_REGCLASS specially.
487 if (Opc
== TargetInstrInfo::COPY_TO_REGCLASS
) {
488 EmitCopyToRegClassNode(Node
, VRBaseMap
);
492 if (Opc
== TargetInstrInfo::IMPLICIT_DEF
)
493 // We want a unique VR for each IMPLICIT_DEF use.
496 const TargetInstrDesc
&II
= TII
->get(Opc
);
497 unsigned NumResults
= CountResults(Node
);
498 unsigned NodeOperands
= CountOperands(Node
);
499 unsigned MemOperandsEnd
= ComputeMemOperandsEnd(Node
);
500 bool HasPhysRegOuts
= (NumResults
> II
.getNumDefs()) &&
501 II
.getImplicitDefs() != 0;
503 unsigned NumMIOperands
= NodeOperands
+ NumResults
;
504 assert((II
.getNumOperands() == NumMIOperands
||
505 HasPhysRegOuts
|| II
.isVariadic()) &&
506 "#operands for dag node doesn't match .td file!");
509 // Create the new machine instruction.
510 MachineInstr
*MI
= BuildMI(MF
, Node
->getDebugLoc(), II
);
512 // Add result register values for things that are defined by this
515 CreateVirtualRegisters(Node
, MI
, II
, IsClone
, IsCloned
, VRBaseMap
);
517 // Emit all of the actual operands of this instruction, adding them to the
518 // instruction as appropriate.
519 bool HasOptPRefs
= II
.getNumDefs() > NumResults
;
520 assert((!HasOptPRefs
|| !HasPhysRegOuts
) &&
521 "Unable to cope with optional defs and phys regs defs!");
522 unsigned NumSkip
= HasOptPRefs
? II
.getNumDefs() - NumResults
: 0;
523 for (unsigned i
= NumSkip
; i
!= NodeOperands
; ++i
)
524 AddOperand(MI
, Node
->getOperand(i
), i
-NumSkip
+II
.getNumDefs(), &II
,
527 // Emit all of the memory operands of this instruction
528 for (unsigned i
= NodeOperands
; i
!= MemOperandsEnd
; ++i
)
529 AddMemOperand(MI
,cast
<MemOperandSDNode
>(Node
->getOperand(i
+NumSkip
))->MO
);
531 if (II
.usesCustomDAGSchedInsertionHook()) {
532 // Insert this instruction into the basic block using a target
533 // specific inserter which may returns a new basic block.
534 BB
= TLI
->EmitInstrWithCustomInserter(MI
, BB
);
535 InsertPos
= BB
->end();
537 BB
->insert(InsertPos
, MI
);
540 // Additional results must be an physical register def.
541 if (HasPhysRegOuts
) {
542 for (unsigned i
= II
.getNumDefs(); i
< NumResults
; ++i
) {
543 unsigned Reg
= II
.getImplicitDefs()[i
- II
.getNumDefs()];
544 if (Node
->hasAnyUseOfValue(i
))
545 EmitCopyFromReg(Node
, i
, IsClone
, IsCloned
, Reg
, VRBaseMap
);
551 switch (Node
->getOpcode()) {
556 llvm_unreachable("This target-independent node should have been selected!");
558 case ISD::EntryToken
:
559 llvm_unreachable("EntryToken should have been excluded from the schedule!");
561 case ISD::MERGE_VALUES
:
562 case ISD::TokenFactor
: // fall thru
564 case ISD::CopyToReg
: {
566 SDValue SrcVal
= Node
->getOperand(2);
567 if (RegisterSDNode
*R
= dyn_cast
<RegisterSDNode
>(SrcVal
))
568 SrcReg
= R
->getReg();
570 SrcReg
= getVR(SrcVal
, VRBaseMap
);
572 unsigned DestReg
= cast
<RegisterSDNode
>(Node
->getOperand(1))->getReg();
573 if (SrcReg
== DestReg
) // Coalesced away the copy? Ignore.
576 const TargetRegisterClass
*SrcTRC
= 0, *DstTRC
= 0;
577 // Get the register classes of the src/dst.
578 if (TargetRegisterInfo::isVirtualRegister(SrcReg
))
579 SrcTRC
= MRI
.getRegClass(SrcReg
);
581 SrcTRC
= TRI
->getPhysicalRegisterRegClass(SrcReg
,SrcVal
.getValueType());
583 if (TargetRegisterInfo::isVirtualRegister(DestReg
))
584 DstTRC
= MRI
.getRegClass(DestReg
);
586 DstTRC
= TRI
->getPhysicalRegisterRegClass(DestReg
,
587 Node
->getOperand(1).getValueType());
589 bool Emitted
= TII
->copyRegToReg(*BB
, InsertPos
, DestReg
, SrcReg
,
591 assert(Emitted
&& "Unable to issue a copy instruction!\n");
595 case ISD::CopyFromReg
: {
596 unsigned SrcReg
= cast
<RegisterSDNode
>(Node
->getOperand(1))->getReg();
597 EmitCopyFromReg(Node
, 0, IsClone
, IsCloned
, SrcReg
, VRBaseMap
);
600 case ISD::INLINEASM
: {
601 unsigned NumOps
= Node
->getNumOperands();
602 if (Node
->getOperand(NumOps
-1).getValueType() == MVT::Flag
)
603 --NumOps
; // Ignore the flag operand.
605 // Create the inline asm machine instruction.
606 MachineInstr
*MI
= BuildMI(MF
, Node
->getDebugLoc(),
607 TII
->get(TargetInstrInfo::INLINEASM
));
609 // Add the asm string as an external symbol operand.
611 cast
<ExternalSymbolSDNode
>(Node
->getOperand(1))->getSymbol();
612 MI
->addOperand(MachineOperand::CreateES(AsmStr
));
614 // Add all of the operand registers to the instruction.
615 for (unsigned i
= 2; i
!= NumOps
;) {
617 cast
<ConstantSDNode
>(Node
->getOperand(i
))->getZExtValue();
618 unsigned NumVals
= InlineAsm::getNumOperandRegisters(Flags
);
620 MI
->addOperand(MachineOperand::CreateImm(Flags
));
621 ++i
; // Skip the ID value.
624 default: llvm_unreachable("Bad flags!");
625 case 2: // Def of register.
626 for (; NumVals
; --NumVals
, ++i
) {
627 unsigned Reg
= cast
<RegisterSDNode
>(Node
->getOperand(i
))->getReg();
628 MI
->addOperand(MachineOperand::CreateReg(Reg
, true));
631 case 6: // Def of earlyclobber register.
632 for (; NumVals
; --NumVals
, ++i
) {
633 unsigned Reg
= cast
<RegisterSDNode
>(Node
->getOperand(i
))->getReg();
634 MI
->addOperand(MachineOperand::CreateReg(Reg
, true, false, false,
635 false, false, true));
638 case 1: // Use of register.
639 case 3: // Immediate.
640 case 4: // Addressing mode.
641 // The addressing mode has been selected, just add all of the
642 // operands to the machine instruction.
643 for (; NumVals
; --NumVals
, ++i
)
644 AddOperand(MI
, Node
->getOperand(i
), 0, 0, VRBaseMap
);
648 BB
->insert(InsertPos
, MI
);
654 /// EmitSchedule - Emit the machine code in scheduled order.
655 MachineBasicBlock
*ScheduleDAGSDNodes::EmitSchedule() {
656 DenseMap
<SDValue
, unsigned> VRBaseMap
;
657 DenseMap
<SUnit
*, unsigned> CopyVRBaseMap
;
658 for (unsigned i
= 0, e
= Sequence
.size(); i
!= e
; i
++) {
659 SUnit
*SU
= Sequence
[i
];
661 // Null SUnit* is a noop.
666 // For pre-regalloc scheduling, create instructions corresponding to the
667 // SDNode and any flagged SDNodes and append them to the block.
668 if (!SU
->getNode()) {
670 EmitPhysRegCopy(SU
, CopyVRBaseMap
);
674 SmallVector
<SDNode
*, 4> FlaggedNodes
;
675 for (SDNode
*N
= SU
->getNode()->getFlaggedNode(); N
;
676 N
= N
->getFlaggedNode())
677 FlaggedNodes
.push_back(N
);
678 while (!FlaggedNodes
.empty()) {
679 EmitNode(FlaggedNodes
.back(), SU
->OrigNode
!= SU
, SU
->isCloned
,VRBaseMap
);
680 FlaggedNodes
.pop_back();
682 EmitNode(SU
->getNode(), SU
->OrigNode
!= SU
, SU
->isCloned
, VRBaseMap
);