Fix comment for consistency sake.
[llvm/avr.git] / lib / CodeGen / SelectionDAG / SelectionDAGBuild.cpp
blob555ef9e1b0a405b0665fa22d95643bfdc8abebd2
1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/InlineAsm.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "llvm/CodeGen/MachineModuleInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/CodeGen/DwarfWriter.h"
42 #include "llvm/Analysis/DebugInfo.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetFrameInfo.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetLowering.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include <algorithm>
57 using namespace llvm;
59 /// LimitFloatPrecision - Generate low-precision inline sequences for
60 /// some float libcalls (6, 8 or 12 bits).
61 static unsigned LimitFloatPrecision;
63 static cl::opt<unsigned, true>
64 LimitFPPrecision("limit-float-precision",
65 cl::desc("Generate low-precision inline sequences "
66 "for some float libcalls"),
67 cl::location(LimitFloatPrecision),
68 cl::init(0));
70 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
71 /// of insertvalue or extractvalue indices that identify a member, return
72 /// the linearized index of the start of the member.
73 ///
74 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
75 const unsigned *Indices,
76 const unsigned *IndicesEnd,
77 unsigned CurIndex = 0) {
78 // Base case: We're done.
79 if (Indices && Indices == IndicesEnd)
80 return CurIndex;
82 // Given a struct type, recursively traverse the elements.
83 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
84 for (StructType::element_iterator EB = STy->element_begin(),
85 EI = EB,
86 EE = STy->element_end();
87 EI != EE; ++EI) {
88 if (Indices && *Indices == unsigned(EI - EB))
89 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
90 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
92 return CurIndex;
94 // Given an array type, recursively traverse the elements.
95 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
96 const Type *EltTy = ATy->getElementType();
97 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
98 if (Indices && *Indices == i)
99 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
100 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
102 return CurIndex;
104 // We haven't found the type we're looking for, so keep searching.
105 return CurIndex + 1;
108 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
109 /// EVTs that represent all the individual underlying
110 /// non-aggregate types that comprise it.
112 /// If Offsets is non-null, it points to a vector to be filled in
113 /// with the in-memory offsets of each of the individual values.
115 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
116 SmallVectorImpl<EVT> &ValueVTs,
117 SmallVectorImpl<uint64_t> *Offsets = 0,
118 uint64_t StartingOffset = 0) {
119 // Given a struct type, recursively traverse the elements.
120 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
121 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
122 for (StructType::element_iterator EB = STy->element_begin(),
123 EI = EB,
124 EE = STy->element_end();
125 EI != EE; ++EI)
126 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
127 StartingOffset + SL->getElementOffset(EI - EB));
128 return;
130 // Given an array type, recursively traverse the elements.
131 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
132 const Type *EltTy = ATy->getElementType();
133 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
134 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
135 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
136 StartingOffset + i * EltSize);
137 return;
139 // Interpret void as zero return values.
140 if (Ty == Type::getVoidTy(Ty->getContext()))
141 return;
142 // Base case: we can get an EVT for this LLVM IR type.
143 ValueVTs.push_back(TLI.getValueType(Ty));
144 if (Offsets)
145 Offsets->push_back(StartingOffset);
148 namespace llvm {
149 /// RegsForValue - This struct represents the registers (physical or virtual)
150 /// that a particular set of values is assigned, and the type information about
151 /// the value. The most common situation is to represent one value at a time,
152 /// but struct or array values are handled element-wise as multiple values.
153 /// The splitting of aggregates is performed recursively, so that we never
154 /// have aggregate-typed registers. The values at this point do not necessarily
155 /// have legal types, so each value may require one or more registers of some
156 /// legal type.
158 struct VISIBILITY_HIDDEN RegsForValue {
159 /// TLI - The TargetLowering object.
161 const TargetLowering *TLI;
163 /// ValueVTs - The value types of the values, which may not be legal, and
164 /// may need be promoted or synthesized from one or more registers.
166 SmallVector<EVT, 4> ValueVTs;
168 /// RegVTs - The value types of the registers. This is the same size as
169 /// ValueVTs and it records, for each value, what the type of the assigned
170 /// register or registers are. (Individual values are never synthesized
171 /// from more than one type of register.)
173 /// With virtual registers, the contents of RegVTs is redundant with TLI's
174 /// getRegisterType member function, however when with physical registers
175 /// it is necessary to have a separate record of the types.
177 SmallVector<EVT, 4> RegVTs;
179 /// Regs - This list holds the registers assigned to the values.
180 /// Each legal or promoted value requires one register, and each
181 /// expanded value requires multiple registers.
183 SmallVector<unsigned, 4> Regs;
185 RegsForValue() : TLI(0) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> &regs,
189 EVT regvt, EVT valuevt)
190 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 const SmallVector<unsigned, 4> &regs,
193 const SmallVector<EVT, 4> &regvts,
194 const SmallVector<EVT, 4> &valuevts)
195 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
196 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
197 unsigned Reg, const Type *Ty) : TLI(&tli) {
198 ComputeValueVTs(tli, Ty, ValueVTs);
200 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
201 EVT ValueVT = ValueVTs[Value];
202 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
203 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
204 for (unsigned i = 0; i != NumRegs; ++i)
205 Regs.push_back(Reg + i);
206 RegVTs.push_back(RegisterVT);
207 Reg += NumRegs;
211 /// append - Add the specified values to this one.
212 void append(const RegsForValue &RHS) {
213 TLI = RHS.TLI;
214 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
215 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
216 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
220 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
221 /// this value and returns the result as a ValueVTs value. This uses
222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
223 /// If the Flag pointer is NULL, no flag is used.
224 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
225 SDValue &Chain, SDValue *Flag) const;
227 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
228 /// specified value into the registers specified by this object. This uses
229 /// Chain/Flag as the input and updates them for the output Chain/Flag.
230 /// If the Flag pointer is NULL, no flag is used.
231 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
232 SDValue &Chain, SDValue *Flag) const;
234 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
235 /// operand list. This adds the code marker, matching input operand index
236 /// (if applicable), and includes the number of values added into it.
237 void AddInlineAsmOperands(unsigned Code,
238 bool HasMatching, unsigned MatchingIdx,
239 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
243 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
244 /// PHI nodes or outside of the basic block that defines it, or used by a
245 /// switch or atomic instruction, which may expand to multiple basic blocks.
246 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
247 if (isa<PHINode>(I)) return true;
248 BasicBlock *BB = I->getParent();
249 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
250 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
251 return true;
252 return false;
255 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
256 /// entry block, return true. This includes arguments used by switches, since
257 /// the switch may expand into multiple basic blocks.
258 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
259 // With FastISel active, we may be splitting blocks, so force creation
260 // of virtual registers for all non-dead arguments.
261 // Don't force virtual registers for byval arguments though, because
262 // fast-isel can't handle those in all cases.
263 if (EnableFastISel && !A->hasByValAttr())
264 return A->use_empty();
266 BasicBlock *Entry = A->getParent()->begin();
267 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
268 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
269 return false; // Use not in entry block.
270 return true;
273 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
274 : TLI(tli) {
277 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 SelectionDAG &DAG,
279 bool EnableFastISel) {
280 Fn = &fn;
281 MF = &mf;
282 RegInfo = &MF->getRegInfo();
284 // Create a vreg for each argument register that is not dead and is used
285 // outside of the entry block for the function.
286 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 AI != E; ++AI)
288 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
289 InitializeRegForValue(AI);
291 // Initialize the mapping of values to registers. This is only set up for
292 // instruction values that are used outside of the block that defines
293 // them.
294 Function::iterator BB = Fn->begin(), EB = Fn->end();
295 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
296 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
297 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
298 const Type *Ty = AI->getAllocatedType();
299 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
300 unsigned Align =
301 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
302 AI->getAlignment());
304 TySize *= CUI->getZExtValue(); // Get total allocated size.
305 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
306 StaticAllocaMap[AI] =
307 MF->getFrameInfo()->CreateStackObject(TySize, Align);
310 for (; BB != EB; ++BB)
311 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
312 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
313 if (!isa<AllocaInst>(I) ||
314 !StaticAllocaMap.count(cast<AllocaInst>(I)))
315 InitializeRegForValue(I);
317 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
318 // also creates the initial PHI MachineInstrs, though none of the input
319 // operands are populated.
320 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
321 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
322 MBBMap[BB] = MBB;
323 MF->push_back(MBB);
325 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
326 // appropriate.
327 PHINode *PN;
328 DebugLoc DL;
329 for (BasicBlock::iterator
330 I = BB->begin(), E = BB->end(); I != E; ++I) {
331 if (CallInst *CI = dyn_cast<CallInst>(I)) {
332 if (Function *F = CI->getCalledFunction()) {
333 switch (F->getIntrinsicID()) {
334 default: break;
335 case Intrinsic::dbg_stoppoint: {
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
337 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
338 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
339 break;
341 case Intrinsic::dbg_func_start: {
342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
343 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
344 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
345 break;
351 PN = dyn_cast<PHINode>(I);
352 if (!PN || PN->use_empty()) continue;
354 unsigned PHIReg = ValueMap[PN];
355 assert(PHIReg && "PHI node does not have an assigned virtual register!");
357 SmallVector<EVT, 4> ValueVTs;
358 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
359 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
360 EVT VT = ValueVTs[vti];
361 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
362 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
363 for (unsigned i = 0; i != NumRegisters; ++i)
364 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
365 PHIReg += NumRegisters;
371 unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
372 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<EVT, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 EVT ValueVT = ValueVTs[Value];
389 EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
397 return FirstReg;
400 /// getCopyFromParts - Create a value that contains the specified legal parts
401 /// combined into the value they represent. If the parts combine to a type
402 /// larger then ValueVT then AssertOp can be used to specify whether the extra
403 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
404 /// (ISD::AssertSext).
405 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
406 const SDValue *Parts,
407 unsigned NumParts, EVT PartVT, EVT ValueVT,
408 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
409 assert(NumParts > 0 && "No parts to assemble!");
410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411 SDValue Val = Parts[0];
413 if (NumParts > 1) {
414 // Assemble the value from multiple parts.
415 if (!ValueVT.isVector() && ValueVT.isInteger()) {
416 unsigned PartBits = PartVT.getSizeInBits();
417 unsigned ValueBits = ValueVT.getSizeInBits();
419 // Assemble the power of 2 part.
420 unsigned RoundParts = NumParts & (NumParts - 1) ?
421 1 << Log2_32(NumParts) : NumParts;
422 unsigned RoundBits = PartBits * RoundParts;
423 EVT RoundVT = RoundBits == ValueBits ?
424 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
425 SDValue Lo, Hi;
427 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
429 if (RoundParts > 2) {
430 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
431 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
432 PartVT, HalfVT);
433 } else {
434 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
435 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
437 if (TLI.isBigEndian())
438 std::swap(Lo, Hi);
439 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
441 if (RoundParts < NumParts) {
442 // Assemble the trailing non-power-of-2 part.
443 unsigned OddParts = NumParts - RoundParts;
444 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
445 Hi = getCopyFromParts(DAG, dl,
446 Parts+RoundParts, OddParts, PartVT, OddVT);
448 // Combine the round and odd parts.
449 Lo = Val;
450 if (TLI.isBigEndian())
451 std::swap(Lo, Hi);
452 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
453 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
454 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
455 DAG.getConstant(Lo.getValueType().getSizeInBits(),
456 TLI.getPointerTy()));
457 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
458 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
460 } else if (ValueVT.isVector()) {
461 // Handle a multi-element vector.
462 EVT IntermediateVT, RegisterVT;
463 unsigned NumIntermediates;
464 unsigned NumRegs =
465 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
466 NumIntermediates, RegisterVT);
467 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
468 NumParts = NumRegs; // Silence a compiler warning.
469 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
470 assert(RegisterVT == Parts[0].getValueType() &&
471 "Part type doesn't match part!");
473 // Assemble the parts into intermediate operands.
474 SmallVector<SDValue, 8> Ops(NumIntermediates);
475 if (NumIntermediates == NumParts) {
476 // If the register was not expanded, truncate or copy the value,
477 // as appropriate.
478 for (unsigned i = 0; i != NumParts; ++i)
479 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
480 PartVT, IntermediateVT);
481 } else if (NumParts > 0) {
482 // If the intermediate type was expanded, build the intermediate operands
483 // from the parts.
484 assert(NumParts % NumIntermediates == 0 &&
485 "Must expand into a divisible number of parts!");
486 unsigned Factor = NumParts / NumIntermediates;
487 for (unsigned i = 0; i != NumIntermediates; ++i)
488 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
489 PartVT, IntermediateVT);
492 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
493 // operands.
494 Val = DAG.getNode(IntermediateVT.isVector() ?
495 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
496 ValueVT, &Ops[0], NumIntermediates);
497 } else if (PartVT.isFloatingPoint()) {
498 // FP split into multiple FP parts (for ppcf128)
499 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
500 "Unexpected split");
501 SDValue Lo, Hi;
502 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
503 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
504 if (TLI.isBigEndian())
505 std::swap(Lo, Hi);
506 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
507 } else {
508 // FP split into integer parts (soft fp)
509 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
510 !PartVT.isVector() && "Unexpected split");
511 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
512 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
516 // There is now one part, held in Val. Correct it to match ValueVT.
517 PartVT = Val.getValueType();
519 if (PartVT == ValueVT)
520 return Val;
522 if (PartVT.isVector()) {
523 assert(ValueVT.isVector() && "Unknown vector conversion!");
524 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
527 if (ValueVT.isVector()) {
528 assert(ValueVT.getVectorElementType() == PartVT &&
529 ValueVT.getVectorNumElements() == 1 &&
530 "Only trivial scalar-to-vector conversions should get here!");
531 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
534 if (PartVT.isInteger() &&
535 ValueVT.isInteger()) {
536 if (ValueVT.bitsLT(PartVT)) {
537 // For a truncate, see if we have any information to
538 // indicate whether the truncated bits will always be
539 // zero or sign-extension.
540 if (AssertOp != ISD::DELETED_NODE)
541 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
542 DAG.getValueType(ValueVT));
543 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
544 } else {
545 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
549 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
550 if (ValueVT.bitsLT(Val.getValueType()))
551 // FP_ROUND's are always exact here.
552 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
553 DAG.getIntPtrConstant(1));
554 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
557 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
558 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
560 llvm_unreachable("Unknown mismatch!");
561 return SDValue();
564 /// getCopyToParts - Create a series of nodes that contain the specified value
565 /// split into legal parts. If the parts contain more bits than Val, then, for
566 /// integers, ExtendKind can be used to specify how to generate the extra bits.
567 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
568 SDValue *Parts, unsigned NumParts, EVT PartVT,
569 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
571 EVT PtrVT = TLI.getPointerTy();
572 EVT ValueVT = Val.getValueType();
573 unsigned PartBits = PartVT.getSizeInBits();
574 unsigned OrigNumParts = NumParts;
575 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
577 if (!NumParts)
578 return;
580 if (!ValueVT.isVector()) {
581 if (PartVT == ValueVT) {
582 assert(NumParts == 1 && "No-op copy with multiple parts!");
583 Parts[0] = Val;
584 return;
587 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
588 // If the parts cover more bits than the value has, promote the value.
589 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
590 assert(NumParts == 1 && "Do not know what to promote to!");
591 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
592 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
593 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
594 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
595 } else {
596 llvm_unreachable("Unknown mismatch!");
598 } else if (PartBits == ValueVT.getSizeInBits()) {
599 // Different types of the same size.
600 assert(NumParts == 1 && PartVT != ValueVT);
601 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
602 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
603 // If the parts cover less bits than value has, truncate the value.
604 if (PartVT.isInteger() && ValueVT.isInteger()) {
605 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
606 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
607 } else {
608 llvm_unreachable("Unknown mismatch!");
612 // The value may have changed - recompute ValueVT.
613 ValueVT = Val.getValueType();
614 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
615 "Failed to tile the value with PartVT!");
617 if (NumParts == 1) {
618 assert(PartVT == ValueVT && "Type conversion failed!");
619 Parts[0] = Val;
620 return;
623 // Expand the value into multiple parts.
624 if (NumParts & (NumParts - 1)) {
625 // The number of parts is not a power of 2. Split off and copy the tail.
626 assert(PartVT.isInteger() && ValueVT.isInteger() &&
627 "Do not know what to expand to!");
628 unsigned RoundParts = 1 << Log2_32(NumParts);
629 unsigned RoundBits = RoundParts * PartBits;
630 unsigned OddParts = NumParts - RoundParts;
631 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
632 DAG.getConstant(RoundBits,
633 TLI.getPointerTy()));
634 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
635 if (TLI.isBigEndian())
636 // The odd parts were reversed by getCopyToParts - unreverse them.
637 std::reverse(Parts + RoundParts, Parts + NumParts);
638 NumParts = RoundParts;
639 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
640 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
643 // The number of parts is a power of 2. Repeatedly bisect the value using
644 // EXTRACT_ELEMENT.
645 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
646 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()),
647 Val);
648 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
649 for (unsigned i = 0; i < NumParts; i += StepSize) {
650 unsigned ThisBits = StepSize * PartBits / 2;
651 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
652 SDValue &Part0 = Parts[i];
653 SDValue &Part1 = Parts[i+StepSize/2];
655 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
656 ThisVT, Part0,
657 DAG.getConstant(1, PtrVT));
658 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
659 ThisVT, Part0,
660 DAG.getConstant(0, PtrVT));
662 if (ThisBits == PartBits && ThisVT != PartVT) {
663 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
664 PartVT, Part0);
665 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
666 PartVT, Part1);
671 if (TLI.isBigEndian())
672 std::reverse(Parts, Parts + OrigNumParts);
674 return;
677 // Vector ValueVT.
678 if (NumParts == 1) {
679 if (PartVT != ValueVT) {
680 if (PartVT.isVector()) {
681 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
682 } else {
683 assert(ValueVT.getVectorElementType() == PartVT &&
684 ValueVT.getVectorNumElements() == 1 &&
685 "Only trivial vector-to-scalar conversions should get here!");
686 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
687 PartVT, Val,
688 DAG.getConstant(0, PtrVT));
692 Parts[0] = Val;
693 return;
696 // Handle a multi-element vector.
697 EVT IntermediateVT, RegisterVT;
698 unsigned NumIntermediates;
699 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
700 IntermediateVT, NumIntermediates, RegisterVT);
701 unsigned NumElements = ValueVT.getVectorNumElements();
703 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
704 NumParts = NumRegs; // Silence a compiler warning.
705 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
707 // Split the vector into intermediate operands.
708 SmallVector<SDValue, 8> Ops(NumIntermediates);
709 for (unsigned i = 0; i != NumIntermediates; ++i)
710 if (IntermediateVT.isVector())
711 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
712 IntermediateVT, Val,
713 DAG.getConstant(i * (NumElements / NumIntermediates),
714 PtrVT));
715 else
716 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
717 IntermediateVT, Val,
718 DAG.getConstant(i, PtrVT));
720 // Split the intermediate operands into legal parts.
721 if (NumParts == NumIntermediates) {
722 // If the register was not expanded, promote or copy the value,
723 // as appropriate.
724 for (unsigned i = 0; i != NumParts; ++i)
725 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
726 } else if (NumParts > 0) {
727 // If the intermediate type was expanded, split each the value into
728 // legal parts.
729 assert(NumParts % NumIntermediates == 0 &&
730 "Must expand into a divisible number of parts!");
731 unsigned Factor = NumParts / NumIntermediates;
732 for (unsigned i = 0; i != NumIntermediates; ++i)
733 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
738 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
739 AA = &aa;
740 GFI = gfi;
741 TD = DAG.getTarget().getTargetData();
744 /// clear - Clear out the curret SelectionDAG and the associated
745 /// state and prepare this SelectionDAGLowering object to be used
746 /// for a new block. This doesn't clear out information about
747 /// additional blocks that are needed to complete switch lowering
748 /// or PHI node updating; that information is cleared out as it is
749 /// consumed.
750 void SelectionDAGLowering::clear() {
751 NodeMap.clear();
752 PendingLoads.clear();
753 PendingExports.clear();
754 DAG.clear();
755 CurDebugLoc = DebugLoc::getUnknownLoc();
756 HasTailCall = false;
759 /// getRoot - Return the current virtual root of the Selection DAG,
760 /// flushing any PendingLoad items. This must be done before emitting
761 /// a store or any other node that may need to be ordered after any
762 /// prior load instructions.
764 SDValue SelectionDAGLowering::getRoot() {
765 if (PendingLoads.empty())
766 return DAG.getRoot();
768 if (PendingLoads.size() == 1) {
769 SDValue Root = PendingLoads[0];
770 DAG.setRoot(Root);
771 PendingLoads.clear();
772 return Root;
775 // Otherwise, we have to make a token factor node.
776 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
777 &PendingLoads[0], PendingLoads.size());
778 PendingLoads.clear();
779 DAG.setRoot(Root);
780 return Root;
783 /// getControlRoot - Similar to getRoot, but instead of flushing all the
784 /// PendingLoad items, flush all the PendingExports items. It is necessary
785 /// to do this before emitting a terminator instruction.
787 SDValue SelectionDAGLowering::getControlRoot() {
788 SDValue Root = DAG.getRoot();
790 if (PendingExports.empty())
791 return Root;
793 // Turn all of the CopyToReg chains into one factored node.
794 if (Root.getOpcode() != ISD::EntryToken) {
795 unsigned i = 0, e = PendingExports.size();
796 for (; i != e; ++i) {
797 assert(PendingExports[i].getNode()->getNumOperands() > 1);
798 if (PendingExports[i].getNode()->getOperand(0) == Root)
799 break; // Don't add the root if we already indirectly depend on it.
802 if (i == e)
803 PendingExports.push_back(Root);
806 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
807 &PendingExports[0],
808 PendingExports.size());
809 PendingExports.clear();
810 DAG.setRoot(Root);
811 return Root;
814 void SelectionDAGLowering::visit(Instruction &I) {
815 visit(I.getOpcode(), I);
818 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
819 // Note: this doesn't use InstVisitor, because it has to work with
820 // ConstantExpr's in addition to instructions.
821 switch (Opcode) {
822 default: llvm_unreachable("Unknown instruction type encountered!");
823 // Build the switch statement using the Instruction.def file.
824 #define HANDLE_INST(NUM, OPCODE, CLASS) \
825 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
826 #include "llvm/Instruction.def"
830 SDValue SelectionDAGLowering::getValue(const Value *V) {
831 SDValue &N = NodeMap[V];
832 if (N.getNode()) return N;
834 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
835 EVT VT = TLI.getValueType(V->getType(), true);
837 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
838 return N = DAG.getConstant(*CI, VT);
840 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
841 return N = DAG.getGlobalAddress(GV, VT);
843 if (isa<ConstantPointerNull>(C))
844 return N = DAG.getConstant(0, TLI.getPointerTy());
846 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
847 return N = DAG.getConstantFP(*CFP, VT);
849 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
850 return N = DAG.getUNDEF(VT);
852 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
853 visit(CE->getOpcode(), *CE);
854 SDValue N1 = NodeMap[V];
855 assert(N1.getNode() && "visit didn't populate the ValueMap!");
856 return N1;
859 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
860 SmallVector<SDValue, 4> Constants;
861 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
862 OI != OE; ++OI) {
863 SDNode *Val = getValue(*OI).getNode();
864 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
865 Constants.push_back(SDValue(Val, i));
867 return DAG.getMergeValues(&Constants[0], Constants.size(),
868 getCurDebugLoc());
871 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
872 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
873 "Unknown struct or array constant!");
875 SmallVector<EVT, 4> ValueVTs;
876 ComputeValueVTs(TLI, C->getType(), ValueVTs);
877 unsigned NumElts = ValueVTs.size();
878 if (NumElts == 0)
879 return SDValue(); // empty struct
880 SmallVector<SDValue, 4> Constants(NumElts);
881 for (unsigned i = 0; i != NumElts; ++i) {
882 EVT EltVT = ValueVTs[i];
883 if (isa<UndefValue>(C))
884 Constants[i] = DAG.getUNDEF(EltVT);
885 else if (EltVT.isFloatingPoint())
886 Constants[i] = DAG.getConstantFP(0, EltVT);
887 else
888 Constants[i] = DAG.getConstant(0, EltVT);
890 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
893 const VectorType *VecTy = cast<VectorType>(V->getType());
894 unsigned NumElements = VecTy->getNumElements();
896 // Now that we know the number and type of the elements, get that number of
897 // elements into the Ops array based on what kind of constant it is.
898 SmallVector<SDValue, 16> Ops;
899 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
900 for (unsigned i = 0; i != NumElements; ++i)
901 Ops.push_back(getValue(CP->getOperand(i)));
902 } else {
903 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
904 EVT EltVT = TLI.getValueType(VecTy->getElementType());
906 SDValue Op;
907 if (EltVT.isFloatingPoint())
908 Op = DAG.getConstantFP(0, EltVT);
909 else
910 Op = DAG.getConstant(0, EltVT);
911 Ops.assign(NumElements, Op);
914 // Create a BUILD_VECTOR node.
915 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
916 VT, &Ops[0], Ops.size());
919 // If this is a static alloca, generate it as the frameindex instead of
920 // computation.
921 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
922 DenseMap<const AllocaInst*, int>::iterator SI =
923 FuncInfo.StaticAllocaMap.find(AI);
924 if (SI != FuncInfo.StaticAllocaMap.end())
925 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
928 unsigned InReg = FuncInfo.ValueMap[V];
929 assert(InReg && "Value not in map!");
931 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
932 SDValue Chain = DAG.getEntryNode();
933 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
937 void SelectionDAGLowering::visitRet(ReturnInst &I) {
938 SDValue Chain = getControlRoot();
939 SmallVector<ISD::OutputArg, 8> Outs;
940 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
941 SmallVector<EVT, 4> ValueVTs;
942 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
943 unsigned NumValues = ValueVTs.size();
944 if (NumValues == 0) continue;
946 SDValue RetOp = getValue(I.getOperand(i));
947 for (unsigned j = 0, f = NumValues; j != f; ++j) {
948 EVT VT = ValueVTs[j];
950 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
952 const Function *F = I.getParent()->getParent();
953 if (F->paramHasAttr(0, Attribute::SExt))
954 ExtendKind = ISD::SIGN_EXTEND;
955 else if (F->paramHasAttr(0, Attribute::ZExt))
956 ExtendKind = ISD::ZERO_EXTEND;
958 // FIXME: C calling convention requires the return type to be promoted to
959 // at least 32-bit. But this is not necessary for non-C calling
960 // conventions. The frontend should mark functions whose return values
961 // require promoting with signext or zeroext attributes.
962 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
963 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
964 if (VT.bitsLT(MinVT))
965 VT = MinVT;
968 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
969 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
970 SmallVector<SDValue, 4> Parts(NumParts);
971 getCopyToParts(DAG, getCurDebugLoc(),
972 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
973 &Parts[0], NumParts, PartVT, ExtendKind);
975 // 'inreg' on function refers to return value
976 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
977 if (F->paramHasAttr(0, Attribute::InReg))
978 Flags.setInReg();
980 // Propagate extension type if any
981 if (F->paramHasAttr(0, Attribute::SExt))
982 Flags.setSExt();
983 else if (F->paramHasAttr(0, Attribute::ZExt))
984 Flags.setZExt();
986 for (unsigned i = 0; i < NumParts; ++i)
987 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
991 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
992 CallingConv::ID CallConv =
993 DAG.getMachineFunction().getFunction()->getCallingConv();
994 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
995 Outs, getCurDebugLoc(), DAG);
997 // Verify that the target's LowerReturn behaved as expected.
998 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
999 "LowerReturn didn't return a valid chain!");
1001 // Update the DAG with the new chain value resulting from return lowering.
1002 DAG.setRoot(Chain);
1005 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1006 /// created for it, emit nodes to copy the value into the virtual
1007 /// registers.
1008 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1009 if (!V->use_empty()) {
1010 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1011 if (VMI != FuncInfo.ValueMap.end())
1012 CopyValueToVirtualRegister(V, VMI->second);
1016 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1017 /// the current basic block, add it to ValueMap now so that we'll get a
1018 /// CopyTo/FromReg.
1019 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1020 // No need to export constants.
1021 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1023 // Already exported?
1024 if (FuncInfo.isExportedInst(V)) return;
1026 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1027 CopyValueToVirtualRegister(V, Reg);
1030 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1031 const BasicBlock *FromBB) {
1032 // The operands of the setcc have to be in this block. We don't know
1033 // how to export them from some other block.
1034 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1035 // Can export from current BB.
1036 if (VI->getParent() == FromBB)
1037 return true;
1039 // Is already exported, noop.
1040 return FuncInfo.isExportedInst(V);
1043 // If this is an argument, we can export it if the BB is the entry block or
1044 // if it is already exported.
1045 if (isa<Argument>(V)) {
1046 if (FromBB == &FromBB->getParent()->getEntryBlock())
1047 return true;
1049 // Otherwise, can only export this if it is already exported.
1050 return FuncInfo.isExportedInst(V);
1053 // Otherwise, constants can always be exported.
1054 return true;
1057 static bool InBlock(const Value *V, const BasicBlock *BB) {
1058 if (const Instruction *I = dyn_cast<Instruction>(V))
1059 return I->getParent() == BB;
1060 return true;
1063 /// getFCmpCondCode - Return the ISD condition code corresponding to
1064 /// the given LLVM IR floating-point condition code. This includes
1065 /// consideration of global floating-point math flags.
1067 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1068 ISD::CondCode FPC, FOC;
1069 switch (Pred) {
1070 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1071 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1072 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1073 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1074 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1075 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1076 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1077 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1078 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1079 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1080 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1081 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1082 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1083 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1084 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1085 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1086 default:
1087 llvm_unreachable("Invalid FCmp predicate opcode!");
1088 FOC = FPC = ISD::SETFALSE;
1089 break;
1091 if (FiniteOnlyFPMath())
1092 return FOC;
1093 else
1094 return FPC;
1097 /// getICmpCondCode - Return the ISD condition code corresponding to
1098 /// the given LLVM IR integer condition code.
1100 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1101 switch (Pred) {
1102 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1103 case ICmpInst::ICMP_NE: return ISD::SETNE;
1104 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1105 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1106 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1107 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1108 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1109 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1110 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1111 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1112 default:
1113 llvm_unreachable("Invalid ICmp predicate opcode!");
1114 return ISD::SETNE;
1118 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1119 /// This function emits a branch and is used at the leaves of an OR or an
1120 /// AND operator tree.
1122 void
1123 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1124 MachineBasicBlock *TBB,
1125 MachineBasicBlock *FBB,
1126 MachineBasicBlock *CurBB) {
1127 const BasicBlock *BB = CurBB->getBasicBlock();
1129 // If the leaf of the tree is a comparison, merge the condition into
1130 // the caseblock.
1131 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1132 // The operands of the cmp have to be in this block. We don't know
1133 // how to export them from some other block. If this is the first block
1134 // of the sequence, no exporting is needed.
1135 if (CurBB == CurMBB ||
1136 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1137 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1138 ISD::CondCode Condition;
1139 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1140 Condition = getICmpCondCode(IC->getPredicate());
1141 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1142 Condition = getFCmpCondCode(FC->getPredicate());
1143 } else {
1144 Condition = ISD::SETEQ; // silence warning.
1145 llvm_unreachable("Unknown compare instruction");
1148 CaseBlock CB(Condition, BOp->getOperand(0),
1149 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1150 SwitchCases.push_back(CB);
1151 return;
1155 // Create a CaseBlock record representing this branch.
1156 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1157 NULL, TBB, FBB, CurBB);
1158 SwitchCases.push_back(CB);
1161 /// FindMergedConditions - If Cond is an expression like
1162 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1163 MachineBasicBlock *TBB,
1164 MachineBasicBlock *FBB,
1165 MachineBasicBlock *CurBB,
1166 unsigned Opc) {
1167 // If this node is not part of the or/and tree, emit it as a branch.
1168 Instruction *BOp = dyn_cast<Instruction>(Cond);
1169 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1170 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1171 BOp->getParent() != CurBB->getBasicBlock() ||
1172 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1173 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1174 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1175 return;
1178 // Create TmpBB after CurBB.
1179 MachineFunction::iterator BBI = CurBB;
1180 MachineFunction &MF = DAG.getMachineFunction();
1181 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1182 CurBB->getParent()->insert(++BBI, TmpBB);
1184 if (Opc == Instruction::Or) {
1185 // Codegen X | Y as:
1186 // jmp_if_X TBB
1187 // jmp TmpBB
1188 // TmpBB:
1189 // jmp_if_Y TBB
1190 // jmp FBB
1193 // Emit the LHS condition.
1194 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1196 // Emit the RHS condition into TmpBB.
1197 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1198 } else {
1199 assert(Opc == Instruction::And && "Unknown merge op!");
1200 // Codegen X & Y as:
1201 // jmp_if_X TmpBB
1202 // jmp FBB
1203 // TmpBB:
1204 // jmp_if_Y TBB
1205 // jmp FBB
1207 // This requires creation of TmpBB after CurBB.
1209 // Emit the LHS condition.
1210 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1212 // Emit the RHS condition into TmpBB.
1213 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1217 /// If the set of cases should be emitted as a series of branches, return true.
1218 /// If we should emit this as a bunch of and/or'd together conditions, return
1219 /// false.
1220 bool
1221 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1222 if (Cases.size() != 2) return true;
1224 // If this is two comparisons of the same values or'd or and'd together, they
1225 // will get folded into a single comparison, so don't emit two blocks.
1226 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1227 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1228 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1229 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1230 return false;
1233 return true;
1236 void SelectionDAGLowering::visitBr(BranchInst &I) {
1237 // Update machine-CFG edges.
1238 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1240 // Figure out which block is immediately after the current one.
1241 MachineBasicBlock *NextBlock = 0;
1242 MachineFunction::iterator BBI = CurMBB;
1243 if (++BBI != FuncInfo.MF->end())
1244 NextBlock = BBI;
1246 if (I.isUnconditional()) {
1247 // Update machine-CFG edges.
1248 CurMBB->addSuccessor(Succ0MBB);
1250 // If this is not a fall-through branch, emit the branch.
1251 if (Succ0MBB != NextBlock)
1252 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1253 MVT::Other, getControlRoot(),
1254 DAG.getBasicBlock(Succ0MBB)));
1255 return;
1258 // If this condition is one of the special cases we handle, do special stuff
1259 // now.
1260 Value *CondVal = I.getCondition();
1261 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1263 // If this is a series of conditions that are or'd or and'd together, emit
1264 // this as a sequence of branches instead of setcc's with and/or operations.
1265 // For example, instead of something like:
1266 // cmp A, B
1267 // C = seteq
1268 // cmp D, E
1269 // F = setle
1270 // or C, F
1271 // jnz foo
1272 // Emit:
1273 // cmp A, B
1274 // je foo
1275 // cmp D, E
1276 // jle foo
1278 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1279 if (BOp->hasOneUse() &&
1280 (BOp->getOpcode() == Instruction::And ||
1281 BOp->getOpcode() == Instruction::Or)) {
1282 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1283 // If the compares in later blocks need to use values not currently
1284 // exported from this block, export them now. This block should always
1285 // be the first entry.
1286 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1288 // Allow some cases to be rejected.
1289 if (ShouldEmitAsBranches(SwitchCases)) {
1290 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1291 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1292 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1295 // Emit the branch for this block.
1296 visitSwitchCase(SwitchCases[0]);
1297 SwitchCases.erase(SwitchCases.begin());
1298 return;
1301 // Okay, we decided not to do this, remove any inserted MBB's and clear
1302 // SwitchCases.
1303 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1304 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1306 SwitchCases.clear();
1310 // Create a CaseBlock record representing this branch.
1311 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1312 NULL, Succ0MBB, Succ1MBB, CurMBB);
1313 // Use visitSwitchCase to actually insert the fast branch sequence for this
1314 // cond branch.
1315 visitSwitchCase(CB);
1318 /// visitSwitchCase - Emits the necessary code to represent a single node in
1319 /// the binary search tree resulting from lowering a switch instruction.
1320 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1321 SDValue Cond;
1322 SDValue CondLHS = getValue(CB.CmpLHS);
1323 DebugLoc dl = getCurDebugLoc();
1325 // Build the setcc now.
1326 if (CB.CmpMHS == NULL) {
1327 // Fold "(X == true)" to X and "(X == false)" to !X to
1328 // handle common cases produced by branch lowering.
1329 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1330 CB.CC == ISD::SETEQ)
1331 Cond = CondLHS;
1332 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1333 CB.CC == ISD::SETEQ) {
1334 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1335 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1336 } else
1337 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1338 } else {
1339 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1341 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1342 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1344 SDValue CmpOp = getValue(CB.CmpMHS);
1345 EVT VT = CmpOp.getValueType();
1347 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1348 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1349 ISD::SETLE);
1350 } else {
1351 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1352 VT, CmpOp, DAG.getConstant(Low, VT));
1353 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1354 DAG.getConstant(High-Low, VT), ISD::SETULE);
1358 // Update successor info
1359 CurMBB->addSuccessor(CB.TrueBB);
1360 CurMBB->addSuccessor(CB.FalseBB);
1362 // Set NextBlock to be the MBB immediately after the current one, if any.
1363 // This is used to avoid emitting unnecessary branches to the next block.
1364 MachineBasicBlock *NextBlock = 0;
1365 MachineFunction::iterator BBI = CurMBB;
1366 if (++BBI != FuncInfo.MF->end())
1367 NextBlock = BBI;
1369 // If the lhs block is the next block, invert the condition so that we can
1370 // fall through to the lhs instead of the rhs block.
1371 if (CB.TrueBB == NextBlock) {
1372 std::swap(CB.TrueBB, CB.FalseBB);
1373 SDValue True = DAG.getConstant(1, Cond.getValueType());
1374 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1376 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1377 MVT::Other, getControlRoot(), Cond,
1378 DAG.getBasicBlock(CB.TrueBB));
1380 // If the branch was constant folded, fix up the CFG.
1381 if (BrCond.getOpcode() == ISD::BR) {
1382 CurMBB->removeSuccessor(CB.FalseBB);
1383 DAG.setRoot(BrCond);
1384 } else {
1385 // Otherwise, go ahead and insert the false branch.
1386 if (BrCond == getControlRoot())
1387 CurMBB->removeSuccessor(CB.TrueBB);
1389 if (CB.FalseBB == NextBlock)
1390 DAG.setRoot(BrCond);
1391 else
1392 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1393 DAG.getBasicBlock(CB.FalseBB)));
1397 /// visitJumpTable - Emit JumpTable node in the current MBB
1398 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1399 // Emit the code for the jump table
1400 assert(JT.Reg != -1U && "Should lower JT Header first!");
1401 EVT PTy = TLI.getPointerTy();
1402 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1403 JT.Reg, PTy);
1404 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1405 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1406 MVT::Other, Index.getValue(1),
1407 Table, Index));
1410 /// visitJumpTableHeader - This function emits necessary code to produce index
1411 /// in the JumpTable from switch case.
1412 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1413 JumpTableHeader &JTH) {
1414 // Subtract the lowest switch case value from the value being switched on and
1415 // conditional branch to default mbb if the result is greater than the
1416 // difference between smallest and largest cases.
1417 SDValue SwitchOp = getValue(JTH.SValue);
1418 EVT VT = SwitchOp.getValueType();
1419 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1420 DAG.getConstant(JTH.First, VT));
1422 // The SDNode we just created, which holds the value being switched on minus
1423 // the the smallest case value, needs to be copied to a virtual register so it
1424 // can be used as an index into the jump table in a subsequent basic block.
1425 // This value may be smaller or larger than the target's pointer type, and
1426 // therefore require extension or truncating.
1427 if (VT.bitsGT(TLI.getPointerTy()))
1428 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1429 TLI.getPointerTy(), SUB);
1430 else
1431 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1432 TLI.getPointerTy(), SUB);
1434 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1435 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1436 JumpTableReg, SwitchOp);
1437 JT.Reg = JumpTableReg;
1439 // Emit the range check for the jump table, and branch to the default block
1440 // for the switch statement if the value being switched on exceeds the largest
1441 // case in the switch.
1442 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1443 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1444 DAG.getConstant(JTH.Last-JTH.First,VT),
1445 ISD::SETUGT);
1447 // Set NextBlock to be the MBB immediately after the current one, if any.
1448 // This is used to avoid emitting unnecessary branches to the next block.
1449 MachineBasicBlock *NextBlock = 0;
1450 MachineFunction::iterator BBI = CurMBB;
1451 if (++BBI != FuncInfo.MF->end())
1452 NextBlock = BBI;
1454 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1455 MVT::Other, CopyTo, CMP,
1456 DAG.getBasicBlock(JT.Default));
1458 if (JT.MBB == NextBlock)
1459 DAG.setRoot(BrCond);
1460 else
1461 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1462 DAG.getBasicBlock(JT.MBB)));
1465 /// visitBitTestHeader - This function emits necessary code to produce value
1466 /// suitable for "bit tests"
1467 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1468 // Subtract the minimum value
1469 SDValue SwitchOp = getValue(B.SValue);
1470 EVT VT = SwitchOp.getValueType();
1471 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1472 DAG.getConstant(B.First, VT));
1474 // Check range
1475 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1476 TLI.getSetCCResultType(SUB.getValueType()),
1477 SUB, DAG.getConstant(B.Range, VT),
1478 ISD::SETUGT);
1480 SDValue ShiftOp;
1481 if (VT.bitsGT(TLI.getPointerTy()))
1482 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1483 TLI.getPointerTy(), SUB);
1484 else
1485 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1486 TLI.getPointerTy(), SUB);
1488 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1489 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1490 B.Reg, ShiftOp);
1492 // Set NextBlock to be the MBB immediately after the current one, if any.
1493 // This is used to avoid emitting unnecessary branches to the next block.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CurMBB;
1496 if (++BBI != FuncInfo.MF->end())
1497 NextBlock = BBI;
1499 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1501 CurMBB->addSuccessor(B.Default);
1502 CurMBB->addSuccessor(MBB);
1504 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1505 MVT::Other, CopyTo, RangeCmp,
1506 DAG.getBasicBlock(B.Default));
1508 if (MBB == NextBlock)
1509 DAG.setRoot(BrRange);
1510 else
1511 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1512 DAG.getBasicBlock(MBB)));
1515 /// visitBitTestCase - this function produces one "bit test"
1516 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1517 unsigned Reg,
1518 BitTestCase &B) {
1519 // Make desired shift
1520 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1521 TLI.getPointerTy());
1522 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1523 TLI.getPointerTy(),
1524 DAG.getConstant(1, TLI.getPointerTy()),
1525 ShiftOp);
1527 // Emit bit tests and jumps
1528 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1529 TLI.getPointerTy(), SwitchVal,
1530 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1531 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1532 TLI.getSetCCResultType(AndOp.getValueType()),
1533 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1534 ISD::SETNE);
1536 CurMBB->addSuccessor(B.TargetBB);
1537 CurMBB->addSuccessor(NextMBB);
1539 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1540 MVT::Other, getControlRoot(),
1541 AndCmp, DAG.getBasicBlock(B.TargetBB));
1543 // Set NextBlock to be the MBB immediately after the current one, if any.
1544 // This is used to avoid emitting unnecessary branches to the next block.
1545 MachineBasicBlock *NextBlock = 0;
1546 MachineFunction::iterator BBI = CurMBB;
1547 if (++BBI != FuncInfo.MF->end())
1548 NextBlock = BBI;
1550 if (NextMBB == NextBlock)
1551 DAG.setRoot(BrAnd);
1552 else
1553 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1554 DAG.getBasicBlock(NextMBB)));
1557 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1558 // Retrieve successors.
1559 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1560 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1562 const Value *Callee(I.getCalledValue());
1563 if (isa<InlineAsm>(Callee))
1564 visitInlineAsm(&I);
1565 else
1566 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1568 // If the value of the invoke is used outside of its defining block, make it
1569 // available as a virtual register.
1570 CopyToExportRegsIfNeeded(&I);
1572 // Update successor info
1573 CurMBB->addSuccessor(Return);
1574 CurMBB->addSuccessor(LandingPad);
1576 // Drop into normal successor.
1577 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1578 MVT::Other, getControlRoot(),
1579 DAG.getBasicBlock(Return)));
1582 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1585 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1586 /// small case ranges).
1587 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1588 CaseRecVector& WorkList,
1589 Value* SV,
1590 MachineBasicBlock* Default) {
1591 Case& BackCase = *(CR.Range.second-1);
1593 // Size is the number of Cases represented by this range.
1594 size_t Size = CR.Range.second - CR.Range.first;
1595 if (Size > 3)
1596 return false;
1598 // Get the MachineFunction which holds the current MBB. This is used when
1599 // inserting any additional MBBs necessary to represent the switch.
1600 MachineFunction *CurMF = FuncInfo.MF;
1602 // Figure out which block is immediately after the current one.
1603 MachineBasicBlock *NextBlock = 0;
1604 MachineFunction::iterator BBI = CR.CaseBB;
1606 if (++BBI != FuncInfo.MF->end())
1607 NextBlock = BBI;
1609 // TODO: If any two of the cases has the same destination, and if one value
1610 // is the same as the other, but has one bit unset that the other has set,
1611 // use bit manipulation to do two compares at once. For example:
1612 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1614 // Rearrange the case blocks so that the last one falls through if possible.
1615 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1616 // The last case block won't fall through into 'NextBlock' if we emit the
1617 // branches in this order. See if rearranging a case value would help.
1618 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1619 if (I->BB == NextBlock) {
1620 std::swap(*I, BackCase);
1621 break;
1626 // Create a CaseBlock record representing a conditional branch to
1627 // the Case's target mbb if the value being switched on SV is equal
1628 // to C.
1629 MachineBasicBlock *CurBlock = CR.CaseBB;
1630 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1631 MachineBasicBlock *FallThrough;
1632 if (I != E-1) {
1633 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1634 CurMF->insert(BBI, FallThrough);
1636 // Put SV in a virtual register to make it available from the new blocks.
1637 ExportFromCurrentBlock(SV);
1638 } else {
1639 // If the last case doesn't match, go to the default block.
1640 FallThrough = Default;
1643 Value *RHS, *LHS, *MHS;
1644 ISD::CondCode CC;
1645 if (I->High == I->Low) {
1646 // This is just small small case range :) containing exactly 1 case
1647 CC = ISD::SETEQ;
1648 LHS = SV; RHS = I->High; MHS = NULL;
1649 } else {
1650 CC = ISD::SETLE;
1651 LHS = I->Low; MHS = SV; RHS = I->High;
1653 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1655 // If emitting the first comparison, just call visitSwitchCase to emit the
1656 // code into the current block. Otherwise, push the CaseBlock onto the
1657 // vector to be later processed by SDISel, and insert the node's MBB
1658 // before the next MBB.
1659 if (CurBlock == CurMBB)
1660 visitSwitchCase(CB);
1661 else
1662 SwitchCases.push_back(CB);
1664 CurBlock = FallThrough;
1667 return true;
1670 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1671 return !DisableJumpTables &&
1672 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1673 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1676 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1677 APInt LastExt(Last), FirstExt(First);
1678 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1679 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1680 return (LastExt - FirstExt + 1ULL);
1683 /// handleJTSwitchCase - Emit jumptable for current switch case range
1684 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1685 CaseRecVector& WorkList,
1686 Value* SV,
1687 MachineBasicBlock* Default) {
1688 Case& FrontCase = *CR.Range.first;
1689 Case& BackCase = *(CR.Range.second-1);
1691 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1692 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1694 size_t TSize = 0;
1695 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1696 I!=E; ++I)
1697 TSize += I->size();
1699 if (!areJTsAllowed(TLI) || TSize <= 3)
1700 return false;
1702 APInt Range = ComputeRange(First, Last);
1703 double Density = (double)TSize / Range.roundToDouble();
1704 if (Density < 0.4)
1705 return false;
1707 DEBUG(errs() << "Lowering jump table\n"
1708 << "First entry: " << First << ". Last entry: " << Last << '\n'
1709 << "Range: " << Range
1710 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1712 // Get the MachineFunction which holds the current MBB. This is used when
1713 // inserting any additional MBBs necessary to represent the switch.
1714 MachineFunction *CurMF = FuncInfo.MF;
1716 // Figure out which block is immediately after the current one.
1717 MachineBasicBlock *NextBlock = 0;
1718 MachineFunction::iterator BBI = CR.CaseBB;
1720 if (++BBI != FuncInfo.MF->end())
1721 NextBlock = BBI;
1723 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1725 // Create a new basic block to hold the code for loading the address
1726 // of the jump table, and jumping to it. Update successor information;
1727 // we will either branch to the default case for the switch, or the jump
1728 // table.
1729 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1730 CurMF->insert(BBI, JumpTableBB);
1731 CR.CaseBB->addSuccessor(Default);
1732 CR.CaseBB->addSuccessor(JumpTableBB);
1734 // Build a vector of destination BBs, corresponding to each target
1735 // of the jump table. If the value of the jump table slot corresponds to
1736 // a case statement, push the case's BB onto the vector, otherwise, push
1737 // the default BB.
1738 std::vector<MachineBasicBlock*> DestBBs;
1739 APInt TEI = First;
1740 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1741 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1742 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1744 if (Low.sle(TEI) && TEI.sle(High)) {
1745 DestBBs.push_back(I->BB);
1746 if (TEI==High)
1747 ++I;
1748 } else {
1749 DestBBs.push_back(Default);
1753 // Update successor info. Add one edge to each unique successor.
1754 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1755 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1756 E = DestBBs.end(); I != E; ++I) {
1757 if (!SuccsHandled[(*I)->getNumber()]) {
1758 SuccsHandled[(*I)->getNumber()] = true;
1759 JumpTableBB->addSuccessor(*I);
1763 // Create a jump table index for this jump table, or return an existing
1764 // one.
1765 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1767 // Set the jump table information so that we can codegen it as a second
1768 // MachineBasicBlock
1769 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1770 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1771 if (CR.CaseBB == CurMBB)
1772 visitJumpTableHeader(JT, JTH);
1774 JTCases.push_back(JumpTableBlock(JTH, JT));
1776 return true;
1779 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1780 /// 2 subtrees.
1781 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1782 CaseRecVector& WorkList,
1783 Value* SV,
1784 MachineBasicBlock* Default) {
1785 // Get the MachineFunction which holds the current MBB. This is used when
1786 // inserting any additional MBBs necessary to represent the switch.
1787 MachineFunction *CurMF = FuncInfo.MF;
1789 // Figure out which block is immediately after the current one.
1790 MachineBasicBlock *NextBlock = 0;
1791 MachineFunction::iterator BBI = CR.CaseBB;
1793 if (++BBI != FuncInfo.MF->end())
1794 NextBlock = BBI;
1796 Case& FrontCase = *CR.Range.first;
1797 Case& BackCase = *(CR.Range.second-1);
1798 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1800 // Size is the number of Cases represented by this range.
1801 unsigned Size = CR.Range.second - CR.Range.first;
1803 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1804 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1805 double FMetric = 0;
1806 CaseItr Pivot = CR.Range.first + Size/2;
1808 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1809 // (heuristically) allow us to emit JumpTable's later.
1810 size_t TSize = 0;
1811 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1812 I!=E; ++I)
1813 TSize += I->size();
1815 size_t LSize = FrontCase.size();
1816 size_t RSize = TSize-LSize;
1817 DEBUG(errs() << "Selecting best pivot: \n"
1818 << "First: " << First << ", Last: " << Last <<'\n'
1819 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1820 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1821 J!=E; ++I, ++J) {
1822 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1823 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1824 APInt Range = ComputeRange(LEnd, RBegin);
1825 assert((Range - 2ULL).isNonNegative() &&
1826 "Invalid case distance");
1827 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1828 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1829 double Metric = Range.logBase2()*(LDensity+RDensity);
1830 // Should always split in some non-trivial place
1831 DEBUG(errs() <<"=>Step\n"
1832 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1833 << "LDensity: " << LDensity
1834 << ", RDensity: " << RDensity << '\n'
1835 << "Metric: " << Metric << '\n');
1836 if (FMetric < Metric) {
1837 Pivot = J;
1838 FMetric = Metric;
1839 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1842 LSize += J->size();
1843 RSize -= J->size();
1845 if (areJTsAllowed(TLI)) {
1846 // If our case is dense we *really* should handle it earlier!
1847 assert((FMetric > 0) && "Should handle dense range earlier!");
1848 } else {
1849 Pivot = CR.Range.first + Size/2;
1852 CaseRange LHSR(CR.Range.first, Pivot);
1853 CaseRange RHSR(Pivot, CR.Range.second);
1854 Constant *C = Pivot->Low;
1855 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1857 // We know that we branch to the LHS if the Value being switched on is
1858 // less than the Pivot value, C. We use this to optimize our binary
1859 // tree a bit, by recognizing that if SV is greater than or equal to the
1860 // LHS's Case Value, and that Case Value is exactly one less than the
1861 // Pivot's Value, then we can branch directly to the LHS's Target,
1862 // rather than creating a leaf node for it.
1863 if ((LHSR.second - LHSR.first) == 1 &&
1864 LHSR.first->High == CR.GE &&
1865 cast<ConstantInt>(C)->getValue() ==
1866 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1867 TrueBB = LHSR.first->BB;
1868 } else {
1869 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1870 CurMF->insert(BBI, TrueBB);
1871 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1873 // Put SV in a virtual register to make it available from the new blocks.
1874 ExportFromCurrentBlock(SV);
1877 // Similar to the optimization above, if the Value being switched on is
1878 // known to be less than the Constant CR.LT, and the current Case Value
1879 // is CR.LT - 1, then we can branch directly to the target block for
1880 // the current Case Value, rather than emitting a RHS leaf node for it.
1881 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1882 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1883 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1884 FalseBB = RHSR.first->BB;
1885 } else {
1886 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1887 CurMF->insert(BBI, FalseBB);
1888 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1890 // Put SV in a virtual register to make it available from the new blocks.
1891 ExportFromCurrentBlock(SV);
1894 // Create a CaseBlock record representing a conditional branch to
1895 // the LHS node if the value being switched on SV is less than C.
1896 // Otherwise, branch to LHS.
1897 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1899 if (CR.CaseBB == CurMBB)
1900 visitSwitchCase(CB);
1901 else
1902 SwitchCases.push_back(CB);
1904 return true;
1907 /// handleBitTestsSwitchCase - if current case range has few destination and
1908 /// range span less, than machine word bitwidth, encode case range into series
1909 /// of masks and emit bit tests with these masks.
1910 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1911 CaseRecVector& WorkList,
1912 Value* SV,
1913 MachineBasicBlock* Default){
1914 EVT PTy = TLI.getPointerTy();
1915 unsigned IntPtrBits = PTy.getSizeInBits();
1917 Case& FrontCase = *CR.Range.first;
1918 Case& BackCase = *(CR.Range.second-1);
1920 // Get the MachineFunction which holds the current MBB. This is used when
1921 // inserting any additional MBBs necessary to represent the switch.
1922 MachineFunction *CurMF = FuncInfo.MF;
1924 // If target does not have legal shift left, do not emit bit tests at all.
1925 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1926 return false;
1928 size_t numCmps = 0;
1929 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1930 I!=E; ++I) {
1931 // Single case counts one, case range - two.
1932 numCmps += (I->Low == I->High ? 1 : 2);
1935 // Count unique destinations
1936 SmallSet<MachineBasicBlock*, 4> Dests;
1937 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1938 Dests.insert(I->BB);
1939 if (Dests.size() > 3)
1940 // Don't bother the code below, if there are too much unique destinations
1941 return false;
1943 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1944 << "Total number of comparisons: " << numCmps << '\n');
1946 // Compute span of values.
1947 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1948 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1949 APInt cmpRange = maxValue - minValue;
1951 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1952 << "Low bound: " << minValue << '\n'
1953 << "High bound: " << maxValue << '\n');
1955 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1956 (!(Dests.size() == 1 && numCmps >= 3) &&
1957 !(Dests.size() == 2 && numCmps >= 5) &&
1958 !(Dests.size() >= 3 && numCmps >= 6)))
1959 return false;
1961 DEBUG(errs() << "Emitting bit tests\n");
1962 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1964 // Optimize the case where all the case values fit in a
1965 // word without having to subtract minValue. In this case,
1966 // we can optimize away the subtraction.
1967 if (minValue.isNonNegative() &&
1968 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1969 cmpRange = maxValue;
1970 } else {
1971 lowBound = minValue;
1974 CaseBitsVector CasesBits;
1975 unsigned i, count = 0;
1977 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1978 MachineBasicBlock* Dest = I->BB;
1979 for (i = 0; i < count; ++i)
1980 if (Dest == CasesBits[i].BB)
1981 break;
1983 if (i == count) {
1984 assert((count < 3) && "Too much destinations to test!");
1985 CasesBits.push_back(CaseBits(0, Dest, 0));
1986 count++;
1989 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1990 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1992 uint64_t lo = (lowValue - lowBound).getZExtValue();
1993 uint64_t hi = (highValue - lowBound).getZExtValue();
1995 for (uint64_t j = lo; j <= hi; j++) {
1996 CasesBits[i].Mask |= 1ULL << j;
1997 CasesBits[i].Bits++;
2001 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2003 BitTestInfo BTC;
2005 // Figure out which block is immediately after the current one.
2006 MachineFunction::iterator BBI = CR.CaseBB;
2007 ++BBI;
2009 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2011 DEBUG(errs() << "Cases:\n");
2012 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2013 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2014 << ", Bits: " << CasesBits[i].Bits
2015 << ", BB: " << CasesBits[i].BB << '\n');
2017 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2018 CurMF->insert(BBI, CaseBB);
2019 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2020 CaseBB,
2021 CasesBits[i].BB));
2023 // Put SV in a virtual register to make it available from the new blocks.
2024 ExportFromCurrentBlock(SV);
2027 BitTestBlock BTB(lowBound, cmpRange, SV,
2028 -1U, (CR.CaseBB == CurMBB),
2029 CR.CaseBB, Default, BTC);
2031 if (CR.CaseBB == CurMBB)
2032 visitBitTestHeader(BTB);
2034 BitTestCases.push_back(BTB);
2036 return true;
2040 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2041 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2042 const SwitchInst& SI) {
2043 size_t numCmps = 0;
2045 // Start with "simple" cases
2046 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2047 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2048 Cases.push_back(Case(SI.getSuccessorValue(i),
2049 SI.getSuccessorValue(i),
2050 SMBB));
2052 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2054 // Merge case into clusters
2055 if (Cases.size() >= 2)
2056 // Must recompute end() each iteration because it may be
2057 // invalidated by erase if we hold on to it
2058 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2059 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2060 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2061 MachineBasicBlock* nextBB = J->BB;
2062 MachineBasicBlock* currentBB = I->BB;
2064 // If the two neighboring cases go to the same destination, merge them
2065 // into a single case.
2066 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2067 I->High = J->High;
2068 J = Cases.erase(J);
2069 } else {
2070 I = J++;
2074 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2075 if (I->Low != I->High)
2076 // A range counts double, since it requires two compares.
2077 ++numCmps;
2080 return numCmps;
2083 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2084 // Figure out which block is immediately after the current one.
2085 MachineBasicBlock *NextBlock = 0;
2087 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2089 // If there is only the default destination, branch to it if it is not the
2090 // next basic block. Otherwise, just fall through.
2091 if (SI.getNumOperands() == 2) {
2092 // Update machine-CFG edges.
2094 // If this is not a fall-through branch, emit the branch.
2095 CurMBB->addSuccessor(Default);
2096 if (Default != NextBlock)
2097 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2098 MVT::Other, getControlRoot(),
2099 DAG.getBasicBlock(Default)));
2100 return;
2103 // If there are any non-default case statements, create a vector of Cases
2104 // representing each one, and sort the vector so that we can efficiently
2105 // create a binary search tree from them.
2106 CaseVector Cases;
2107 size_t numCmps = Clusterify(Cases, SI);
2108 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2109 << ". Total compares: " << numCmps << '\n');
2110 numCmps = 0;
2112 // Get the Value to be switched on and default basic blocks, which will be
2113 // inserted into CaseBlock records, representing basic blocks in the binary
2114 // search tree.
2115 Value *SV = SI.getOperand(0);
2117 // Push the initial CaseRec onto the worklist
2118 CaseRecVector WorkList;
2119 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2121 while (!WorkList.empty()) {
2122 // Grab a record representing a case range to process off the worklist
2123 CaseRec CR = WorkList.back();
2124 WorkList.pop_back();
2126 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2127 continue;
2129 // If the range has few cases (two or less) emit a series of specific
2130 // tests.
2131 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2132 continue;
2134 // If the switch has more than 5 blocks, and at least 40% dense, and the
2135 // target supports indirect branches, then emit a jump table rather than
2136 // lowering the switch to a binary tree of conditional branches.
2137 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2138 continue;
2140 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2141 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2142 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2147 void SelectionDAGLowering::visitFSub(User &I) {
2148 // -0.0 - X --> fneg
2149 const Type *Ty = I.getType();
2150 if (isa<VectorType>(Ty)) {
2151 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2152 const VectorType *DestTy = cast<VectorType>(I.getType());
2153 const Type *ElTy = DestTy->getElementType();
2154 unsigned VL = DestTy->getNumElements();
2155 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2156 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2157 if (CV == CNZ) {
2158 SDValue Op2 = getValue(I.getOperand(1));
2159 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2160 Op2.getValueType(), Op2));
2161 return;
2165 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2166 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2167 SDValue Op2 = getValue(I.getOperand(1));
2168 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2169 Op2.getValueType(), Op2));
2170 return;
2173 visitBinary(I, ISD::FSUB);
2176 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2177 SDValue Op1 = getValue(I.getOperand(0));
2178 SDValue Op2 = getValue(I.getOperand(1));
2180 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2181 Op1.getValueType(), Op1, Op2));
2184 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2185 SDValue Op1 = getValue(I.getOperand(0));
2186 SDValue Op2 = getValue(I.getOperand(1));
2187 if (!isa<VectorType>(I.getType()) &&
2188 Op2.getValueType() != TLI.getShiftAmountTy()) {
2189 // If the operand is smaller than the shift count type, promote it.
2190 EVT PTy = TLI.getPointerTy();
2191 EVT STy = TLI.getShiftAmountTy();
2192 if (STy.bitsGT(Op2.getValueType()))
2193 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2194 TLI.getShiftAmountTy(), Op2);
2195 // If the operand is larger than the shift count type but the shift
2196 // count type has enough bits to represent any shift value, truncate
2197 // it now. This is a common case and it exposes the truncate to
2198 // optimization early.
2199 else if (STy.getSizeInBits() >=
2200 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2201 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2202 TLI.getShiftAmountTy(), Op2);
2203 // Otherwise we'll need to temporarily settle for some other
2204 // convenient type; type legalization will make adjustments as
2205 // needed.
2206 else if (PTy.bitsLT(Op2.getValueType()))
2207 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2208 TLI.getPointerTy(), Op2);
2209 else if (PTy.bitsGT(Op2.getValueType()))
2210 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2211 TLI.getPointerTy(), Op2);
2214 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2215 Op1.getValueType(), Op1, Op2));
2218 void SelectionDAGLowering::visitICmp(User &I) {
2219 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2220 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2221 predicate = IC->getPredicate();
2222 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2223 predicate = ICmpInst::Predicate(IC->getPredicate());
2224 SDValue Op1 = getValue(I.getOperand(0));
2225 SDValue Op2 = getValue(I.getOperand(1));
2226 ISD::CondCode Opcode = getICmpCondCode(predicate);
2228 EVT DestVT = TLI.getValueType(I.getType());
2229 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2232 void SelectionDAGLowering::visitFCmp(User &I) {
2233 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2234 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2235 predicate = FC->getPredicate();
2236 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2237 predicate = FCmpInst::Predicate(FC->getPredicate());
2238 SDValue Op1 = getValue(I.getOperand(0));
2239 SDValue Op2 = getValue(I.getOperand(1));
2240 ISD::CondCode Condition = getFCmpCondCode(predicate);
2241 EVT DestVT = TLI.getValueType(I.getType());
2242 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2245 void SelectionDAGLowering::visitSelect(User &I) {
2246 SmallVector<EVT, 4> ValueVTs;
2247 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2248 unsigned NumValues = ValueVTs.size();
2249 if (NumValues != 0) {
2250 SmallVector<SDValue, 4> Values(NumValues);
2251 SDValue Cond = getValue(I.getOperand(0));
2252 SDValue TrueVal = getValue(I.getOperand(1));
2253 SDValue FalseVal = getValue(I.getOperand(2));
2255 for (unsigned i = 0; i != NumValues; ++i)
2256 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2257 TrueVal.getValueType(), Cond,
2258 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2259 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2261 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2262 DAG.getVTList(&ValueVTs[0], NumValues),
2263 &Values[0], NumValues));
2268 void SelectionDAGLowering::visitTrunc(User &I) {
2269 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2270 SDValue N = getValue(I.getOperand(0));
2271 EVT DestVT = TLI.getValueType(I.getType());
2272 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2275 void SelectionDAGLowering::visitZExt(User &I) {
2276 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2277 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2278 SDValue N = getValue(I.getOperand(0));
2279 EVT DestVT = TLI.getValueType(I.getType());
2280 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2283 void SelectionDAGLowering::visitSExt(User &I) {
2284 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2285 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2286 SDValue N = getValue(I.getOperand(0));
2287 EVT DestVT = TLI.getValueType(I.getType());
2288 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2291 void SelectionDAGLowering::visitFPTrunc(User &I) {
2292 // FPTrunc is never a no-op cast, no need to check
2293 SDValue N = getValue(I.getOperand(0));
2294 EVT DestVT = TLI.getValueType(I.getType());
2295 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2296 DestVT, N, DAG.getIntPtrConstant(0)));
2299 void SelectionDAGLowering::visitFPExt(User &I){
2300 // FPTrunc is never a no-op cast, no need to check
2301 SDValue N = getValue(I.getOperand(0));
2302 EVT DestVT = TLI.getValueType(I.getType());
2303 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2306 void SelectionDAGLowering::visitFPToUI(User &I) {
2307 // FPToUI is never a no-op cast, no need to check
2308 SDValue N = getValue(I.getOperand(0));
2309 EVT DestVT = TLI.getValueType(I.getType());
2310 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2313 void SelectionDAGLowering::visitFPToSI(User &I) {
2314 // FPToSI is never a no-op cast, no need to check
2315 SDValue N = getValue(I.getOperand(0));
2316 EVT DestVT = TLI.getValueType(I.getType());
2317 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2320 void SelectionDAGLowering::visitUIToFP(User &I) {
2321 // UIToFP is never a no-op cast, no need to check
2322 SDValue N = getValue(I.getOperand(0));
2323 EVT DestVT = TLI.getValueType(I.getType());
2324 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2327 void SelectionDAGLowering::visitSIToFP(User &I){
2328 // SIToFP is never a no-op cast, no need to check
2329 SDValue N = getValue(I.getOperand(0));
2330 EVT DestVT = TLI.getValueType(I.getType());
2331 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2334 void SelectionDAGLowering::visitPtrToInt(User &I) {
2335 // What to do depends on the size of the integer and the size of the pointer.
2336 // We can either truncate, zero extend, or no-op, accordingly.
2337 SDValue N = getValue(I.getOperand(0));
2338 EVT SrcVT = N.getValueType();
2339 EVT DestVT = TLI.getValueType(I.getType());
2340 SDValue Result;
2341 if (DestVT.bitsLT(SrcVT))
2342 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2343 else
2344 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2345 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2346 setValue(&I, Result);
2349 void SelectionDAGLowering::visitIntToPtr(User &I) {
2350 // What to do depends on the size of the integer and the size of the pointer.
2351 // We can either truncate, zero extend, or no-op, accordingly.
2352 SDValue N = getValue(I.getOperand(0));
2353 EVT SrcVT = N.getValueType();
2354 EVT DestVT = TLI.getValueType(I.getType());
2355 if (DestVT.bitsLT(SrcVT))
2356 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2357 else
2358 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2359 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2360 DestVT, N));
2363 void SelectionDAGLowering::visitBitCast(User &I) {
2364 SDValue N = getValue(I.getOperand(0));
2365 EVT DestVT = TLI.getValueType(I.getType());
2367 // BitCast assures us that source and destination are the same size so this
2368 // is either a BIT_CONVERT or a no-op.
2369 if (DestVT != N.getValueType())
2370 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2371 DestVT, N)); // convert types
2372 else
2373 setValue(&I, N); // noop cast.
2376 void SelectionDAGLowering::visitInsertElement(User &I) {
2377 SDValue InVec = getValue(I.getOperand(0));
2378 SDValue InVal = getValue(I.getOperand(1));
2379 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2380 TLI.getPointerTy(),
2381 getValue(I.getOperand(2)));
2383 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2384 TLI.getValueType(I.getType()),
2385 InVec, InVal, InIdx));
2388 void SelectionDAGLowering::visitExtractElement(User &I) {
2389 SDValue InVec = getValue(I.getOperand(0));
2390 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2391 TLI.getPointerTy(),
2392 getValue(I.getOperand(1)));
2393 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2394 TLI.getValueType(I.getType()), InVec, InIdx));
2398 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2399 // from SIndx and increasing to the element length (undefs are allowed).
2400 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2401 unsigned MaskNumElts = Mask.size();
2402 for (unsigned i = 0; i != MaskNumElts; ++i)
2403 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2404 return false;
2405 return true;
2408 void SelectionDAGLowering::visitShuffleVector(User &I) {
2409 SmallVector<int, 8> Mask;
2410 SDValue Src1 = getValue(I.getOperand(0));
2411 SDValue Src2 = getValue(I.getOperand(1));
2413 // Convert the ConstantVector mask operand into an array of ints, with -1
2414 // representing undef values.
2415 SmallVector<Constant*, 8> MaskElts;
2416 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2417 MaskElts);
2418 unsigned MaskNumElts = MaskElts.size();
2419 for (unsigned i = 0; i != MaskNumElts; ++i) {
2420 if (isa<UndefValue>(MaskElts[i]))
2421 Mask.push_back(-1);
2422 else
2423 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2426 EVT VT = TLI.getValueType(I.getType());
2427 EVT SrcVT = Src1.getValueType();
2428 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2430 if (SrcNumElts == MaskNumElts) {
2431 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2432 &Mask[0]));
2433 return;
2436 // Normalize the shuffle vector since mask and vector length don't match.
2437 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2438 // Mask is longer than the source vectors and is a multiple of the source
2439 // vectors. We can use concatenate vector to make the mask and vectors
2440 // lengths match.
2441 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2442 // The shuffle is concatenating two vectors together.
2443 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2444 VT, Src1, Src2));
2445 return;
2448 // Pad both vectors with undefs to make them the same length as the mask.
2449 unsigned NumConcat = MaskNumElts / SrcNumElts;
2450 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2451 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2452 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2454 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2455 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2456 MOps1[0] = Src1;
2457 MOps2[0] = Src2;
2459 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2460 getCurDebugLoc(), VT,
2461 &MOps1[0], NumConcat);
2462 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2463 getCurDebugLoc(), VT,
2464 &MOps2[0], NumConcat);
2466 // Readjust mask for new input vector length.
2467 SmallVector<int, 8> MappedOps;
2468 for (unsigned i = 0; i != MaskNumElts; ++i) {
2469 int Idx = Mask[i];
2470 if (Idx < (int)SrcNumElts)
2471 MappedOps.push_back(Idx);
2472 else
2473 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2475 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2476 &MappedOps[0]));
2477 return;
2480 if (SrcNumElts > MaskNumElts) {
2481 // Analyze the access pattern of the vector to see if we can extract
2482 // two subvectors and do the shuffle. The analysis is done by calculating
2483 // the range of elements the mask access on both vectors.
2484 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2485 int MaxRange[2] = {-1, -1};
2487 for (unsigned i = 0; i != MaskNumElts; ++i) {
2488 int Idx = Mask[i];
2489 int Input = 0;
2490 if (Idx < 0)
2491 continue;
2493 if (Idx >= (int)SrcNumElts) {
2494 Input = 1;
2495 Idx -= SrcNumElts;
2497 if (Idx > MaxRange[Input])
2498 MaxRange[Input] = Idx;
2499 if (Idx < MinRange[Input])
2500 MinRange[Input] = Idx;
2503 // Check if the access is smaller than the vector size and can we find
2504 // a reasonable extract index.
2505 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2506 int StartIdx[2]; // StartIdx to extract from
2507 for (int Input=0; Input < 2; ++Input) {
2508 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2509 RangeUse[Input] = 0; // Unused
2510 StartIdx[Input] = 0;
2511 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2512 // Fits within range but we should see if we can find a good
2513 // start index that is a multiple of the mask length.
2514 if (MaxRange[Input] < (int)MaskNumElts) {
2515 RangeUse[Input] = 1; // Extract from beginning of the vector
2516 StartIdx[Input] = 0;
2517 } else {
2518 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2519 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2520 StartIdx[Input] + MaskNumElts < SrcNumElts)
2521 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2526 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2527 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2528 return;
2530 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2531 // Extract appropriate subvector and generate a vector shuffle
2532 for (int Input=0; Input < 2; ++Input) {
2533 SDValue& Src = Input == 0 ? Src1 : Src2;
2534 if (RangeUse[Input] == 0) {
2535 Src = DAG.getUNDEF(VT);
2536 } else {
2537 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2538 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2541 // Calculate new mask.
2542 SmallVector<int, 8> MappedOps;
2543 for (unsigned i = 0; i != MaskNumElts; ++i) {
2544 int Idx = Mask[i];
2545 if (Idx < 0)
2546 MappedOps.push_back(Idx);
2547 else if (Idx < (int)SrcNumElts)
2548 MappedOps.push_back(Idx - StartIdx[0]);
2549 else
2550 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2552 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2553 &MappedOps[0]));
2554 return;
2558 // We can't use either concat vectors or extract subvectors so fall back to
2559 // replacing the shuffle with extract and build vector.
2560 // to insert and build vector.
2561 EVT EltVT = VT.getVectorElementType();
2562 EVT PtrVT = TLI.getPointerTy();
2563 SmallVector<SDValue,8> Ops;
2564 for (unsigned i = 0; i != MaskNumElts; ++i) {
2565 if (Mask[i] < 0) {
2566 Ops.push_back(DAG.getUNDEF(EltVT));
2567 } else {
2568 int Idx = Mask[i];
2569 if (Idx < (int)SrcNumElts)
2570 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2571 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2572 else
2573 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2574 EltVT, Src2,
2575 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2578 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2579 VT, &Ops[0], Ops.size()));
2582 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2583 const Value *Op0 = I.getOperand(0);
2584 const Value *Op1 = I.getOperand(1);
2585 const Type *AggTy = I.getType();
2586 const Type *ValTy = Op1->getType();
2587 bool IntoUndef = isa<UndefValue>(Op0);
2588 bool FromUndef = isa<UndefValue>(Op1);
2590 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2591 I.idx_begin(), I.idx_end());
2593 SmallVector<EVT, 4> AggValueVTs;
2594 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2595 SmallVector<EVT, 4> ValValueVTs;
2596 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2598 unsigned NumAggValues = AggValueVTs.size();
2599 unsigned NumValValues = ValValueVTs.size();
2600 SmallVector<SDValue, 4> Values(NumAggValues);
2602 SDValue Agg = getValue(Op0);
2603 SDValue Val = getValue(Op1);
2604 unsigned i = 0;
2605 // Copy the beginning value(s) from the original aggregate.
2606 for (; i != LinearIndex; ++i)
2607 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2608 SDValue(Agg.getNode(), Agg.getResNo() + i);
2609 // Copy values from the inserted value(s).
2610 for (; i != LinearIndex + NumValValues; ++i)
2611 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2612 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2613 // Copy remaining value(s) from the original aggregate.
2614 for (; i != NumAggValues; ++i)
2615 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2616 SDValue(Agg.getNode(), Agg.getResNo() + i);
2618 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2619 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2620 &Values[0], NumAggValues));
2623 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2624 const Value *Op0 = I.getOperand(0);
2625 const Type *AggTy = Op0->getType();
2626 const Type *ValTy = I.getType();
2627 bool OutOfUndef = isa<UndefValue>(Op0);
2629 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2630 I.idx_begin(), I.idx_end());
2632 SmallVector<EVT, 4> ValValueVTs;
2633 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2635 unsigned NumValValues = ValValueVTs.size();
2636 SmallVector<SDValue, 4> Values(NumValValues);
2638 SDValue Agg = getValue(Op0);
2639 // Copy out the selected value(s).
2640 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2641 Values[i - LinearIndex] =
2642 OutOfUndef ?
2643 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2644 SDValue(Agg.getNode(), Agg.getResNo() + i);
2646 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2647 DAG.getVTList(&ValValueVTs[0], NumValValues),
2648 &Values[0], NumValValues));
2652 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2653 SDValue N = getValue(I.getOperand(0));
2654 const Type *Ty = I.getOperand(0)->getType();
2656 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2657 OI != E; ++OI) {
2658 Value *Idx = *OI;
2659 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2660 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2661 if (Field) {
2662 // N = N + Offset
2663 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2664 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2665 DAG.getIntPtrConstant(Offset));
2667 Ty = StTy->getElementType(Field);
2668 } else {
2669 Ty = cast<SequentialType>(Ty)->getElementType();
2671 // If this is a constant subscript, handle it quickly.
2672 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2673 if (CI->getZExtValue() == 0) continue;
2674 uint64_t Offs =
2675 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2676 SDValue OffsVal;
2677 EVT PTy = TLI.getPointerTy();
2678 unsigned PtrBits = PTy.getSizeInBits();
2679 if (PtrBits < 64) {
2680 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2681 TLI.getPointerTy(),
2682 DAG.getConstant(Offs, MVT::i64));
2683 } else
2684 OffsVal = DAG.getIntPtrConstant(Offs);
2685 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2686 OffsVal);
2687 continue;
2690 // N = N + Idx * ElementSize;
2691 uint64_t ElementSize = TD->getTypeAllocSize(Ty);
2692 SDValue IdxN = getValue(Idx);
2694 // If the index is smaller or larger than intptr_t, truncate or extend
2695 // it.
2696 if (IdxN.getValueType().bitsLT(N.getValueType()))
2697 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2698 N.getValueType(), IdxN);
2699 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2700 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2701 N.getValueType(), IdxN);
2703 // If this is a multiply by a power of two, turn it into a shl
2704 // immediately. This is a very common case.
2705 if (ElementSize != 1) {
2706 if (isPowerOf2_64(ElementSize)) {
2707 unsigned Amt = Log2_64(ElementSize);
2708 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2709 N.getValueType(), IdxN,
2710 DAG.getConstant(Amt, TLI.getPointerTy()));
2711 } else {
2712 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2713 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2714 N.getValueType(), IdxN, Scale);
2718 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2719 N.getValueType(), N, IdxN);
2722 setValue(&I, N);
2725 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2726 // If this is a fixed sized alloca in the entry block of the function,
2727 // allocate it statically on the stack.
2728 if (FuncInfo.StaticAllocaMap.count(&I))
2729 return; // getValue will auto-populate this.
2731 const Type *Ty = I.getAllocatedType();
2732 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2733 unsigned Align =
2734 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2735 I.getAlignment());
2737 SDValue AllocSize = getValue(I.getArraySize());
2739 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2740 AllocSize,
2741 DAG.getConstant(TySize, AllocSize.getValueType()));
2745 EVT IntPtr = TLI.getPointerTy();
2746 if (IntPtr.bitsLT(AllocSize.getValueType()))
2747 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2748 IntPtr, AllocSize);
2749 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2750 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2751 IntPtr, AllocSize);
2753 // Handle alignment. If the requested alignment is less than or equal to
2754 // the stack alignment, ignore it. If the size is greater than or equal to
2755 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2756 unsigned StackAlign =
2757 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2758 if (Align <= StackAlign)
2759 Align = 0;
2761 // Round the size of the allocation up to the stack alignment size
2762 // by add SA-1 to the size.
2763 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2764 AllocSize.getValueType(), AllocSize,
2765 DAG.getIntPtrConstant(StackAlign-1));
2766 // Mask out the low bits for alignment purposes.
2767 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2768 AllocSize.getValueType(), AllocSize,
2769 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2771 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2772 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2773 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2774 VTs, Ops, 3);
2775 setValue(&I, DSA);
2776 DAG.setRoot(DSA.getValue(1));
2778 // Inform the Frame Information that we have just allocated a variable-sized
2779 // object.
2780 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2783 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2784 const Value *SV = I.getOperand(0);
2785 SDValue Ptr = getValue(SV);
2787 const Type *Ty = I.getType();
2788 bool isVolatile = I.isVolatile();
2789 unsigned Alignment = I.getAlignment();
2791 SmallVector<EVT, 4> ValueVTs;
2792 SmallVector<uint64_t, 4> Offsets;
2793 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2794 unsigned NumValues = ValueVTs.size();
2795 if (NumValues == 0)
2796 return;
2798 SDValue Root;
2799 bool ConstantMemory = false;
2800 if (I.isVolatile())
2801 // Serialize volatile loads with other side effects.
2802 Root = getRoot();
2803 else if (AA->pointsToConstantMemory(SV)) {
2804 // Do not serialize (non-volatile) loads of constant memory with anything.
2805 Root = DAG.getEntryNode();
2806 ConstantMemory = true;
2807 } else {
2808 // Do not serialize non-volatile loads against each other.
2809 Root = DAG.getRoot();
2812 SmallVector<SDValue, 4> Values(NumValues);
2813 SmallVector<SDValue, 4> Chains(NumValues);
2814 EVT PtrVT = Ptr.getValueType();
2815 for (unsigned i = 0; i != NumValues; ++i) {
2816 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2817 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2818 PtrVT, Ptr,
2819 DAG.getConstant(Offsets[i], PtrVT)),
2820 SV, Offsets[i],
2821 isVolatile, Alignment);
2822 Values[i] = L;
2823 Chains[i] = L.getValue(1);
2826 if (!ConstantMemory) {
2827 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2828 MVT::Other,
2829 &Chains[0], NumValues);
2830 if (isVolatile)
2831 DAG.setRoot(Chain);
2832 else
2833 PendingLoads.push_back(Chain);
2836 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2837 DAG.getVTList(&ValueVTs[0], NumValues),
2838 &Values[0], NumValues));
2842 void SelectionDAGLowering::visitStore(StoreInst &I) {
2843 Value *SrcV = I.getOperand(0);
2844 Value *PtrV = I.getOperand(1);
2846 SmallVector<EVT, 4> ValueVTs;
2847 SmallVector<uint64_t, 4> Offsets;
2848 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2849 unsigned NumValues = ValueVTs.size();
2850 if (NumValues == 0)
2851 return;
2853 // Get the lowered operands. Note that we do this after
2854 // checking if NumResults is zero, because with zero results
2855 // the operands won't have values in the map.
2856 SDValue Src = getValue(SrcV);
2857 SDValue Ptr = getValue(PtrV);
2859 SDValue Root = getRoot();
2860 SmallVector<SDValue, 4> Chains(NumValues);
2861 EVT PtrVT = Ptr.getValueType();
2862 bool isVolatile = I.isVolatile();
2863 unsigned Alignment = I.getAlignment();
2864 for (unsigned i = 0; i != NumValues; ++i)
2865 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2866 SDValue(Src.getNode(), Src.getResNo() + i),
2867 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2868 PtrVT, Ptr,
2869 DAG.getConstant(Offsets[i], PtrVT)),
2870 PtrV, Offsets[i],
2871 isVolatile, Alignment);
2873 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2874 MVT::Other, &Chains[0], NumValues));
2877 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2878 /// node.
2879 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2880 unsigned Intrinsic) {
2881 bool HasChain = !I.doesNotAccessMemory();
2882 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2884 // Build the operand list.
2885 SmallVector<SDValue, 8> Ops;
2886 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2887 if (OnlyLoad) {
2888 // We don't need to serialize loads against other loads.
2889 Ops.push_back(DAG.getRoot());
2890 } else {
2891 Ops.push_back(getRoot());
2895 // Info is set by getTgtMemInstrinsic
2896 TargetLowering::IntrinsicInfo Info;
2897 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2899 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2900 if (!IsTgtIntrinsic)
2901 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2903 // Add all operands of the call to the operand list.
2904 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2905 SDValue Op = getValue(I.getOperand(i));
2906 assert(TLI.isTypeLegal(Op.getValueType()) &&
2907 "Intrinsic uses a non-legal type?");
2908 Ops.push_back(Op);
2911 SmallVector<EVT, 4> ValueVTs;
2912 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2913 #ifndef NDEBUG
2914 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2915 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2916 "Intrinsic uses a non-legal type?");
2918 #endif // NDEBUG
2919 if (HasChain)
2920 ValueVTs.push_back(MVT::Other);
2922 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2924 // Create the node.
2925 SDValue Result;
2926 if (IsTgtIntrinsic) {
2927 // This is target intrinsic that touches memory
2928 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2929 VTs, &Ops[0], Ops.size(),
2930 Info.memVT, Info.ptrVal, Info.offset,
2931 Info.align, Info.vol,
2932 Info.readMem, Info.writeMem);
2934 else if (!HasChain)
2935 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2936 VTs, &Ops[0], Ops.size());
2937 else if (I.getType() != Type::getVoidTy(*DAG.getContext()))
2938 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2939 VTs, &Ops[0], Ops.size());
2940 else
2941 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2942 VTs, &Ops[0], Ops.size());
2944 if (HasChain) {
2945 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2946 if (OnlyLoad)
2947 PendingLoads.push_back(Chain);
2948 else
2949 DAG.setRoot(Chain);
2951 if (I.getType() != Type::getVoidTy(*DAG.getContext())) {
2952 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2953 EVT VT = TLI.getValueType(PTy);
2954 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2956 setValue(&I, Result);
2960 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2961 static GlobalVariable *ExtractTypeInfo(Value *V) {
2962 V = V->stripPointerCasts();
2963 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2964 assert ((GV || isa<ConstantPointerNull>(V)) &&
2965 "TypeInfo must be a global variable or NULL");
2966 return GV;
2969 namespace llvm {
2971 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2972 /// call, and add them to the specified machine basic block.
2973 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2974 MachineBasicBlock *MBB) {
2975 // Inform the MachineModuleInfo of the personality for this landing pad.
2976 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2977 assert(CE->getOpcode() == Instruction::BitCast &&
2978 isa<Function>(CE->getOperand(0)) &&
2979 "Personality should be a function");
2980 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2982 // Gather all the type infos for this landing pad and pass them along to
2983 // MachineModuleInfo.
2984 std::vector<GlobalVariable *> TyInfo;
2985 unsigned N = I.getNumOperands();
2987 for (unsigned i = N - 1; i > 2; --i) {
2988 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2989 unsigned FilterLength = CI->getZExtValue();
2990 unsigned FirstCatch = i + FilterLength + !FilterLength;
2991 assert (FirstCatch <= N && "Invalid filter length");
2993 if (FirstCatch < N) {
2994 TyInfo.reserve(N - FirstCatch);
2995 for (unsigned j = FirstCatch; j < N; ++j)
2996 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2997 MMI->addCatchTypeInfo(MBB, TyInfo);
2998 TyInfo.clear();
3001 if (!FilterLength) {
3002 // Cleanup.
3003 MMI->addCleanup(MBB);
3004 } else {
3005 // Filter.
3006 TyInfo.reserve(FilterLength - 1);
3007 for (unsigned j = i + 1; j < FirstCatch; ++j)
3008 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3009 MMI->addFilterTypeInfo(MBB, TyInfo);
3010 TyInfo.clear();
3013 N = i;
3017 if (N > 3) {
3018 TyInfo.reserve(N - 3);
3019 for (unsigned j = 3; j < N; ++j)
3020 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3021 MMI->addCatchTypeInfo(MBB, TyInfo);
3027 /// GetSignificand - Get the significand and build it into a floating-point
3028 /// number with exponent of 1:
3030 /// Op = (Op & 0x007fffff) | 0x3f800000;
3032 /// where Op is the hexidecimal representation of floating point value.
3033 static SDValue
3034 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3035 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3036 DAG.getConstant(0x007fffff, MVT::i32));
3037 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3038 DAG.getConstant(0x3f800000, MVT::i32));
3039 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3042 /// GetExponent - Get the exponent:
3044 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3046 /// where Op is the hexidecimal representation of floating point value.
3047 static SDValue
3048 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3049 DebugLoc dl) {
3050 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3051 DAG.getConstant(0x7f800000, MVT::i32));
3052 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3053 DAG.getConstant(23, TLI.getPointerTy()));
3054 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3055 DAG.getConstant(127, MVT::i32));
3056 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3059 /// getF32Constant - Get 32-bit floating point constant.
3060 static SDValue
3061 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3062 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3065 /// Inlined utility function to implement binary input atomic intrinsics for
3066 /// visitIntrinsicCall: I is a call instruction
3067 /// Op is the associated NodeType for I
3068 const char *
3069 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3070 SDValue Root = getRoot();
3071 SDValue L =
3072 DAG.getAtomic(Op, getCurDebugLoc(),
3073 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3074 Root,
3075 getValue(I.getOperand(1)),
3076 getValue(I.getOperand(2)),
3077 I.getOperand(1));
3078 setValue(&I, L);
3079 DAG.setRoot(L.getValue(1));
3080 return 0;
3083 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3084 const char *
3085 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3086 SDValue Op1 = getValue(I.getOperand(1));
3087 SDValue Op2 = getValue(I.getOperand(2));
3089 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3090 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3092 setValue(&I, Result);
3093 return 0;
3096 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3097 /// limited-precision mode.
3098 void
3099 SelectionDAGLowering::visitExp(CallInst &I) {
3100 SDValue result;
3101 DebugLoc dl = getCurDebugLoc();
3103 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3104 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3105 SDValue Op = getValue(I.getOperand(1));
3107 // Put the exponent in the right bit position for later addition to the
3108 // final result:
3110 // #define LOG2OFe 1.4426950f
3111 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3112 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3113 getF32Constant(DAG, 0x3fb8aa3b));
3114 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3116 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3117 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3118 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3120 // IntegerPartOfX <<= 23;
3121 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3122 DAG.getConstant(23, TLI.getPointerTy()));
3124 if (LimitFloatPrecision <= 6) {
3125 // For floating-point precision of 6:
3127 // TwoToFractionalPartOfX =
3128 // 0.997535578f +
3129 // (0.735607626f + 0.252464424f * x) * x;
3131 // error 0.0144103317, which is 6 bits
3132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3133 getF32Constant(DAG, 0x3e814304));
3134 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3135 getF32Constant(DAG, 0x3f3c50c8));
3136 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3137 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3138 getF32Constant(DAG, 0x3f7f5e7e));
3139 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3141 // Add the exponent into the result in integer domain.
3142 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3143 TwoToFracPartOfX, IntegerPartOfX);
3145 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3146 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3147 // For floating-point precision of 12:
3149 // TwoToFractionalPartOfX =
3150 // 0.999892986f +
3151 // (0.696457318f +
3152 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3154 // 0.000107046256 error, which is 13 to 14 bits
3155 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3156 getF32Constant(DAG, 0x3da235e3));
3157 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3158 getF32Constant(DAG, 0x3e65b8f3));
3159 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3160 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3161 getF32Constant(DAG, 0x3f324b07));
3162 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3163 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3164 getF32Constant(DAG, 0x3f7ff8fd));
3165 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3167 // Add the exponent into the result in integer domain.
3168 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3169 TwoToFracPartOfX, IntegerPartOfX);
3171 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3172 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3173 // For floating-point precision of 18:
3175 // TwoToFractionalPartOfX =
3176 // 0.999999982f +
3177 // (0.693148872f +
3178 // (0.240227044f +
3179 // (0.554906021e-1f +
3180 // (0.961591928e-2f +
3181 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3183 // error 2.47208000*10^(-7), which is better than 18 bits
3184 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3185 getF32Constant(DAG, 0x3924b03e));
3186 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3187 getF32Constant(DAG, 0x3ab24b87));
3188 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3189 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3190 getF32Constant(DAG, 0x3c1d8c17));
3191 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3192 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3193 getF32Constant(DAG, 0x3d634a1d));
3194 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3195 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3196 getF32Constant(DAG, 0x3e75fe14));
3197 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3198 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3199 getF32Constant(DAG, 0x3f317234));
3200 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3201 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3202 getF32Constant(DAG, 0x3f800000));
3203 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3204 MVT::i32, t13);
3206 // Add the exponent into the result in integer domain.
3207 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3208 TwoToFracPartOfX, IntegerPartOfX);
3210 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3212 } else {
3213 // No special expansion.
3214 result = DAG.getNode(ISD::FEXP, dl,
3215 getValue(I.getOperand(1)).getValueType(),
3216 getValue(I.getOperand(1)));
3219 setValue(&I, result);
3222 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3223 /// limited-precision mode.
3224 void
3225 SelectionDAGLowering::visitLog(CallInst &I) {
3226 SDValue result;
3227 DebugLoc dl = getCurDebugLoc();
3229 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3230 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3231 SDValue Op = getValue(I.getOperand(1));
3232 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3234 // Scale the exponent by log(2) [0.69314718f].
3235 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3236 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3237 getF32Constant(DAG, 0x3f317218));
3239 // Get the significand and build it into a floating-point number with
3240 // exponent of 1.
3241 SDValue X = GetSignificand(DAG, Op1, dl);
3243 if (LimitFloatPrecision <= 6) {
3244 // For floating-point precision of 6:
3246 // LogofMantissa =
3247 // -1.1609546f +
3248 // (1.4034025f - 0.23903021f * x) * x;
3250 // error 0.0034276066, which is better than 8 bits
3251 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3252 getF32Constant(DAG, 0xbe74c456));
3253 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3254 getF32Constant(DAG, 0x3fb3a2b1));
3255 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3256 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3257 getF32Constant(DAG, 0x3f949a29));
3259 result = DAG.getNode(ISD::FADD, dl,
3260 MVT::f32, LogOfExponent, LogOfMantissa);
3261 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3262 // For floating-point precision of 12:
3264 // LogOfMantissa =
3265 // -1.7417939f +
3266 // (2.8212026f +
3267 // (-1.4699568f +
3268 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3270 // error 0.000061011436, which is 14 bits
3271 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3272 getF32Constant(DAG, 0xbd67b6d6));
3273 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3274 getF32Constant(DAG, 0x3ee4f4b8));
3275 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3276 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3277 getF32Constant(DAG, 0x3fbc278b));
3278 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3279 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3280 getF32Constant(DAG, 0x40348e95));
3281 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3282 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3283 getF32Constant(DAG, 0x3fdef31a));
3285 result = DAG.getNode(ISD::FADD, dl,
3286 MVT::f32, LogOfExponent, LogOfMantissa);
3287 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3288 // For floating-point precision of 18:
3290 // LogOfMantissa =
3291 // -2.1072184f +
3292 // (4.2372794f +
3293 // (-3.7029485f +
3294 // (2.2781945f +
3295 // (-0.87823314f +
3296 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3298 // error 0.0000023660568, which is better than 18 bits
3299 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3300 getF32Constant(DAG, 0xbc91e5ac));
3301 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3302 getF32Constant(DAG, 0x3e4350aa));
3303 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3304 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3305 getF32Constant(DAG, 0x3f60d3e3));
3306 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3307 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3308 getF32Constant(DAG, 0x4011cdf0));
3309 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3310 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3311 getF32Constant(DAG, 0x406cfd1c));
3312 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3313 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3314 getF32Constant(DAG, 0x408797cb));
3315 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3316 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3317 getF32Constant(DAG, 0x4006dcab));
3319 result = DAG.getNode(ISD::FADD, dl,
3320 MVT::f32, LogOfExponent, LogOfMantissa);
3322 } else {
3323 // No special expansion.
3324 result = DAG.getNode(ISD::FLOG, dl,
3325 getValue(I.getOperand(1)).getValueType(),
3326 getValue(I.getOperand(1)));
3329 setValue(&I, result);
3332 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3333 /// limited-precision mode.
3334 void
3335 SelectionDAGLowering::visitLog2(CallInst &I) {
3336 SDValue result;
3337 DebugLoc dl = getCurDebugLoc();
3339 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3340 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3341 SDValue Op = getValue(I.getOperand(1));
3342 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3344 // Get the exponent.
3345 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3347 // Get the significand and build it into a floating-point number with
3348 // exponent of 1.
3349 SDValue X = GetSignificand(DAG, Op1, dl);
3351 // Different possible minimax approximations of significand in
3352 // floating-point for various degrees of accuracy over [1,2].
3353 if (LimitFloatPrecision <= 6) {
3354 // For floating-point precision of 6:
3356 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3358 // error 0.0049451742, which is more than 7 bits
3359 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3360 getF32Constant(DAG, 0xbeb08fe0));
3361 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3362 getF32Constant(DAG, 0x40019463));
3363 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3364 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3365 getF32Constant(DAG, 0x3fd6633d));
3367 result = DAG.getNode(ISD::FADD, dl,
3368 MVT::f32, LogOfExponent, Log2ofMantissa);
3369 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3370 // For floating-point precision of 12:
3372 // Log2ofMantissa =
3373 // -2.51285454f +
3374 // (4.07009056f +
3375 // (-2.12067489f +
3376 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3378 // error 0.0000876136000, which is better than 13 bits
3379 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3380 getF32Constant(DAG, 0xbda7262e));
3381 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3382 getF32Constant(DAG, 0x3f25280b));
3383 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3384 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3385 getF32Constant(DAG, 0x4007b923));
3386 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3387 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3388 getF32Constant(DAG, 0x40823e2f));
3389 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3390 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3391 getF32Constant(DAG, 0x4020d29c));
3393 result = DAG.getNode(ISD::FADD, dl,
3394 MVT::f32, LogOfExponent, Log2ofMantissa);
3395 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3396 // For floating-point precision of 18:
3398 // Log2ofMantissa =
3399 // -3.0400495f +
3400 // (6.1129976f +
3401 // (-5.3420409f +
3402 // (3.2865683f +
3403 // (-1.2669343f +
3404 // (0.27515199f -
3405 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3407 // error 0.0000018516, which is better than 18 bits
3408 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3409 getF32Constant(DAG, 0xbcd2769e));
3410 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3411 getF32Constant(DAG, 0x3e8ce0b9));
3412 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3413 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3414 getF32Constant(DAG, 0x3fa22ae7));
3415 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3416 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3417 getF32Constant(DAG, 0x40525723));
3418 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3419 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3420 getF32Constant(DAG, 0x40aaf200));
3421 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3422 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3423 getF32Constant(DAG, 0x40c39dad));
3424 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3425 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3426 getF32Constant(DAG, 0x4042902c));
3428 result = DAG.getNode(ISD::FADD, dl,
3429 MVT::f32, LogOfExponent, Log2ofMantissa);
3431 } else {
3432 // No special expansion.
3433 result = DAG.getNode(ISD::FLOG2, dl,
3434 getValue(I.getOperand(1)).getValueType(),
3435 getValue(I.getOperand(1)));
3438 setValue(&I, result);
3441 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3442 /// limited-precision mode.
3443 void
3444 SelectionDAGLowering::visitLog10(CallInst &I) {
3445 SDValue result;
3446 DebugLoc dl = getCurDebugLoc();
3448 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3449 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3450 SDValue Op = getValue(I.getOperand(1));
3451 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3453 // Scale the exponent by log10(2) [0.30102999f].
3454 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3455 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3456 getF32Constant(DAG, 0x3e9a209a));
3458 // Get the significand and build it into a floating-point number with
3459 // exponent of 1.
3460 SDValue X = GetSignificand(DAG, Op1, dl);
3462 if (LimitFloatPrecision <= 6) {
3463 // For floating-point precision of 6:
3465 // Log10ofMantissa =
3466 // -0.50419619f +
3467 // (0.60948995f - 0.10380950f * x) * x;
3469 // error 0.0014886165, which is 6 bits
3470 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3471 getF32Constant(DAG, 0xbdd49a13));
3472 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3473 getF32Constant(DAG, 0x3f1c0789));
3474 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3475 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3476 getF32Constant(DAG, 0x3f011300));
3478 result = DAG.getNode(ISD::FADD, dl,
3479 MVT::f32, LogOfExponent, Log10ofMantissa);
3480 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3481 // For floating-point precision of 12:
3483 // Log10ofMantissa =
3484 // -0.64831180f +
3485 // (0.91751397f +
3486 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3488 // error 0.00019228036, which is better than 12 bits
3489 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3490 getF32Constant(DAG, 0x3d431f31));
3491 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3492 getF32Constant(DAG, 0x3ea21fb2));
3493 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3494 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3495 getF32Constant(DAG, 0x3f6ae232));
3496 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3497 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3498 getF32Constant(DAG, 0x3f25f7c3));
3500 result = DAG.getNode(ISD::FADD, dl,
3501 MVT::f32, LogOfExponent, Log10ofMantissa);
3502 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3503 // For floating-point precision of 18:
3505 // Log10ofMantissa =
3506 // -0.84299375f +
3507 // (1.5327582f +
3508 // (-1.0688956f +
3509 // (0.49102474f +
3510 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3512 // error 0.0000037995730, which is better than 18 bits
3513 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3514 getF32Constant(DAG, 0x3c5d51ce));
3515 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3516 getF32Constant(DAG, 0x3e00685a));
3517 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3518 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3519 getF32Constant(DAG, 0x3efb6798));
3520 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3521 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3522 getF32Constant(DAG, 0x3f88d192));
3523 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3524 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3525 getF32Constant(DAG, 0x3fc4316c));
3526 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3527 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3528 getF32Constant(DAG, 0x3f57ce70));
3530 result = DAG.getNode(ISD::FADD, dl,
3531 MVT::f32, LogOfExponent, Log10ofMantissa);
3533 } else {
3534 // No special expansion.
3535 result = DAG.getNode(ISD::FLOG10, dl,
3536 getValue(I.getOperand(1)).getValueType(),
3537 getValue(I.getOperand(1)));
3540 setValue(&I, result);
3543 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3544 /// limited-precision mode.
3545 void
3546 SelectionDAGLowering::visitExp2(CallInst &I) {
3547 SDValue result;
3548 DebugLoc dl = getCurDebugLoc();
3550 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3551 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3552 SDValue Op = getValue(I.getOperand(1));
3554 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3556 // FractionalPartOfX = x - (float)IntegerPartOfX;
3557 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3558 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3560 // IntegerPartOfX <<= 23;
3561 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3562 DAG.getConstant(23, TLI.getPointerTy()));
3564 if (LimitFloatPrecision <= 6) {
3565 // For floating-point precision of 6:
3567 // TwoToFractionalPartOfX =
3568 // 0.997535578f +
3569 // (0.735607626f + 0.252464424f * x) * x;
3571 // error 0.0144103317, which is 6 bits
3572 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3573 getF32Constant(DAG, 0x3e814304));
3574 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3575 getF32Constant(DAG, 0x3f3c50c8));
3576 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3577 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3578 getF32Constant(DAG, 0x3f7f5e7e));
3579 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3580 SDValue TwoToFractionalPartOfX =
3581 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3583 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3584 MVT::f32, TwoToFractionalPartOfX);
3585 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3586 // For floating-point precision of 12:
3588 // TwoToFractionalPartOfX =
3589 // 0.999892986f +
3590 // (0.696457318f +
3591 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3593 // error 0.000107046256, which is 13 to 14 bits
3594 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3595 getF32Constant(DAG, 0x3da235e3));
3596 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3597 getF32Constant(DAG, 0x3e65b8f3));
3598 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3599 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3600 getF32Constant(DAG, 0x3f324b07));
3601 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3602 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3603 getF32Constant(DAG, 0x3f7ff8fd));
3604 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3605 SDValue TwoToFractionalPartOfX =
3606 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3608 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3609 MVT::f32, TwoToFractionalPartOfX);
3610 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3611 // For floating-point precision of 18:
3613 // TwoToFractionalPartOfX =
3614 // 0.999999982f +
3615 // (0.693148872f +
3616 // (0.240227044f +
3617 // (0.554906021e-1f +
3618 // (0.961591928e-2f +
3619 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3620 // error 2.47208000*10^(-7), which is better than 18 bits
3621 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3622 getF32Constant(DAG, 0x3924b03e));
3623 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3624 getF32Constant(DAG, 0x3ab24b87));
3625 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3626 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3627 getF32Constant(DAG, 0x3c1d8c17));
3628 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3629 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3630 getF32Constant(DAG, 0x3d634a1d));
3631 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3632 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3633 getF32Constant(DAG, 0x3e75fe14));
3634 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3635 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3636 getF32Constant(DAG, 0x3f317234));
3637 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3638 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3639 getF32Constant(DAG, 0x3f800000));
3640 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3641 SDValue TwoToFractionalPartOfX =
3642 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3644 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3645 MVT::f32, TwoToFractionalPartOfX);
3647 } else {
3648 // No special expansion.
3649 result = DAG.getNode(ISD::FEXP2, dl,
3650 getValue(I.getOperand(1)).getValueType(),
3651 getValue(I.getOperand(1)));
3654 setValue(&I, result);
3657 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3658 /// limited-precision mode with x == 10.0f.
3659 void
3660 SelectionDAGLowering::visitPow(CallInst &I) {
3661 SDValue result;
3662 Value *Val = I.getOperand(1);
3663 DebugLoc dl = getCurDebugLoc();
3664 bool IsExp10 = false;
3666 if (getValue(Val).getValueType() == MVT::f32 &&
3667 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3668 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3669 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3670 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3671 APFloat Ten(10.0f);
3672 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3677 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3678 SDValue Op = getValue(I.getOperand(2));
3680 // Put the exponent in the right bit position for later addition to the
3681 // final result:
3683 // #define LOG2OF10 3.3219281f
3684 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3685 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3686 getF32Constant(DAG, 0x40549a78));
3687 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3689 // FractionalPartOfX = x - (float)IntegerPartOfX;
3690 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3691 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3693 // IntegerPartOfX <<= 23;
3694 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3695 DAG.getConstant(23, TLI.getPointerTy()));
3697 if (LimitFloatPrecision <= 6) {
3698 // For floating-point precision of 6:
3700 // twoToFractionalPartOfX =
3701 // 0.997535578f +
3702 // (0.735607626f + 0.252464424f * x) * x;
3704 // error 0.0144103317, which is 6 bits
3705 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3706 getF32Constant(DAG, 0x3e814304));
3707 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3708 getF32Constant(DAG, 0x3f3c50c8));
3709 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3710 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3711 getF32Constant(DAG, 0x3f7f5e7e));
3712 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3713 SDValue TwoToFractionalPartOfX =
3714 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3716 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3717 MVT::f32, TwoToFractionalPartOfX);
3718 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3719 // For floating-point precision of 12:
3721 // TwoToFractionalPartOfX =
3722 // 0.999892986f +
3723 // (0.696457318f +
3724 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3726 // error 0.000107046256, which is 13 to 14 bits
3727 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3728 getF32Constant(DAG, 0x3da235e3));
3729 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3730 getF32Constant(DAG, 0x3e65b8f3));
3731 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3732 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3733 getF32Constant(DAG, 0x3f324b07));
3734 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3735 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3736 getF32Constant(DAG, 0x3f7ff8fd));
3737 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3738 SDValue TwoToFractionalPartOfX =
3739 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3741 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3742 MVT::f32, TwoToFractionalPartOfX);
3743 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3744 // For floating-point precision of 18:
3746 // TwoToFractionalPartOfX =
3747 // 0.999999982f +
3748 // (0.693148872f +
3749 // (0.240227044f +
3750 // (0.554906021e-1f +
3751 // (0.961591928e-2f +
3752 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3753 // error 2.47208000*10^(-7), which is better than 18 bits
3754 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3755 getF32Constant(DAG, 0x3924b03e));
3756 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3757 getF32Constant(DAG, 0x3ab24b87));
3758 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3759 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3760 getF32Constant(DAG, 0x3c1d8c17));
3761 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3762 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3763 getF32Constant(DAG, 0x3d634a1d));
3764 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3765 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3766 getF32Constant(DAG, 0x3e75fe14));
3767 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3768 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3769 getF32Constant(DAG, 0x3f317234));
3770 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3771 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3772 getF32Constant(DAG, 0x3f800000));
3773 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3774 SDValue TwoToFractionalPartOfX =
3775 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3777 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3778 MVT::f32, TwoToFractionalPartOfX);
3780 } else {
3781 // No special expansion.
3782 result = DAG.getNode(ISD::FPOW, dl,
3783 getValue(I.getOperand(1)).getValueType(),
3784 getValue(I.getOperand(1)),
3785 getValue(I.getOperand(2)));
3788 setValue(&I, result);
3791 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3792 /// we want to emit this as a call to a named external function, return the name
3793 /// otherwise lower it and return null.
3794 const char *
3795 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3796 DebugLoc dl = getCurDebugLoc();
3797 switch (Intrinsic) {
3798 default:
3799 // By default, turn this into a target intrinsic node.
3800 visitTargetIntrinsic(I, Intrinsic);
3801 return 0;
3802 case Intrinsic::vastart: visitVAStart(I); return 0;
3803 case Intrinsic::vaend: visitVAEnd(I); return 0;
3804 case Intrinsic::vacopy: visitVACopy(I); return 0;
3805 case Intrinsic::returnaddress:
3806 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3807 getValue(I.getOperand(1))));
3808 return 0;
3809 case Intrinsic::frameaddress:
3810 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3811 getValue(I.getOperand(1))));
3812 return 0;
3813 case Intrinsic::setjmp:
3814 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3815 break;
3816 case Intrinsic::longjmp:
3817 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3818 break;
3819 case Intrinsic::memcpy: {
3820 SDValue Op1 = getValue(I.getOperand(1));
3821 SDValue Op2 = getValue(I.getOperand(2));
3822 SDValue Op3 = getValue(I.getOperand(3));
3823 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3824 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3825 I.getOperand(1), 0, I.getOperand(2), 0));
3826 return 0;
3828 case Intrinsic::memset: {
3829 SDValue Op1 = getValue(I.getOperand(1));
3830 SDValue Op2 = getValue(I.getOperand(2));
3831 SDValue Op3 = getValue(I.getOperand(3));
3832 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3833 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3834 I.getOperand(1), 0));
3835 return 0;
3837 case Intrinsic::memmove: {
3838 SDValue Op1 = getValue(I.getOperand(1));
3839 SDValue Op2 = getValue(I.getOperand(2));
3840 SDValue Op3 = getValue(I.getOperand(3));
3841 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3843 // If the source and destination are known to not be aliases, we can
3844 // lower memmove as memcpy.
3845 uint64_t Size = -1ULL;
3846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3847 Size = C->getZExtValue();
3848 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3849 AliasAnalysis::NoAlias) {
3850 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3851 I.getOperand(1), 0, I.getOperand(2), 0));
3852 return 0;
3855 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3856 I.getOperand(1), 0, I.getOperand(2), 0));
3857 return 0;
3859 case Intrinsic::dbg_stoppoint: {
3860 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3861 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3862 MachineFunction &MF = DAG.getMachineFunction();
3863 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3864 setCurDebugLoc(Loc);
3866 if (OptLevel == CodeGenOpt::None)
3867 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3868 SPI.getLine(),
3869 SPI.getColumn(),
3870 SPI.getContext()));
3872 return 0;
3874 case Intrinsic::dbg_region_start: {
3875 DwarfWriter *DW = DAG.getDwarfWriter();
3876 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3877 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3878 && DW->ShouldEmitDwarfDebug()) {
3879 unsigned LabelID =
3880 DW->RecordRegionStart(RSI.getContext());
3881 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3882 getRoot(), LabelID));
3884 return 0;
3886 case Intrinsic::dbg_region_end: {
3887 DwarfWriter *DW = DAG.getDwarfWriter();
3888 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3890 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3891 || !DW->ShouldEmitDwarfDebug())
3892 return 0;
3894 MachineFunction &MF = DAG.getMachineFunction();
3895 DISubprogram Subprogram(REI.getContext());
3897 if (isInlinedFnEnd(REI, MF.getFunction())) {
3898 // This is end of inlined function. Debugging information for inlined
3899 // function is not handled yet (only supported by FastISel).
3900 if (OptLevel == CodeGenOpt::None) {
3901 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3902 if (ID != 0)
3903 // Returned ID is 0 if this is unbalanced "end of inlined
3904 // scope". This could happen if optimizer eats dbg intrinsics or
3905 // "beginning of inlined scope" is not recoginized due to missing
3906 // location info. In such cases, do ignore this region.end.
3907 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3908 getRoot(), ID));
3910 return 0;
3913 unsigned LabelID =
3914 DW->RecordRegionEnd(REI.getContext());
3915 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3916 getRoot(), LabelID));
3917 return 0;
3919 case Intrinsic::dbg_func_start: {
3920 DwarfWriter *DW = DAG.getDwarfWriter();
3921 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3922 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3923 return 0;
3925 MachineFunction &MF = DAG.getMachineFunction();
3926 // This is a beginning of an inlined function.
3927 if (isInlinedFnStart(FSI, MF.getFunction())) {
3928 if (OptLevel != CodeGenOpt::None)
3929 // FIXME: Debugging informaation for inlined function is only
3930 // supported at CodeGenOpt::Node.
3931 return 0;
3933 DebugLoc PrevLoc = CurDebugLoc;
3934 // If llvm.dbg.func.start is seen in a new block before any
3935 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3936 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3937 if (PrevLoc.isUnknown())
3938 return 0;
3940 // Record the source line.
3941 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3943 if (!DW || !DW->ShouldEmitDwarfDebug())
3944 return 0;
3945 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3946 DISubprogram SP(FSI.getSubprogram());
3947 DICompileUnit CU(PrevLocTpl.CompileUnit);
3948 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3949 PrevLocTpl.Line,
3950 PrevLocTpl.Col);
3951 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3952 getRoot(), LabelID));
3953 return 0;
3956 // This is a beginning of a new function.
3957 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3959 if (!DW || !DW->ShouldEmitDwarfDebug())
3960 return 0;
3961 // llvm.dbg.func_start also defines beginning of function scope.
3962 DW->RecordRegionStart(FSI.getSubprogram());
3963 return 0;
3965 case Intrinsic::dbg_declare: {
3966 if (OptLevel != CodeGenOpt::None)
3967 // FIXME: Variable debug info is not supported here.
3968 return 0;
3969 DwarfWriter *DW = DAG.getDwarfWriter();
3970 if (!DW)
3971 return 0;
3972 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3973 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3974 return 0;
3976 Value *Variable = DI.getVariable();
3977 Value *Address = DI.getAddress();
3978 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3979 Address = BCI->getOperand(0);
3980 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3981 // Don't handle byval struct arguments or VLAs, for example.
3982 if (!AI)
3983 return 0;
3984 int FI = FuncInfo.StaticAllocaMap[AI];
3985 DW->RecordVariable(cast<MDNode>(Variable), FI);
3986 return 0;
3988 case Intrinsic::eh_exception: {
3989 // Insert the EXCEPTIONADDR instruction.
3990 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3991 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3992 SDValue Ops[1];
3993 Ops[0] = DAG.getRoot();
3994 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3995 setValue(&I, Op);
3996 DAG.setRoot(Op.getValue(1));
3997 return 0;
4000 case Intrinsic::eh_selector_i32:
4001 case Intrinsic::eh_selector_i64: {
4002 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4003 EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64);
4005 if (MMI) {
4006 if (CurMBB->isLandingPad())
4007 AddCatchInfo(I, MMI, CurMBB);
4008 else {
4009 #ifndef NDEBUG
4010 FuncInfo.CatchInfoLost.insert(&I);
4011 #endif
4012 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4013 unsigned Reg = TLI.getExceptionSelectorRegister();
4014 if (Reg) CurMBB->addLiveIn(Reg);
4017 // Insert the EHSELECTION instruction.
4018 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4019 SDValue Ops[2];
4020 Ops[0] = getValue(I.getOperand(1));
4021 Ops[1] = getRoot();
4022 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4023 setValue(&I, Op);
4024 DAG.setRoot(Op.getValue(1));
4025 } else {
4026 setValue(&I, DAG.getConstant(0, VT));
4029 return 0;
4032 case Intrinsic::eh_typeid_for_i32:
4033 case Intrinsic::eh_typeid_for_i64: {
4034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4035 EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4036 MVT::i32 : MVT::i64);
4038 if (MMI) {
4039 // Find the type id for the given typeinfo.
4040 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4042 unsigned TypeID = MMI->getTypeIDFor(GV);
4043 setValue(&I, DAG.getConstant(TypeID, VT));
4044 } else {
4045 // Return something different to eh_selector.
4046 setValue(&I, DAG.getConstant(1, VT));
4049 return 0;
4052 case Intrinsic::eh_return_i32:
4053 case Intrinsic::eh_return_i64:
4054 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4055 MMI->setCallsEHReturn(true);
4056 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4057 MVT::Other,
4058 getControlRoot(),
4059 getValue(I.getOperand(1)),
4060 getValue(I.getOperand(2))));
4061 } else {
4062 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4065 return 0;
4066 case Intrinsic::eh_unwind_init:
4067 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4068 MMI->setCallsUnwindInit(true);
4071 return 0;
4073 case Intrinsic::eh_dwarf_cfa: {
4074 EVT VT = getValue(I.getOperand(1)).getValueType();
4075 SDValue CfaArg;
4076 if (VT.bitsGT(TLI.getPointerTy()))
4077 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4078 TLI.getPointerTy(), getValue(I.getOperand(1)));
4079 else
4080 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4081 TLI.getPointerTy(), getValue(I.getOperand(1)));
4083 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4084 TLI.getPointerTy(),
4085 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4086 TLI.getPointerTy()),
4087 CfaArg);
4088 setValue(&I, DAG.getNode(ISD::ADD, dl,
4089 TLI.getPointerTy(),
4090 DAG.getNode(ISD::FRAMEADDR, dl,
4091 TLI.getPointerTy(),
4092 DAG.getConstant(0,
4093 TLI.getPointerTy())),
4094 Offset));
4095 return 0;
4097 case Intrinsic::convertff:
4098 case Intrinsic::convertfsi:
4099 case Intrinsic::convertfui:
4100 case Intrinsic::convertsif:
4101 case Intrinsic::convertuif:
4102 case Intrinsic::convertss:
4103 case Intrinsic::convertsu:
4104 case Intrinsic::convertus:
4105 case Intrinsic::convertuu: {
4106 ISD::CvtCode Code = ISD::CVT_INVALID;
4107 switch (Intrinsic) {
4108 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4109 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4110 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4111 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4112 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4113 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4114 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4115 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4116 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4118 EVT DestVT = TLI.getValueType(I.getType());
4119 Value* Op1 = I.getOperand(1);
4120 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4121 DAG.getValueType(DestVT),
4122 DAG.getValueType(getValue(Op1).getValueType()),
4123 getValue(I.getOperand(2)),
4124 getValue(I.getOperand(3)),
4125 Code));
4126 return 0;
4129 case Intrinsic::sqrt:
4130 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4131 getValue(I.getOperand(1)).getValueType(),
4132 getValue(I.getOperand(1))));
4133 return 0;
4134 case Intrinsic::powi:
4135 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4136 getValue(I.getOperand(1)).getValueType(),
4137 getValue(I.getOperand(1)),
4138 getValue(I.getOperand(2))));
4139 return 0;
4140 case Intrinsic::sin:
4141 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4142 getValue(I.getOperand(1)).getValueType(),
4143 getValue(I.getOperand(1))));
4144 return 0;
4145 case Intrinsic::cos:
4146 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4147 getValue(I.getOperand(1)).getValueType(),
4148 getValue(I.getOperand(1))));
4149 return 0;
4150 case Intrinsic::log:
4151 visitLog(I);
4152 return 0;
4153 case Intrinsic::log2:
4154 visitLog2(I);
4155 return 0;
4156 case Intrinsic::log10:
4157 visitLog10(I);
4158 return 0;
4159 case Intrinsic::exp:
4160 visitExp(I);
4161 return 0;
4162 case Intrinsic::exp2:
4163 visitExp2(I);
4164 return 0;
4165 case Intrinsic::pow:
4166 visitPow(I);
4167 return 0;
4168 case Intrinsic::pcmarker: {
4169 SDValue Tmp = getValue(I.getOperand(1));
4170 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4171 return 0;
4173 case Intrinsic::readcyclecounter: {
4174 SDValue Op = getRoot();
4175 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4176 DAG.getVTList(MVT::i64, MVT::Other),
4177 &Op, 1);
4178 setValue(&I, Tmp);
4179 DAG.setRoot(Tmp.getValue(1));
4180 return 0;
4182 case Intrinsic::bswap:
4183 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4184 getValue(I.getOperand(1)).getValueType(),
4185 getValue(I.getOperand(1))));
4186 return 0;
4187 case Intrinsic::cttz: {
4188 SDValue Arg = getValue(I.getOperand(1));
4189 EVT Ty = Arg.getValueType();
4190 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4191 setValue(&I, result);
4192 return 0;
4194 case Intrinsic::ctlz: {
4195 SDValue Arg = getValue(I.getOperand(1));
4196 EVT Ty = Arg.getValueType();
4197 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4198 setValue(&I, result);
4199 return 0;
4201 case Intrinsic::ctpop: {
4202 SDValue Arg = getValue(I.getOperand(1));
4203 EVT Ty = Arg.getValueType();
4204 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4205 setValue(&I, result);
4206 return 0;
4208 case Intrinsic::stacksave: {
4209 SDValue Op = getRoot();
4210 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4211 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4212 setValue(&I, Tmp);
4213 DAG.setRoot(Tmp.getValue(1));
4214 return 0;
4216 case Intrinsic::stackrestore: {
4217 SDValue Tmp = getValue(I.getOperand(1));
4218 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4219 return 0;
4221 case Intrinsic::stackprotector: {
4222 // Emit code into the DAG to store the stack guard onto the stack.
4223 MachineFunction &MF = DAG.getMachineFunction();
4224 MachineFrameInfo *MFI = MF.getFrameInfo();
4225 EVT PtrTy = TLI.getPointerTy();
4227 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4228 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4230 int FI = FuncInfo.StaticAllocaMap[Slot];
4231 MFI->setStackProtectorIndex(FI);
4233 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4235 // Store the stack protector onto the stack.
4236 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4237 PseudoSourceValue::getFixedStack(FI),
4238 0, true);
4239 setValue(&I, Result);
4240 DAG.setRoot(Result);
4241 return 0;
4243 case Intrinsic::var_annotation:
4244 // Discard annotate attributes
4245 return 0;
4247 case Intrinsic::init_trampoline: {
4248 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4250 SDValue Ops[6];
4251 Ops[0] = getRoot();
4252 Ops[1] = getValue(I.getOperand(1));
4253 Ops[2] = getValue(I.getOperand(2));
4254 Ops[3] = getValue(I.getOperand(3));
4255 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4256 Ops[5] = DAG.getSrcValue(F);
4258 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4259 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4260 Ops, 6);
4262 setValue(&I, Tmp);
4263 DAG.setRoot(Tmp.getValue(1));
4264 return 0;
4267 case Intrinsic::gcroot:
4268 if (GFI) {
4269 Value *Alloca = I.getOperand(1);
4270 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4272 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4273 GFI->addStackRoot(FI->getIndex(), TypeMap);
4275 return 0;
4277 case Intrinsic::gcread:
4278 case Intrinsic::gcwrite:
4279 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4280 return 0;
4282 case Intrinsic::flt_rounds: {
4283 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4284 return 0;
4287 case Intrinsic::trap: {
4288 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4289 return 0;
4292 case Intrinsic::uadd_with_overflow:
4293 return implVisitAluOverflow(I, ISD::UADDO);
4294 case Intrinsic::sadd_with_overflow:
4295 return implVisitAluOverflow(I, ISD::SADDO);
4296 case Intrinsic::usub_with_overflow:
4297 return implVisitAluOverflow(I, ISD::USUBO);
4298 case Intrinsic::ssub_with_overflow:
4299 return implVisitAluOverflow(I, ISD::SSUBO);
4300 case Intrinsic::umul_with_overflow:
4301 return implVisitAluOverflow(I, ISD::UMULO);
4302 case Intrinsic::smul_with_overflow:
4303 return implVisitAluOverflow(I, ISD::SMULO);
4305 case Intrinsic::prefetch: {
4306 SDValue Ops[4];
4307 Ops[0] = getRoot();
4308 Ops[1] = getValue(I.getOperand(1));
4309 Ops[2] = getValue(I.getOperand(2));
4310 Ops[3] = getValue(I.getOperand(3));
4311 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4312 return 0;
4315 case Intrinsic::memory_barrier: {
4316 SDValue Ops[6];
4317 Ops[0] = getRoot();
4318 for (int x = 1; x < 6; ++x)
4319 Ops[x] = getValue(I.getOperand(x));
4321 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4322 return 0;
4324 case Intrinsic::atomic_cmp_swap: {
4325 SDValue Root = getRoot();
4326 SDValue L =
4327 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4328 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4329 Root,
4330 getValue(I.getOperand(1)),
4331 getValue(I.getOperand(2)),
4332 getValue(I.getOperand(3)),
4333 I.getOperand(1));
4334 setValue(&I, L);
4335 DAG.setRoot(L.getValue(1));
4336 return 0;
4338 case Intrinsic::atomic_load_add:
4339 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4340 case Intrinsic::atomic_load_sub:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4342 case Intrinsic::atomic_load_or:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4344 case Intrinsic::atomic_load_xor:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4346 case Intrinsic::atomic_load_and:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4348 case Intrinsic::atomic_load_nand:
4349 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4350 case Intrinsic::atomic_load_max:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4352 case Intrinsic::atomic_load_min:
4353 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4354 case Intrinsic::atomic_load_umin:
4355 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4356 case Intrinsic::atomic_load_umax:
4357 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4358 case Intrinsic::atomic_swap:
4359 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4363 /// Test if the given instruction is in a position to be optimized
4364 /// with a tail-call. This roughly means that it's in a block with
4365 /// a return and there's nothing that needs to be scheduled
4366 /// between it and the return.
4368 /// This function only tests target-independent requirements.
4369 /// For target-dependent requirements, a target should override
4370 /// TargetLowering::IsEligibleForTailCallOptimization.
4372 static bool
4373 isInTailCallPosition(const Instruction *I, Attributes RetAttr,
4374 const TargetLowering &TLI) {
4375 const BasicBlock *ExitBB = I->getParent();
4376 const TerminatorInst *Term = ExitBB->getTerminator();
4377 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4378 const Function *F = ExitBB->getParent();
4380 // The block must end in a return statement or an unreachable.
4381 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4383 // If I will have a chain, make sure no other instruction that will have a
4384 // chain interposes between I and the return.
4385 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4386 !I->isSafeToSpeculativelyExecute())
4387 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4388 --BBI) {
4389 if (&*BBI == I)
4390 break;
4391 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4392 !BBI->isSafeToSpeculativelyExecute())
4393 return false;
4396 // If the block ends with a void return or unreachable, it doesn't matter
4397 // what the call's return type is.
4398 if (!Ret || Ret->getNumOperands() == 0) return true;
4400 // Conservatively require the attributes of the call to match those of
4401 // the return.
4402 if (F->getAttributes().getRetAttributes() != RetAttr)
4403 return false;
4405 // Otherwise, make sure the unmodified return value of I is the return value.
4406 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4407 U = dyn_cast<Instruction>(U->getOperand(0))) {
4408 if (!U)
4409 return false;
4410 if (!U->hasOneUse())
4411 return false;
4412 if (U == I)
4413 break;
4414 // Check for a truly no-op truncate.
4415 if (isa<TruncInst>(U) &&
4416 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4417 continue;
4418 // Check for a truly no-op bitcast.
4419 if (isa<BitCastInst>(U) &&
4420 (U->getOperand(0)->getType() == U->getType() ||
4421 (isa<PointerType>(U->getOperand(0)->getType()) &&
4422 isa<PointerType>(U->getType()))))
4423 continue;
4424 // Otherwise it's not a true no-op.
4425 return false;
4428 return true;
4431 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4432 bool isTailCall,
4433 MachineBasicBlock *LandingPad) {
4434 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4435 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4436 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4437 unsigned BeginLabel = 0, EndLabel = 0;
4439 TargetLowering::ArgListTy Args;
4440 TargetLowering::ArgListEntry Entry;
4441 Args.reserve(CS.arg_size());
4442 unsigned j = 1;
4443 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4444 i != e; ++i, ++j) {
4445 SDValue ArgNode = getValue(*i);
4446 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4448 unsigned attrInd = i - CS.arg_begin() + 1;
4449 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4450 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4451 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4452 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4453 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4454 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4455 Entry.Alignment = CS.getParamAlignment(attrInd);
4456 Args.push_back(Entry);
4459 if (LandingPad && MMI) {
4460 // Insert a label before the invoke call to mark the try range. This can be
4461 // used to detect deletion of the invoke via the MachineModuleInfo.
4462 BeginLabel = MMI->NextLabelID();
4464 // Both PendingLoads and PendingExports must be flushed here;
4465 // this call might not return.
4466 (void)getRoot();
4467 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4468 getControlRoot(), BeginLabel));
4471 // Check if target-independent constraints permit a tail call here.
4472 // Target-dependent constraints are checked within TLI.LowerCallTo.
4473 if (isTailCall &&
4474 !isInTailCallPosition(CS.getInstruction(),
4475 CS.getAttributes().getRetAttributes(),
4476 TLI))
4477 isTailCall = false;
4479 std::pair<SDValue,SDValue> Result =
4480 TLI.LowerCallTo(getRoot(), CS.getType(),
4481 CS.paramHasAttr(0, Attribute::SExt),
4482 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4483 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4484 CS.getCallingConv(),
4485 isTailCall,
4486 !CS.getInstruction()->use_empty(),
4487 Callee, Args, DAG, getCurDebugLoc());
4488 assert((isTailCall || Result.second.getNode()) &&
4489 "Non-null chain expected with non-tail call!");
4490 assert((Result.second.getNode() || !Result.first.getNode()) &&
4491 "Null value expected with tail call!");
4492 if (Result.first.getNode())
4493 setValue(CS.getInstruction(), Result.first);
4494 // As a special case, a null chain means that a tail call has
4495 // been emitted and the DAG root is already updated.
4496 if (Result.second.getNode())
4497 DAG.setRoot(Result.second);
4498 else
4499 HasTailCall = true;
4501 if (LandingPad && MMI) {
4502 // Insert a label at the end of the invoke call to mark the try range. This
4503 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4504 EndLabel = MMI->NextLabelID();
4505 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4506 getRoot(), EndLabel));
4508 // Inform MachineModuleInfo of range.
4509 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4514 void SelectionDAGLowering::visitCall(CallInst &I) {
4515 const char *RenameFn = 0;
4516 if (Function *F = I.getCalledFunction()) {
4517 if (F->isDeclaration()) {
4518 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4519 if (II) {
4520 if (unsigned IID = II->getIntrinsicID(F)) {
4521 RenameFn = visitIntrinsicCall(I, IID);
4522 if (!RenameFn)
4523 return;
4526 if (unsigned IID = F->getIntrinsicID()) {
4527 RenameFn = visitIntrinsicCall(I, IID);
4528 if (!RenameFn)
4529 return;
4533 // Check for well-known libc/libm calls. If the function is internal, it
4534 // can't be a library call.
4535 if (!F->hasLocalLinkage() && F->hasName()) {
4536 StringRef Name = F->getName();
4537 if (Name == "copysign" || Name == "copysignf") {
4538 if (I.getNumOperands() == 3 && // Basic sanity checks.
4539 I.getOperand(1)->getType()->isFloatingPoint() &&
4540 I.getType() == I.getOperand(1)->getType() &&
4541 I.getType() == I.getOperand(2)->getType()) {
4542 SDValue LHS = getValue(I.getOperand(1));
4543 SDValue RHS = getValue(I.getOperand(2));
4544 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4545 LHS.getValueType(), LHS, RHS));
4546 return;
4548 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4549 if (I.getNumOperands() == 2 && // Basic sanity checks.
4550 I.getOperand(1)->getType()->isFloatingPoint() &&
4551 I.getType() == I.getOperand(1)->getType()) {
4552 SDValue Tmp = getValue(I.getOperand(1));
4553 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4554 Tmp.getValueType(), Tmp));
4555 return;
4557 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4558 if (I.getNumOperands() == 2 && // Basic sanity checks.
4559 I.getOperand(1)->getType()->isFloatingPoint() &&
4560 I.getType() == I.getOperand(1)->getType()) {
4561 SDValue Tmp = getValue(I.getOperand(1));
4562 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4563 Tmp.getValueType(), Tmp));
4564 return;
4566 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4567 if (I.getNumOperands() == 2 && // Basic sanity checks.
4568 I.getOperand(1)->getType()->isFloatingPoint() &&
4569 I.getType() == I.getOperand(1)->getType()) {
4570 SDValue Tmp = getValue(I.getOperand(1));
4571 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4572 Tmp.getValueType(), Tmp));
4573 return;
4577 } else if (isa<InlineAsm>(I.getOperand(0))) {
4578 visitInlineAsm(&I);
4579 return;
4582 SDValue Callee;
4583 if (!RenameFn)
4584 Callee = getValue(I.getOperand(0));
4585 else
4586 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4588 // Check if we can potentially perform a tail call. More detailed
4589 // checking is be done within LowerCallTo, after more information
4590 // about the call is known.
4591 bool isTailCall = PerformTailCallOpt && I.isTailCall();
4593 LowerCallTo(&I, Callee, isTailCall);
4597 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4598 /// this value and returns the result as a ValueVT value. This uses
4599 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4600 /// If the Flag pointer is NULL, no flag is used.
4601 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4602 SDValue &Chain,
4603 SDValue *Flag) const {
4604 // Assemble the legal parts into the final values.
4605 SmallVector<SDValue, 4> Values(ValueVTs.size());
4606 SmallVector<SDValue, 8> Parts;
4607 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4608 // Copy the legal parts from the registers.
4609 EVT ValueVT = ValueVTs[Value];
4610 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4611 EVT RegisterVT = RegVTs[Value];
4613 Parts.resize(NumRegs);
4614 for (unsigned i = 0; i != NumRegs; ++i) {
4615 SDValue P;
4616 if (Flag == 0)
4617 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4618 else {
4619 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4620 *Flag = P.getValue(2);
4622 Chain = P.getValue(1);
4624 // If the source register was virtual and if we know something about it,
4625 // add an assert node.
4626 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4627 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4628 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4629 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4630 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4631 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4633 unsigned RegSize = RegisterVT.getSizeInBits();
4634 unsigned NumSignBits = LOI.NumSignBits;
4635 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4637 // FIXME: We capture more information than the dag can represent. For
4638 // now, just use the tightest assertzext/assertsext possible.
4639 bool isSExt = true;
4640 EVT FromVT(MVT::Other);
4641 if (NumSignBits == RegSize)
4642 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4643 else if (NumZeroBits >= RegSize-1)
4644 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4645 else if (NumSignBits > RegSize-8)
4646 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4647 else if (NumZeroBits >= RegSize-8)
4648 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4649 else if (NumSignBits > RegSize-16)
4650 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4651 else if (NumZeroBits >= RegSize-16)
4652 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4653 else if (NumSignBits > RegSize-32)
4654 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4655 else if (NumZeroBits >= RegSize-32)
4656 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4658 if (FromVT != MVT::Other) {
4659 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4660 RegisterVT, P, DAG.getValueType(FromVT));
4666 Parts[i] = P;
4669 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4670 NumRegs, RegisterVT, ValueVT);
4671 Part += NumRegs;
4672 Parts.clear();
4675 return DAG.getNode(ISD::MERGE_VALUES, dl,
4676 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4677 &Values[0], ValueVTs.size());
4680 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4681 /// specified value into the registers specified by this object. This uses
4682 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4683 /// If the Flag pointer is NULL, no flag is used.
4684 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4685 SDValue &Chain, SDValue *Flag) const {
4686 // Get the list of the values's legal parts.
4687 unsigned NumRegs = Regs.size();
4688 SmallVector<SDValue, 8> Parts(NumRegs);
4689 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4690 EVT ValueVT = ValueVTs[Value];
4691 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4692 EVT RegisterVT = RegVTs[Value];
4694 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4695 &Parts[Part], NumParts, RegisterVT);
4696 Part += NumParts;
4699 // Copy the parts into the registers.
4700 SmallVector<SDValue, 8> Chains(NumRegs);
4701 for (unsigned i = 0; i != NumRegs; ++i) {
4702 SDValue Part;
4703 if (Flag == 0)
4704 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4705 else {
4706 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4707 *Flag = Part.getValue(1);
4709 Chains[i] = Part.getValue(0);
4712 if (NumRegs == 1 || Flag)
4713 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4714 // flagged to it. That is the CopyToReg nodes and the user are considered
4715 // a single scheduling unit. If we create a TokenFactor and return it as
4716 // chain, then the TokenFactor is both a predecessor (operand) of the
4717 // user as well as a successor (the TF operands are flagged to the user).
4718 // c1, f1 = CopyToReg
4719 // c2, f2 = CopyToReg
4720 // c3 = TokenFactor c1, c2
4721 // ...
4722 // = op c3, ..., f2
4723 Chain = Chains[NumRegs-1];
4724 else
4725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4728 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4729 /// operand list. This adds the code marker and includes the number of
4730 /// values added into it.
4731 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4732 bool HasMatching,unsigned MatchingIdx,
4733 SelectionDAG &DAG,
4734 std::vector<SDValue> &Ops) const {
4735 EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4736 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4737 unsigned Flag = Code | (Regs.size() << 3);
4738 if (HasMatching)
4739 Flag |= 0x80000000 | (MatchingIdx << 16);
4740 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4741 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4742 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4743 EVT RegisterVT = RegVTs[Value];
4744 for (unsigned i = 0; i != NumRegs; ++i) {
4745 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4746 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4751 /// isAllocatableRegister - If the specified register is safe to allocate,
4752 /// i.e. it isn't a stack pointer or some other special register, return the
4753 /// register class for the register. Otherwise, return null.
4754 static const TargetRegisterClass *
4755 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4756 const TargetLowering &TLI,
4757 const TargetRegisterInfo *TRI) {
4758 EVT FoundVT = MVT::Other;
4759 const TargetRegisterClass *FoundRC = 0;
4760 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4761 E = TRI->regclass_end(); RCI != E; ++RCI) {
4762 EVT ThisVT = MVT::Other;
4764 const TargetRegisterClass *RC = *RCI;
4765 // If none of the the value types for this register class are valid, we
4766 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4767 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4768 I != E; ++I) {
4769 if (TLI.isTypeLegal(*I)) {
4770 // If we have already found this register in a different register class,
4771 // choose the one with the largest VT specified. For example, on
4772 // PowerPC, we favor f64 register classes over f32.
4773 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4774 ThisVT = *I;
4775 break;
4780 if (ThisVT == MVT::Other) continue;
4782 // NOTE: This isn't ideal. In particular, this might allocate the
4783 // frame pointer in functions that need it (due to them not being taken
4784 // out of allocation, because a variable sized allocation hasn't been seen
4785 // yet). This is a slight code pessimization, but should still work.
4786 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4787 E = RC->allocation_order_end(MF); I != E; ++I)
4788 if (*I == Reg) {
4789 // We found a matching register class. Keep looking at others in case
4790 // we find one with larger registers that this physreg is also in.
4791 FoundRC = RC;
4792 FoundVT = ThisVT;
4793 break;
4796 return FoundRC;
4800 namespace llvm {
4801 /// AsmOperandInfo - This contains information for each constraint that we are
4802 /// lowering.
4803 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4804 public TargetLowering::AsmOperandInfo {
4805 public:
4806 /// CallOperand - If this is the result output operand or a clobber
4807 /// this is null, otherwise it is the incoming operand to the CallInst.
4808 /// This gets modified as the asm is processed.
4809 SDValue CallOperand;
4811 /// AssignedRegs - If this is a register or register class operand, this
4812 /// contains the set of register corresponding to the operand.
4813 RegsForValue AssignedRegs;
4815 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4816 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4819 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4820 /// busy in OutputRegs/InputRegs.
4821 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4822 std::set<unsigned> &OutputRegs,
4823 std::set<unsigned> &InputRegs,
4824 const TargetRegisterInfo &TRI) const {
4825 if (isOutReg) {
4826 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4827 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4829 if (isInReg) {
4830 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4831 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4835 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4836 /// corresponds to. If there is no Value* for this operand, it returns
4837 /// MVT::Other.
4838 EVT getCallOperandValEVT(LLVMContext &Context,
4839 const TargetLowering &TLI,
4840 const TargetData *TD) const {
4841 if (CallOperandVal == 0) return MVT::Other;
4843 if (isa<BasicBlock>(CallOperandVal))
4844 return TLI.getPointerTy();
4846 const llvm::Type *OpTy = CallOperandVal->getType();
4848 // If this is an indirect operand, the operand is a pointer to the
4849 // accessed type.
4850 if (isIndirect)
4851 OpTy = cast<PointerType>(OpTy)->getElementType();
4853 // If OpTy is not a single value, it may be a struct/union that we
4854 // can tile with integers.
4855 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4856 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4857 switch (BitSize) {
4858 default: break;
4859 case 1:
4860 case 8:
4861 case 16:
4862 case 32:
4863 case 64:
4864 case 128:
4865 OpTy = IntegerType::get(Context, BitSize);
4866 break;
4870 return TLI.getValueType(OpTy, true);
4873 private:
4874 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4875 /// specified set.
4876 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4877 const TargetRegisterInfo &TRI) {
4878 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4879 Regs.insert(Reg);
4880 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4881 for (; *Aliases; ++Aliases)
4882 Regs.insert(*Aliases);
4885 } // end llvm namespace.
4888 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4889 /// specified operand. We prefer to assign virtual registers, to allow the
4890 /// register allocator handle the assignment process. However, if the asm uses
4891 /// features that we can't model on machineinstrs, we have SDISel do the
4892 /// allocation. This produces generally horrible, but correct, code.
4894 /// OpInfo describes the operand.
4895 /// Input and OutputRegs are the set of already allocated physical registers.
4897 void SelectionDAGLowering::
4898 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4899 std::set<unsigned> &OutputRegs,
4900 std::set<unsigned> &InputRegs) {
4901 LLVMContext &Context = FuncInfo.Fn->getContext();
4903 // Compute whether this value requires an input register, an output register,
4904 // or both.
4905 bool isOutReg = false;
4906 bool isInReg = false;
4907 switch (OpInfo.Type) {
4908 case InlineAsm::isOutput:
4909 isOutReg = true;
4911 // If there is an input constraint that matches this, we need to reserve
4912 // the input register so no other inputs allocate to it.
4913 isInReg = OpInfo.hasMatchingInput();
4914 break;
4915 case InlineAsm::isInput:
4916 isInReg = true;
4917 isOutReg = false;
4918 break;
4919 case InlineAsm::isClobber:
4920 isOutReg = true;
4921 isInReg = true;
4922 break;
4926 MachineFunction &MF = DAG.getMachineFunction();
4927 SmallVector<unsigned, 4> Regs;
4929 // If this is a constraint for a single physreg, or a constraint for a
4930 // register class, find it.
4931 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4932 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4933 OpInfo.ConstraintVT);
4935 unsigned NumRegs = 1;
4936 if (OpInfo.ConstraintVT != MVT::Other) {
4937 // If this is a FP input in an integer register (or visa versa) insert a bit
4938 // cast of the input value. More generally, handle any case where the input
4939 // value disagrees with the register class we plan to stick this in.
4940 if (OpInfo.Type == InlineAsm::isInput &&
4941 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4942 // Try to convert to the first EVT that the reg class contains. If the
4943 // types are identical size, use a bitcast to convert (e.g. two differing
4944 // vector types).
4945 EVT RegVT = *PhysReg.second->vt_begin();
4946 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4947 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4948 RegVT, OpInfo.CallOperand);
4949 OpInfo.ConstraintVT = RegVT;
4950 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4951 // If the input is a FP value and we want it in FP registers, do a
4952 // bitcast to the corresponding integer type. This turns an f64 value
4953 // into i64, which can be passed with two i32 values on a 32-bit
4954 // machine.
4955 RegVT = EVT::getIntegerVT(Context,
4956 OpInfo.ConstraintVT.getSizeInBits());
4957 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4958 RegVT, OpInfo.CallOperand);
4959 OpInfo.ConstraintVT = RegVT;
4963 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
4966 EVT RegVT;
4967 EVT ValueVT = OpInfo.ConstraintVT;
4969 // If this is a constraint for a specific physical register, like {r17},
4970 // assign it now.
4971 if (unsigned AssignedReg = PhysReg.first) {
4972 const TargetRegisterClass *RC = PhysReg.second;
4973 if (OpInfo.ConstraintVT == MVT::Other)
4974 ValueVT = *RC->vt_begin();
4976 // Get the actual register value type. This is important, because the user
4977 // may have asked for (e.g.) the AX register in i32 type. We need to
4978 // remember that AX is actually i16 to get the right extension.
4979 RegVT = *RC->vt_begin();
4981 // This is a explicit reference to a physical register.
4982 Regs.push_back(AssignedReg);
4984 // If this is an expanded reference, add the rest of the regs to Regs.
4985 if (NumRegs != 1) {
4986 TargetRegisterClass::iterator I = RC->begin();
4987 for (; *I != AssignedReg; ++I)
4988 assert(I != RC->end() && "Didn't find reg!");
4990 // Already added the first reg.
4991 --NumRegs; ++I;
4992 for (; NumRegs; --NumRegs, ++I) {
4993 assert(I != RC->end() && "Ran out of registers to allocate!");
4994 Regs.push_back(*I);
4997 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4998 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4999 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5000 return;
5003 // Otherwise, if this was a reference to an LLVM register class, create vregs
5004 // for this reference.
5005 if (const TargetRegisterClass *RC = PhysReg.second) {
5006 RegVT = *RC->vt_begin();
5007 if (OpInfo.ConstraintVT == MVT::Other)
5008 ValueVT = RegVT;
5010 // Create the appropriate number of virtual registers.
5011 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5012 for (; NumRegs; --NumRegs)
5013 Regs.push_back(RegInfo.createVirtualRegister(RC));
5015 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5016 return;
5019 // This is a reference to a register class that doesn't directly correspond
5020 // to an LLVM register class. Allocate NumRegs consecutive, available,
5021 // registers from the class.
5022 std::vector<unsigned> RegClassRegs
5023 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5024 OpInfo.ConstraintVT);
5026 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5027 unsigned NumAllocated = 0;
5028 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5029 unsigned Reg = RegClassRegs[i];
5030 // See if this register is available.
5031 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5032 (isInReg && InputRegs.count(Reg))) { // Already used.
5033 // Make sure we find consecutive registers.
5034 NumAllocated = 0;
5035 continue;
5038 // Check to see if this register is allocatable (i.e. don't give out the
5039 // stack pointer).
5040 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5041 if (!RC) { // Couldn't allocate this register.
5042 // Reset NumAllocated to make sure we return consecutive registers.
5043 NumAllocated = 0;
5044 continue;
5047 // Okay, this register is good, we can use it.
5048 ++NumAllocated;
5050 // If we allocated enough consecutive registers, succeed.
5051 if (NumAllocated == NumRegs) {
5052 unsigned RegStart = (i-NumAllocated)+1;
5053 unsigned RegEnd = i+1;
5054 // Mark all of the allocated registers used.
5055 for (unsigned i = RegStart; i != RegEnd; ++i)
5056 Regs.push_back(RegClassRegs[i]);
5058 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5059 OpInfo.ConstraintVT);
5060 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5061 return;
5065 // Otherwise, we couldn't allocate enough registers for this.
5068 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5069 /// processed uses a memory 'm' constraint.
5070 static bool
5071 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5072 const TargetLowering &TLI) {
5073 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5074 InlineAsm::ConstraintInfo &CI = CInfos[i];
5075 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5076 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5077 if (CType == TargetLowering::C_Memory)
5078 return true;
5081 // Indirect operand accesses access memory.
5082 if (CI.isIndirect)
5083 return true;
5086 return false;
5089 /// visitInlineAsm - Handle a call to an InlineAsm object.
5091 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5092 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5094 /// ConstraintOperands - Information about all of the constraints.
5095 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5097 std::set<unsigned> OutputRegs, InputRegs;
5099 // Do a prepass over the constraints, canonicalizing them, and building up the
5100 // ConstraintOperands list.
5101 std::vector<InlineAsm::ConstraintInfo>
5102 ConstraintInfos = IA->ParseConstraints();
5104 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5106 SDValue Chain, Flag;
5108 // We won't need to flush pending loads if this asm doesn't touch
5109 // memory and is nonvolatile.
5110 if (hasMemory || IA->hasSideEffects())
5111 Chain = getRoot();
5112 else
5113 Chain = DAG.getRoot();
5115 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5116 unsigned ResNo = 0; // ResNo - The result number of the next output.
5117 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5118 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5119 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5121 EVT OpVT = MVT::Other;
5123 // Compute the value type for each operand.
5124 switch (OpInfo.Type) {
5125 case InlineAsm::isOutput:
5126 // Indirect outputs just consume an argument.
5127 if (OpInfo.isIndirect) {
5128 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5129 break;
5132 // The return value of the call is this value. As such, there is no
5133 // corresponding argument.
5134 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5135 "Bad inline asm!");
5136 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5137 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5138 } else {
5139 assert(ResNo == 0 && "Asm only has one result!");
5140 OpVT = TLI.getValueType(CS.getType());
5142 ++ResNo;
5143 break;
5144 case InlineAsm::isInput:
5145 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5146 break;
5147 case InlineAsm::isClobber:
5148 // Nothing to do.
5149 break;
5152 // If this is an input or an indirect output, process the call argument.
5153 // BasicBlocks are labels, currently appearing only in asm's.
5154 if (OpInfo.CallOperandVal) {
5155 // Strip bitcasts, if any. This mostly comes up for functions.
5156 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5158 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5159 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5160 } else {
5161 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5164 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5167 OpInfo.ConstraintVT = OpVT;
5170 // Second pass over the constraints: compute which constraint option to use
5171 // and assign registers to constraints that want a specific physreg.
5172 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5173 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5175 // If this is an output operand with a matching input operand, look up the
5176 // matching input. If their types mismatch, e.g. one is an integer, the
5177 // other is floating point, or their sizes are different, flag it as an
5178 // error.
5179 if (OpInfo.hasMatchingInput()) {
5180 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5181 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5182 if ((OpInfo.ConstraintVT.isInteger() !=
5183 Input.ConstraintVT.isInteger()) ||
5184 (OpInfo.ConstraintVT.getSizeInBits() !=
5185 Input.ConstraintVT.getSizeInBits())) {
5186 llvm_report_error("Unsupported asm: input constraint"
5187 " with a matching output constraint of incompatible"
5188 " type!");
5190 Input.ConstraintVT = OpInfo.ConstraintVT;
5194 // Compute the constraint code and ConstraintType to use.
5195 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5197 // If this is a memory input, and if the operand is not indirect, do what we
5198 // need to to provide an address for the memory input.
5199 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5200 !OpInfo.isIndirect) {
5201 assert(OpInfo.Type == InlineAsm::isInput &&
5202 "Can only indirectify direct input operands!");
5204 // Memory operands really want the address of the value. If we don't have
5205 // an indirect input, put it in the constpool if we can, otherwise spill
5206 // it to a stack slot.
5208 // If the operand is a float, integer, or vector constant, spill to a
5209 // constant pool entry to get its address.
5210 Value *OpVal = OpInfo.CallOperandVal;
5211 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5212 isa<ConstantVector>(OpVal)) {
5213 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5214 TLI.getPointerTy());
5215 } else {
5216 // Otherwise, create a stack slot and emit a store to it before the
5217 // asm.
5218 const Type *Ty = OpVal->getType();
5219 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5220 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5221 MachineFunction &MF = DAG.getMachineFunction();
5222 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5223 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5224 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5225 OpInfo.CallOperand, StackSlot, NULL, 0);
5226 OpInfo.CallOperand = StackSlot;
5229 // There is no longer a Value* corresponding to this operand.
5230 OpInfo.CallOperandVal = 0;
5231 // It is now an indirect operand.
5232 OpInfo.isIndirect = true;
5235 // If this constraint is for a specific register, allocate it before
5236 // anything else.
5237 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5238 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5240 ConstraintInfos.clear();
5243 // Second pass - Loop over all of the operands, assigning virtual or physregs
5244 // to register class operands.
5245 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5246 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5248 // C_Register operands have already been allocated, Other/Memory don't need
5249 // to be.
5250 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5251 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5254 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5255 std::vector<SDValue> AsmNodeOperands;
5256 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5257 AsmNodeOperands.push_back(
5258 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5261 // Loop over all of the inputs, copying the operand values into the
5262 // appropriate registers and processing the output regs.
5263 RegsForValue RetValRegs;
5265 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5266 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5268 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5269 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5271 switch (OpInfo.Type) {
5272 case InlineAsm::isOutput: {
5273 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5274 OpInfo.ConstraintType != TargetLowering::C_Register) {
5275 // Memory output, or 'other' output (e.g. 'X' constraint).
5276 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5278 // Add information to the INLINEASM node to know about this output.
5279 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5280 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5281 TLI.getPointerTy()));
5282 AsmNodeOperands.push_back(OpInfo.CallOperand);
5283 break;
5286 // Otherwise, this is a register or register class output.
5288 // Copy the output from the appropriate register. Find a register that
5289 // we can use.
5290 if (OpInfo.AssignedRegs.Regs.empty()) {
5291 llvm_report_error("Couldn't allocate output reg for"
5292 " constraint '" + OpInfo.ConstraintCode + "'!");
5295 // If this is an indirect operand, store through the pointer after the
5296 // asm.
5297 if (OpInfo.isIndirect) {
5298 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5299 OpInfo.CallOperandVal));
5300 } else {
5301 // This is the result value of the call.
5302 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5303 "Bad inline asm!");
5304 // Concatenate this output onto the outputs list.
5305 RetValRegs.append(OpInfo.AssignedRegs);
5308 // Add information to the INLINEASM node to know that this register is
5309 // set.
5310 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5311 6 /* EARLYCLOBBER REGDEF */ :
5312 2 /* REGDEF */ ,
5313 false,
5315 DAG, AsmNodeOperands);
5316 break;
5318 case InlineAsm::isInput: {
5319 SDValue InOperandVal = OpInfo.CallOperand;
5321 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5322 // If this is required to match an output register we have already set,
5323 // just use its register.
5324 unsigned OperandNo = OpInfo.getMatchedOperand();
5326 // Scan until we find the definition we already emitted of this operand.
5327 // When we find it, create a RegsForValue operand.
5328 unsigned CurOp = 2; // The first operand.
5329 for (; OperandNo; --OperandNo) {
5330 // Advance to the next operand.
5331 unsigned OpFlag =
5332 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5333 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5334 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5335 (OpFlag & 7) == 4 /*MEM*/) &&
5336 "Skipped past definitions?");
5337 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5340 unsigned OpFlag =
5341 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5342 if ((OpFlag & 7) == 2 /*REGDEF*/
5343 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5344 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5345 if (OpInfo.isIndirect) {
5346 llvm_report_error("Don't know how to handle tied indirect "
5347 "register inputs yet!");
5349 RegsForValue MatchedRegs;
5350 MatchedRegs.TLI = &TLI;
5351 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5352 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5353 MatchedRegs.RegVTs.push_back(RegVT);
5354 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5355 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5356 i != e; ++i)
5357 MatchedRegs.Regs.
5358 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5360 // Use the produced MatchedRegs object to
5361 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5362 Chain, &Flag);
5363 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5364 true, OpInfo.getMatchedOperand(),
5365 DAG, AsmNodeOperands);
5366 break;
5367 } else {
5368 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5369 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5370 "Unexpected number of operands");
5371 // Add information to the INLINEASM node to know about this input.
5372 // See InlineAsm.h isUseOperandTiedToDef.
5373 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5374 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5375 TLI.getPointerTy()));
5376 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5377 break;
5381 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5382 assert(!OpInfo.isIndirect &&
5383 "Don't know how to handle indirect other inputs yet!");
5385 std::vector<SDValue> Ops;
5386 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5387 hasMemory, Ops, DAG);
5388 if (Ops.empty()) {
5389 llvm_report_error("Invalid operand for inline asm"
5390 " constraint '" + OpInfo.ConstraintCode + "'!");
5393 // Add information to the INLINEASM node to know about this input.
5394 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5395 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5396 TLI.getPointerTy()));
5397 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5398 break;
5399 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5400 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5401 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5402 "Memory operands expect pointer values");
5404 // Add information to the INLINEASM node to know about this input.
5405 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5406 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5407 TLI.getPointerTy()));
5408 AsmNodeOperands.push_back(InOperandVal);
5409 break;
5412 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5413 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5414 "Unknown constraint type!");
5415 assert(!OpInfo.isIndirect &&
5416 "Don't know how to handle indirect register inputs yet!");
5418 // Copy the input into the appropriate registers.
5419 if (OpInfo.AssignedRegs.Regs.empty()) {
5420 llvm_report_error("Couldn't allocate input reg for"
5421 " constraint '"+ OpInfo.ConstraintCode +"'!");
5424 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5425 Chain, &Flag);
5427 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5428 DAG, AsmNodeOperands);
5429 break;
5431 case InlineAsm::isClobber: {
5432 // Add the clobbered value to the operand list, so that the register
5433 // allocator is aware that the physreg got clobbered.
5434 if (!OpInfo.AssignedRegs.Regs.empty())
5435 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5436 false, 0, DAG,AsmNodeOperands);
5437 break;
5442 // Finish up input operands.
5443 AsmNodeOperands[0] = Chain;
5444 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5446 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5447 DAG.getVTList(MVT::Other, MVT::Flag),
5448 &AsmNodeOperands[0], AsmNodeOperands.size());
5449 Flag = Chain.getValue(1);
5451 // If this asm returns a register value, copy the result from that register
5452 // and set it as the value of the call.
5453 if (!RetValRegs.Regs.empty()) {
5454 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5455 Chain, &Flag);
5457 // FIXME: Why don't we do this for inline asms with MRVs?
5458 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5459 EVT ResultType = TLI.getValueType(CS.getType());
5461 // If any of the results of the inline asm is a vector, it may have the
5462 // wrong width/num elts. This can happen for register classes that can
5463 // contain multiple different value types. The preg or vreg allocated may
5464 // not have the same VT as was expected. Convert it to the right type
5465 // with bit_convert.
5466 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5467 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5468 ResultType, Val);
5470 } else if (ResultType != Val.getValueType() &&
5471 ResultType.isInteger() && Val.getValueType().isInteger()) {
5472 // If a result value was tied to an input value, the computed result may
5473 // have a wider width than the expected result. Extract the relevant
5474 // portion.
5475 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5478 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5481 setValue(CS.getInstruction(), Val);
5482 // Don't need to use this as a chain in this case.
5483 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5484 return;
5487 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5489 // Process indirect outputs, first output all of the flagged copies out of
5490 // physregs.
5491 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5492 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5493 Value *Ptr = IndirectStoresToEmit[i].second;
5494 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5495 Chain, &Flag);
5496 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5500 // Emit the non-flagged stores from the physregs.
5501 SmallVector<SDValue, 8> OutChains;
5502 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5503 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5504 StoresToEmit[i].first,
5505 getValue(StoresToEmit[i].second),
5506 StoresToEmit[i].second, 0));
5507 if (!OutChains.empty())
5508 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5509 &OutChains[0], OutChains.size());
5510 DAG.setRoot(Chain);
5514 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5515 SDValue Src = getValue(I.getOperand(0));
5517 // Scale up by the type size in the original i32 type width. Various
5518 // mid-level optimizers may make assumptions about demanded bits etc from the
5519 // i32-ness of the optimizer: we do not want to promote to i64 and then
5520 // multiply on 64-bit targets.
5521 // FIXME: Malloc inst should go away: PR715.
5522 uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
5523 if (ElementSize != 1) {
5524 // Src is always 32-bits, make sure the constant fits.
5525 assert(Src.getValueType() == MVT::i32);
5526 ElementSize = (uint32_t)ElementSize;
5527 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5528 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5531 EVT IntPtr = TLI.getPointerTy();
5533 if (IntPtr.bitsLT(Src.getValueType()))
5534 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5535 else if (IntPtr.bitsGT(Src.getValueType()))
5536 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5538 TargetLowering::ArgListTy Args;
5539 TargetLowering::ArgListEntry Entry;
5540 Entry.Node = Src;
5541 Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext());
5542 Args.push_back(Entry);
5544 bool isTailCall = PerformTailCallOpt &&
5545 isInTailCallPosition(&I, Attribute::None, TLI);
5546 std::pair<SDValue,SDValue> Result =
5547 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5548 0, CallingConv::C, isTailCall,
5549 /*isReturnValueUsed=*/true,
5550 DAG.getExternalSymbol("malloc", IntPtr),
5551 Args, DAG, getCurDebugLoc());
5552 if (Result.first.getNode())
5553 setValue(&I, Result.first); // Pointers always fit in registers
5554 if (Result.second.getNode())
5555 DAG.setRoot(Result.second);
5558 void SelectionDAGLowering::visitFree(FreeInst &I) {
5559 TargetLowering::ArgListTy Args;
5560 TargetLowering::ArgListEntry Entry;
5561 Entry.Node = getValue(I.getOperand(0));
5562 Entry.Ty = TLI.getTargetData()->getIntPtrType(*DAG.getContext());
5563 Args.push_back(Entry);
5564 EVT IntPtr = TLI.getPointerTy();
5565 bool isTailCall = PerformTailCallOpt &&
5566 isInTailCallPosition(&I, Attribute::None, TLI);
5567 std::pair<SDValue,SDValue> Result =
5568 TLI.LowerCallTo(getRoot(), Type::getVoidTy(*DAG.getContext()),
5569 false, false, false, false,
5570 0, CallingConv::C, isTailCall,
5571 /*isReturnValueUsed=*/true,
5572 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5573 getCurDebugLoc());
5574 if (Result.second.getNode())
5575 DAG.setRoot(Result.second);
5578 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5579 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5580 MVT::Other, getRoot(),
5581 getValue(I.getOperand(1)),
5582 DAG.getSrcValue(I.getOperand(1))));
5585 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5586 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5587 getRoot(), getValue(I.getOperand(0)),
5588 DAG.getSrcValue(I.getOperand(0)));
5589 setValue(&I, V);
5590 DAG.setRoot(V.getValue(1));
5593 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5594 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5595 MVT::Other, getRoot(),
5596 getValue(I.getOperand(1)),
5597 DAG.getSrcValue(I.getOperand(1))));
5600 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5601 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5602 MVT::Other, getRoot(),
5603 getValue(I.getOperand(1)),
5604 getValue(I.getOperand(2)),
5605 DAG.getSrcValue(I.getOperand(1)),
5606 DAG.getSrcValue(I.getOperand(2))));
5609 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5610 /// implementation, which just calls LowerCall.
5611 /// FIXME: When all targets are
5612 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5613 std::pair<SDValue, SDValue>
5614 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5615 bool RetSExt, bool RetZExt, bool isVarArg,
5616 bool isInreg, unsigned NumFixedArgs,
5617 CallingConv::ID CallConv, bool isTailCall,
5618 bool isReturnValueUsed,
5619 SDValue Callee,
5620 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5622 assert((!isTailCall || PerformTailCallOpt) &&
5623 "isTailCall set when tail-call optimizations are disabled!");
5625 // Handle all of the outgoing arguments.
5626 SmallVector<ISD::OutputArg, 32> Outs;
5627 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5628 SmallVector<EVT, 4> ValueVTs;
5629 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5630 for (unsigned Value = 0, NumValues = ValueVTs.size();
5631 Value != NumValues; ++Value) {
5632 EVT VT = ValueVTs[Value];
5633 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5634 SDValue Op = SDValue(Args[i].Node.getNode(),
5635 Args[i].Node.getResNo() + Value);
5636 ISD::ArgFlagsTy Flags;
5637 unsigned OriginalAlignment =
5638 getTargetData()->getABITypeAlignment(ArgTy);
5640 if (Args[i].isZExt)
5641 Flags.setZExt();
5642 if (Args[i].isSExt)
5643 Flags.setSExt();
5644 if (Args[i].isInReg)
5645 Flags.setInReg();
5646 if (Args[i].isSRet)
5647 Flags.setSRet();
5648 if (Args[i].isByVal) {
5649 Flags.setByVal();
5650 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5651 const Type *ElementTy = Ty->getElementType();
5652 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5653 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5654 // For ByVal, alignment should come from FE. BE will guess if this
5655 // info is not there but there are cases it cannot get right.
5656 if (Args[i].Alignment)
5657 FrameAlign = Args[i].Alignment;
5658 Flags.setByValAlign(FrameAlign);
5659 Flags.setByValSize(FrameSize);
5661 if (Args[i].isNest)
5662 Flags.setNest();
5663 Flags.setOrigAlign(OriginalAlignment);
5665 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5666 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5667 SmallVector<SDValue, 4> Parts(NumParts);
5668 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5670 if (Args[i].isSExt)
5671 ExtendKind = ISD::SIGN_EXTEND;
5672 else if (Args[i].isZExt)
5673 ExtendKind = ISD::ZERO_EXTEND;
5675 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5677 for (unsigned j = 0; j != NumParts; ++j) {
5678 // if it isn't first piece, alignment must be 1
5679 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5680 if (NumParts > 1 && j == 0)
5681 MyFlags.Flags.setSplit();
5682 else if (j != 0)
5683 MyFlags.Flags.setOrigAlign(1);
5685 Outs.push_back(MyFlags);
5690 // Handle the incoming return values from the call.
5691 SmallVector<ISD::InputArg, 32> Ins;
5692 SmallVector<EVT, 4> RetTys;
5693 ComputeValueVTs(*this, RetTy, RetTys);
5694 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5695 EVT VT = RetTys[I];
5696 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5697 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5698 for (unsigned i = 0; i != NumRegs; ++i) {
5699 ISD::InputArg MyFlags;
5700 MyFlags.VT = RegisterVT;
5701 MyFlags.Used = isReturnValueUsed;
5702 if (RetSExt)
5703 MyFlags.Flags.setSExt();
5704 if (RetZExt)
5705 MyFlags.Flags.setZExt();
5706 if (isInreg)
5707 MyFlags.Flags.setInReg();
5708 Ins.push_back(MyFlags);
5712 // Check if target-dependent constraints permit a tail call here.
5713 // Target-independent constraints should be checked by the caller.
5714 if (isTailCall &&
5715 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
5716 isTailCall = false;
5718 SmallVector<SDValue, 4> InVals;
5719 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5720 Outs, Ins, dl, DAG, InVals);
5722 // Verify that the target's LowerCall behaved as expected.
5723 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5724 "LowerCall didn't return a valid chain!");
5725 assert((!isTailCall || InVals.empty()) &&
5726 "LowerCall emitted a return value for a tail call!");
5727 assert((isTailCall || InVals.size() == Ins.size()) &&
5728 "LowerCall didn't emit the correct number of values!");
5729 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5730 assert(InVals[i].getNode() &&
5731 "LowerCall emitted a null value!");
5732 assert(Ins[i].VT == InVals[i].getValueType() &&
5733 "LowerCall emitted a value with the wrong type!");
5736 // For a tail call, the return value is merely live-out and there aren't
5737 // any nodes in the DAG representing it. Return a special value to
5738 // indicate that a tail call has been emitted and no more Instructions
5739 // should be processed in the current block.
5740 if (isTailCall) {
5741 DAG.setRoot(Chain);
5742 return std::make_pair(SDValue(), SDValue());
5745 // Collect the legal value parts into potentially illegal values
5746 // that correspond to the original function's return values.
5747 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5748 if (RetSExt)
5749 AssertOp = ISD::AssertSext;
5750 else if (RetZExt)
5751 AssertOp = ISD::AssertZext;
5752 SmallVector<SDValue, 4> ReturnValues;
5753 unsigned CurReg = 0;
5754 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5755 EVT VT = RetTys[I];
5756 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5757 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5759 SDValue ReturnValue =
5760 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
5761 AssertOp);
5762 ReturnValues.push_back(ReturnValue);
5763 CurReg += NumRegs;
5766 // For a function returning void, there is no return value. We can't create
5767 // such a node, so we just return a null return value in that case. In
5768 // that case, nothing will actualy look at the value.
5769 if (ReturnValues.empty())
5770 return std::make_pair(SDValue(), Chain);
5772 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5773 DAG.getVTList(&RetTys[0], RetTys.size()),
5774 &ReturnValues[0], ReturnValues.size());
5776 return std::make_pair(Res, Chain);
5779 void TargetLowering::LowerOperationWrapper(SDNode *N,
5780 SmallVectorImpl<SDValue> &Results,
5781 SelectionDAG &DAG) {
5782 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5783 if (Res.getNode())
5784 Results.push_back(Res);
5787 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5788 llvm_unreachable("LowerOperation not implemented for this target!");
5789 return SDValue();
5793 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5794 SDValue Op = getValue(V);
5795 assert((Op.getOpcode() != ISD::CopyFromReg ||
5796 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5797 "Copy from a reg to the same reg!");
5798 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5800 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5801 SDValue Chain = DAG.getEntryNode();
5802 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5803 PendingExports.push_back(Chain);
5806 #include "llvm/CodeGen/SelectionDAGISel.h"
5808 void SelectionDAGISel::
5809 LowerArguments(BasicBlock *LLVMBB) {
5810 // If this is the entry block, emit arguments.
5811 Function &F = *LLVMBB->getParent();
5812 SelectionDAG &DAG = SDL->DAG;
5813 SDValue OldRoot = DAG.getRoot();
5814 DebugLoc dl = SDL->getCurDebugLoc();
5815 const TargetData *TD = TLI.getTargetData();
5817 // Set up the incoming argument description vector.
5818 SmallVector<ISD::InputArg, 16> Ins;
5819 unsigned Idx = 1;
5820 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5821 I != E; ++I, ++Idx) {
5822 SmallVector<EVT, 4> ValueVTs;
5823 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5824 bool isArgValueUsed = !I->use_empty();
5825 for (unsigned Value = 0, NumValues = ValueVTs.size();
5826 Value != NumValues; ++Value) {
5827 EVT VT = ValueVTs[Value];
5828 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5829 ISD::ArgFlagsTy Flags;
5830 unsigned OriginalAlignment =
5831 TD->getABITypeAlignment(ArgTy);
5833 if (F.paramHasAttr(Idx, Attribute::ZExt))
5834 Flags.setZExt();
5835 if (F.paramHasAttr(Idx, Attribute::SExt))
5836 Flags.setSExt();
5837 if (F.paramHasAttr(Idx, Attribute::InReg))
5838 Flags.setInReg();
5839 if (F.paramHasAttr(Idx, Attribute::StructRet))
5840 Flags.setSRet();
5841 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5842 Flags.setByVal();
5843 const PointerType *Ty = cast<PointerType>(I->getType());
5844 const Type *ElementTy = Ty->getElementType();
5845 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5846 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5847 // For ByVal, alignment should be passed from FE. BE will guess if
5848 // this info is not there but there are cases it cannot get right.
5849 if (F.getParamAlignment(Idx))
5850 FrameAlign = F.getParamAlignment(Idx);
5851 Flags.setByValAlign(FrameAlign);
5852 Flags.setByValSize(FrameSize);
5854 if (F.paramHasAttr(Idx, Attribute::Nest))
5855 Flags.setNest();
5856 Flags.setOrigAlign(OriginalAlignment);
5858 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5859 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5860 for (unsigned i = 0; i != NumRegs; ++i) {
5861 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5862 if (NumRegs > 1 && i == 0)
5863 MyFlags.Flags.setSplit();
5864 // if it isn't first piece, alignment must be 1
5865 else if (i > 0)
5866 MyFlags.Flags.setOrigAlign(1);
5867 Ins.push_back(MyFlags);
5872 // Call the target to set up the argument values.
5873 SmallVector<SDValue, 8> InVals;
5874 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5875 F.isVarArg(), Ins,
5876 dl, DAG, InVals);
5878 // Verify that the target's LowerFormalArguments behaved as expected.
5879 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5880 "LowerFormalArguments didn't return a valid chain!");
5881 assert(InVals.size() == Ins.size() &&
5882 "LowerFormalArguments didn't emit the correct number of values!");
5883 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5884 assert(InVals[i].getNode() &&
5885 "LowerFormalArguments emitted a null value!");
5886 assert(Ins[i].VT == InVals[i].getValueType() &&
5887 "LowerFormalArguments emitted a value with the wrong type!");
5890 // Update the DAG with the new chain value resulting from argument lowering.
5891 DAG.setRoot(NewRoot);
5893 // Set up the argument values.
5894 unsigned i = 0;
5895 Idx = 1;
5896 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5897 ++I, ++Idx) {
5898 SmallVector<SDValue, 4> ArgValues;
5899 SmallVector<EVT, 4> ValueVTs;
5900 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5901 unsigned NumValues = ValueVTs.size();
5902 for (unsigned Value = 0; Value != NumValues; ++Value) {
5903 EVT VT = ValueVTs[Value];
5904 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5905 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5907 if (!I->use_empty()) {
5908 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5909 if (F.paramHasAttr(Idx, Attribute::SExt))
5910 AssertOp = ISD::AssertSext;
5911 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5912 AssertOp = ISD::AssertZext;
5914 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
5915 PartVT, VT, AssertOp));
5917 i += NumParts;
5919 if (!I->use_empty()) {
5920 SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
5921 SDL->getCurDebugLoc()));
5922 // If this argument is live outside of the entry block, insert a copy from
5923 // whereever we got it to the vreg that other BB's will reference it as.
5924 SDL->CopyToExportRegsIfNeeded(I);
5927 assert(i == InVals.size() && "Argument register count mismatch!");
5929 // Finally, if the target has anything special to do, allow it to do so.
5930 // FIXME: this should insert code into the DAG!
5931 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5934 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5935 /// ensure constants are generated when needed. Remember the virtual registers
5936 /// that need to be added to the Machine PHI nodes as input. We cannot just
5937 /// directly add them, because expansion might result in multiple MBB's for one
5938 /// BB. As such, the start of the BB might correspond to a different MBB than
5939 /// the end.
5941 void
5942 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5943 TerminatorInst *TI = LLVMBB->getTerminator();
5945 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5947 // Check successor nodes' PHI nodes that expect a constant to be available
5948 // from this block.
5949 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5950 BasicBlock *SuccBB = TI->getSuccessor(succ);
5951 if (!isa<PHINode>(SuccBB->begin())) continue;
5952 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5954 // If this terminator has multiple identical successors (common for
5955 // switches), only handle each succ once.
5956 if (!SuccsHandled.insert(SuccMBB)) continue;
5958 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5959 PHINode *PN;
5961 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5962 // nodes and Machine PHI nodes, but the incoming operands have not been
5963 // emitted yet.
5964 for (BasicBlock::iterator I = SuccBB->begin();
5965 (PN = dyn_cast<PHINode>(I)); ++I) {
5966 // Ignore dead phi's.
5967 if (PN->use_empty()) continue;
5969 unsigned Reg;
5970 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5972 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5973 unsigned &RegOut = SDL->ConstantsOut[C];
5974 if (RegOut == 0) {
5975 RegOut = FuncInfo->CreateRegForValue(C);
5976 SDL->CopyValueToVirtualRegister(C, RegOut);
5978 Reg = RegOut;
5979 } else {
5980 Reg = FuncInfo->ValueMap[PHIOp];
5981 if (Reg == 0) {
5982 assert(isa<AllocaInst>(PHIOp) &&
5983 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5984 "Didn't codegen value into a register!??");
5985 Reg = FuncInfo->CreateRegForValue(PHIOp);
5986 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5990 // Remember that this register needs to added to the machine PHI node as
5991 // the input for this MBB.
5992 SmallVector<EVT, 4> ValueVTs;
5993 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5994 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5995 EVT VT = ValueVTs[vti];
5996 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5997 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5998 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5999 Reg += NumRegisters;
6003 SDL->ConstantsOut.clear();
6006 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
6007 /// supports legal types, and it emits MachineInstrs directly instead of
6008 /// creating SelectionDAG nodes.
6010 bool
6011 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
6012 FastISel *F) {
6013 TerminatorInst *TI = LLVMBB->getTerminator();
6015 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6016 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
6018 // Check successor nodes' PHI nodes that expect a constant to be available
6019 // from this block.
6020 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6021 BasicBlock *SuccBB = TI->getSuccessor(succ);
6022 if (!isa<PHINode>(SuccBB->begin())) continue;
6023 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
6025 // If this terminator has multiple identical successors (common for
6026 // switches), only handle each succ once.
6027 if (!SuccsHandled.insert(SuccMBB)) continue;
6029 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6030 PHINode *PN;
6032 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6033 // nodes and Machine PHI nodes, but the incoming operands have not been
6034 // emitted yet.
6035 for (BasicBlock::iterator I = SuccBB->begin();
6036 (PN = dyn_cast<PHINode>(I)); ++I) {
6037 // Ignore dead phi's.
6038 if (PN->use_empty()) continue;
6040 // Only handle legal types. Two interesting things to note here. First,
6041 // by bailing out early, we may leave behind some dead instructions,
6042 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
6043 // own moves. Second, this check is necessary becuase FastISel doesn't
6044 // use CreateRegForValue to create registers, so it always creates
6045 // exactly one register for each non-void instruction.
6046 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
6047 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
6048 // Promote MVT::i1.
6049 if (VT == MVT::i1)
6050 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
6051 else {
6052 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6053 return false;
6057 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6059 unsigned Reg = F->getRegForValue(PHIOp);
6060 if (Reg == 0) {
6061 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6062 return false;
6064 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
6068 return true;