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Fix comment for consistency sake.
[llvm/avr.git] / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blobe60a945580890196fccd1873bf9aafe44f24970e
1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/Target/TargetData.h"
17 #include "llvm/Target/TargetLoweringObjectFile.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/Target/TargetSubtarget.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/MathExtras.h"
29 using namespace llvm;
30
31 namespace llvm {
32 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
33 bool isLocal = GV->hasLocalLinkage();
34 bool isDeclaration = GV->isDeclaration();
35 // FIXME: what should we do for protected and internal visibility?
36 // For variables, is internal different from hidden?
37 bool isHidden = GV->hasHiddenVisibility();
38
39 if (reloc == Reloc::PIC_) {
40 if (isLocal || isHidden)
41 return TLSModel::LocalDynamic;
42 else
43 return TLSModel::GeneralDynamic;
44 } else {
45 if (!isDeclaration || isHidden)
46 return TLSModel::LocalExec;
47 else
48 return TLSModel::InitialExec;
49 }
50 }
51 }
52
53 /// InitLibcallNames - Set default libcall names.
54 ///
55 static void InitLibcallNames(const char **Names) {
56 Names[RTLIB::SHL_I16] = "__ashlhi3";
57 Names[RTLIB::SHL_I32] = "__ashlsi3";
58 Names[RTLIB::SHL_I64] = "__ashldi3";
59 Names[RTLIB::SHL_I128] = "__ashlti3";
60 Names[RTLIB::SRL_I16] = "__lshrhi3";
61 Names[RTLIB::SRL_I32] = "__lshrsi3";
62 Names[RTLIB::SRL_I64] = "__lshrdi3";
63 Names[RTLIB::SRL_I128] = "__lshrti3";
64 Names[RTLIB::SRA_I16] = "__ashrhi3";
65 Names[RTLIB::SRA_I32] = "__ashrsi3";
66 Names[RTLIB::SRA_I64] = "__ashrdi3";
67 Names[RTLIB::SRA_I128] = "__ashrti3";
68 Names[RTLIB::MUL_I16] = "__mulhi3";
69 Names[RTLIB::MUL_I32] = "__mulsi3";
70 Names[RTLIB::MUL_I64] = "__muldi3";
71 Names[RTLIB::MUL_I128] = "__multi3";
72 Names[RTLIB::SDIV_I16] = "__divhi3";
73 Names[RTLIB::SDIV_I32] = "__divsi3";
74 Names[RTLIB::SDIV_I64] = "__divdi3";
75 Names[RTLIB::SDIV_I128] = "__divti3";
76 Names[RTLIB::UDIV_I16] = "__udivhi3";
77 Names[RTLIB::UDIV_I32] = "__udivsi3";
78 Names[RTLIB::UDIV_I64] = "__udivdi3";
79 Names[RTLIB::UDIV_I128] = "__udivti3";
80 Names[RTLIB::SREM_I16] = "__modhi3";
81 Names[RTLIB::SREM_I32] = "__modsi3";
82 Names[RTLIB::SREM_I64] = "__moddi3";
83 Names[RTLIB::SREM_I128] = "__modti3";
84 Names[RTLIB::UREM_I16] = "__umodhi3";
85 Names[RTLIB::UREM_I32] = "__umodsi3";
86 Names[RTLIB::UREM_I64] = "__umoddi3";
87 Names[RTLIB::UREM_I128] = "__umodti3";
88 Names[RTLIB::NEG_I32] = "__negsi2";
89 Names[RTLIB::NEG_I64] = "__negdi2";
90 Names[RTLIB::ADD_F32] = "__addsf3";
91 Names[RTLIB::ADD_F64] = "__adddf3";
92 Names[RTLIB::ADD_F80] = "__addxf3";
93 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
94 Names[RTLIB::SUB_F32] = "__subsf3";
95 Names[RTLIB::SUB_F64] = "__subdf3";
96 Names[RTLIB::SUB_F80] = "__subxf3";
97 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
98 Names[RTLIB::MUL_F32] = "__mulsf3";
99 Names[RTLIB::MUL_F64] = "__muldf3";
100 Names[RTLIB::MUL_F80] = "__mulxf3";
101 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
102 Names[RTLIB::DIV_F32] = "__divsf3";
103 Names[RTLIB::DIV_F64] = "__divdf3";
104 Names[RTLIB::DIV_F80] = "__divxf3";
105 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
106 Names[RTLIB::REM_F32] = "fmodf";
107 Names[RTLIB::REM_F64] = "fmod";
108 Names[RTLIB::REM_F80] = "fmodl";
109 Names[RTLIB::REM_PPCF128] = "fmodl";
110 Names[RTLIB::POWI_F32] = "__powisf2";
111 Names[RTLIB::POWI_F64] = "__powidf2";
112 Names[RTLIB::POWI_F80] = "__powixf2";
113 Names[RTLIB::POWI_PPCF128] = "__powitf2";
114 Names[RTLIB::SQRT_F32] = "sqrtf";
115 Names[RTLIB::SQRT_F64] = "sqrt";
116 Names[RTLIB::SQRT_F80] = "sqrtl";
117 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
118 Names[RTLIB::LOG_F32] = "logf";
119 Names[RTLIB::LOG_F64] = "log";
120 Names[RTLIB::LOG_F80] = "logl";
121 Names[RTLIB::LOG_PPCF128] = "logl";
122 Names[RTLIB::LOG2_F32] = "log2f";
123 Names[RTLIB::LOG2_F64] = "log2";
124 Names[RTLIB::LOG2_F80] = "log2l";
125 Names[RTLIB::LOG2_PPCF128] = "log2l";
126 Names[RTLIB::LOG10_F32] = "log10f";
127 Names[RTLIB::LOG10_F64] = "log10";
128 Names[RTLIB::LOG10_F80] = "log10l";
129 Names[RTLIB::LOG10_PPCF128] = "log10l";
130 Names[RTLIB::EXP_F32] = "expf";
131 Names[RTLIB::EXP_F64] = "exp";
132 Names[RTLIB::EXP_F80] = "expl";
133 Names[RTLIB::EXP_PPCF128] = "expl";
134 Names[RTLIB::EXP2_F32] = "exp2f";
135 Names[RTLIB::EXP2_F64] = "exp2";
136 Names[RTLIB::EXP2_F80] = "exp2l";
137 Names[RTLIB::EXP2_PPCF128] = "exp2l";
138 Names[RTLIB::SIN_F32] = "sinf";
139 Names[RTLIB::SIN_F64] = "sin";
140 Names[RTLIB::SIN_F80] = "sinl";
141 Names[RTLIB::SIN_PPCF128] = "sinl";
142 Names[RTLIB::COS_F32] = "cosf";
143 Names[RTLIB::COS_F64] = "cos";
144 Names[RTLIB::COS_F80] = "cosl";
145 Names[RTLIB::COS_PPCF128] = "cosl";
146 Names[RTLIB::POW_F32] = "powf";
147 Names[RTLIB::POW_F64] = "pow";
148 Names[RTLIB::POW_F80] = "powl";
149 Names[RTLIB::POW_PPCF128] = "powl";
150 Names[RTLIB::CEIL_F32] = "ceilf";
151 Names[RTLIB::CEIL_F64] = "ceil";
152 Names[RTLIB::CEIL_F80] = "ceill";
153 Names[RTLIB::CEIL_PPCF128] = "ceill";
154 Names[RTLIB::TRUNC_F32] = "truncf";
155 Names[RTLIB::TRUNC_F64] = "trunc";
156 Names[RTLIB::TRUNC_F80] = "truncl";
157 Names[RTLIB::TRUNC_PPCF128] = "truncl";
158 Names[RTLIB::RINT_F32] = "rintf";
159 Names[RTLIB::RINT_F64] = "rint";
160 Names[RTLIB::RINT_F80] = "rintl";
161 Names[RTLIB::RINT_PPCF128] = "rintl";
162 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
163 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
164 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
165 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
166 Names[RTLIB::FLOOR_F32] = "floorf";
167 Names[RTLIB::FLOOR_F64] = "floor";
168 Names[RTLIB::FLOOR_F80] = "floorl";
169 Names[RTLIB::FLOOR_PPCF128] = "floorl";
170 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
171 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
172 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
173 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
174 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
175 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
176 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfi8";
177 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfi16";
178 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
179 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
180 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
181 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
182 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
183 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
184 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
185 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
186 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
187 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
188 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
189 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
190 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfi8";
191 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfi16";
192 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
193 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
194 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
195 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
196 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
197 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
198 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
199 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
200 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
201 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
202 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
203 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
204 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
205 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
206 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
207 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
208 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
209 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
210 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
211 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
212 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
213 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
214 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
215 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
216 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
217 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
218 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
219 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
220 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
221 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
222 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
223 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
224 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
225 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
226 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
227 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
228 Names[RTLIB::OEQ_F32] = "__eqsf2";
229 Names[RTLIB::OEQ_F64] = "__eqdf2";
230 Names[RTLIB::UNE_F32] = "__nesf2";
231 Names[RTLIB::UNE_F64] = "__nedf2";
232 Names[RTLIB::OGE_F32] = "__gesf2";
233 Names[RTLIB::OGE_F64] = "__gedf2";
234 Names[RTLIB::OLT_F32] = "__ltsf2";
235 Names[RTLIB::OLT_F64] = "__ltdf2";
236 Names[RTLIB::OLE_F32] = "__lesf2";
237 Names[RTLIB::OLE_F64] = "__ledf2";
238 Names[RTLIB::OGT_F32] = "__gtsf2";
239 Names[RTLIB::OGT_F64] = "__gtdf2";
240 Names[RTLIB::UO_F32] = "__unordsf2";
241 Names[RTLIB::UO_F64] = "__unorddf2";
242 Names[RTLIB::O_F32] = "__unordsf2";
243 Names[RTLIB::O_F64] = "__unorddf2";
244 Names[RTLIB::MEMCPY] = "memcpy";
245 Names[RTLIB::MEMMOVE] = "memmove";
246 Names[RTLIB::MEMSET] = "memset";
247 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
248 }
249
250 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
251 ///
252 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
253 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
254 CCs[i] = CallingConv::C;
255 }
256 }
257
258 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
259 /// UNKNOWN_LIBCALL if there is none.
260 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
261 if (OpVT == MVT::f32) {
262 if (RetVT == MVT::f64)
263 return FPEXT_F32_F64;
264 }
265 return UNKNOWN_LIBCALL;
266 }
267
268 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
269 /// UNKNOWN_LIBCALL if there is none.
270 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
271 if (RetVT == MVT::f32) {
272 if (OpVT == MVT::f64)
273 return FPROUND_F64_F32;
274 if (OpVT == MVT::f80)
275 return FPROUND_F80_F32;
276 if (OpVT == MVT::ppcf128)
277 return FPROUND_PPCF128_F32;
278 } else if (RetVT == MVT::f64) {
279 if (OpVT == MVT::f80)
280 return FPROUND_F80_F64;
281 if (OpVT == MVT::ppcf128)
282 return FPROUND_PPCF128_F64;
283 }
284 return UNKNOWN_LIBCALL;
285 }
286
287 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
288 /// UNKNOWN_LIBCALL if there is none.
289 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
290 if (OpVT == MVT::f32) {
291 if (RetVT == MVT::i8)
292 return FPTOSINT_F32_I8;
293 if (RetVT == MVT::i16)
294 return FPTOSINT_F32_I16;
295 if (RetVT == MVT::i32)
296 return FPTOSINT_F32_I32;
297 if (RetVT == MVT::i64)
298 return FPTOSINT_F32_I64;
299 if (RetVT == MVT::i128)
300 return FPTOSINT_F32_I128;
301 } else if (OpVT == MVT::f64) {
302 if (RetVT == MVT::i32)
303 return FPTOSINT_F64_I32;
304 if (RetVT == MVT::i64)
305 return FPTOSINT_F64_I64;
306 if (RetVT == MVT::i128)
307 return FPTOSINT_F64_I128;
308 } else if (OpVT == MVT::f80) {
309 if (RetVT == MVT::i32)
310 return FPTOSINT_F80_I32;
311 if (RetVT == MVT::i64)
312 return FPTOSINT_F80_I64;
313 if (RetVT == MVT::i128)
314 return FPTOSINT_F80_I128;
315 } else if (OpVT == MVT::ppcf128) {
316 if (RetVT == MVT::i32)
317 return FPTOSINT_PPCF128_I32;
318 if (RetVT == MVT::i64)
319 return FPTOSINT_PPCF128_I64;
320 if (RetVT == MVT::i128)
321 return FPTOSINT_PPCF128_I128;
322 }
323 return UNKNOWN_LIBCALL;
324 }
325
326 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
327 /// UNKNOWN_LIBCALL if there is none.
328 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
329 if (OpVT == MVT::f32) {
330 if (RetVT == MVT::i8)
331 return FPTOUINT_F32_I8;
332 if (RetVT == MVT::i16)
333 return FPTOUINT_F32_I16;
334 if (RetVT == MVT::i32)
335 return FPTOUINT_F32_I32;
336 if (RetVT == MVT::i64)
337 return FPTOUINT_F32_I64;
338 if (RetVT == MVT::i128)
339 return FPTOUINT_F32_I128;
340 } else if (OpVT == MVT::f64) {
341 if (RetVT == MVT::i32)
342 return FPTOUINT_F64_I32;
343 if (RetVT == MVT::i64)
344 return FPTOUINT_F64_I64;
345 if (RetVT == MVT::i128)
346 return FPTOUINT_F64_I128;
347 } else if (OpVT == MVT::f80) {
348 if (RetVT == MVT::i32)
349 return FPTOUINT_F80_I32;
350 if (RetVT == MVT::i64)
351 return FPTOUINT_F80_I64;
352 if (RetVT == MVT::i128)
353 return FPTOUINT_F80_I128;
354 } else if (OpVT == MVT::ppcf128) {
355 if (RetVT == MVT::i32)
356 return FPTOUINT_PPCF128_I32;
357 if (RetVT == MVT::i64)
358 return FPTOUINT_PPCF128_I64;
359 if (RetVT == MVT::i128)
360 return FPTOUINT_PPCF128_I128;
361 }
362 return UNKNOWN_LIBCALL;
363 }
364
365 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
366 /// UNKNOWN_LIBCALL if there is none.
367 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
368 if (OpVT == MVT::i32) {
369 if (RetVT == MVT::f32)
370 return SINTTOFP_I32_F32;
371 else if (RetVT == MVT::f64)
372 return SINTTOFP_I32_F64;
373 else if (RetVT == MVT::f80)
374 return SINTTOFP_I32_F80;
375 else if (RetVT == MVT::ppcf128)
376 return SINTTOFP_I32_PPCF128;
377 } else if (OpVT == MVT::i64) {
378 if (RetVT == MVT::f32)
379 return SINTTOFP_I64_F32;
380 else if (RetVT == MVT::f64)
381 return SINTTOFP_I64_F64;
382 else if (RetVT == MVT::f80)
383 return SINTTOFP_I64_F80;
384 else if (RetVT == MVT::ppcf128)
385 return SINTTOFP_I64_PPCF128;
386 } else if (OpVT == MVT::i128) {
387 if (RetVT == MVT::f32)
388 return SINTTOFP_I128_F32;
389 else if (RetVT == MVT::f64)
390 return SINTTOFP_I128_F64;
391 else if (RetVT == MVT::f80)
392 return SINTTOFP_I128_F80;
393 else if (RetVT == MVT::ppcf128)
394 return SINTTOFP_I128_PPCF128;
395 }
396 return UNKNOWN_LIBCALL;
397 }
398
399 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
400 /// UNKNOWN_LIBCALL if there is none.
401 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
402 if (OpVT == MVT::i32) {
403 if (RetVT == MVT::f32)
404 return UINTTOFP_I32_F32;
405 else if (RetVT == MVT::f64)
406 return UINTTOFP_I32_F64;
407 else if (RetVT == MVT::f80)
408 return UINTTOFP_I32_F80;
409 else if (RetVT == MVT::ppcf128)
410 return UINTTOFP_I32_PPCF128;
411 } else if (OpVT == MVT::i64) {
412 if (RetVT == MVT::f32)
413 return UINTTOFP_I64_F32;
414 else if (RetVT == MVT::f64)
415 return UINTTOFP_I64_F64;
416 else if (RetVT == MVT::f80)
417 return UINTTOFP_I64_F80;
418 else if (RetVT == MVT::ppcf128)
419 return UINTTOFP_I64_PPCF128;
420 } else if (OpVT == MVT::i128) {
421 if (RetVT == MVT::f32)
422 return UINTTOFP_I128_F32;
423 else if (RetVT == MVT::f64)
424 return UINTTOFP_I128_F64;
425 else if (RetVT == MVT::f80)
426 return UINTTOFP_I128_F80;
427 else if (RetVT == MVT::ppcf128)
428 return UINTTOFP_I128_PPCF128;
429 }
430 return UNKNOWN_LIBCALL;
431 }
432
433 /// InitCmpLibcallCCs - Set default comparison libcall CC.
434 ///
435 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
436 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
437 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
438 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
439 CCs[RTLIB::UNE_F32] = ISD::SETNE;
440 CCs[RTLIB::UNE_F64] = ISD::SETNE;
441 CCs[RTLIB::OGE_F32] = ISD::SETGE;
442 CCs[RTLIB::OGE_F64] = ISD::SETGE;
443 CCs[RTLIB::OLT_F32] = ISD::SETLT;
444 CCs[RTLIB::OLT_F64] = ISD::SETLT;
445 CCs[RTLIB::OLE_F32] = ISD::SETLE;
446 CCs[RTLIB::OLE_F64] = ISD::SETLE;
447 CCs[RTLIB::OGT_F32] = ISD::SETGT;
448 CCs[RTLIB::OGT_F64] = ISD::SETGT;
449 CCs[RTLIB::UO_F32] = ISD::SETNE;
450 CCs[RTLIB::UO_F64] = ISD::SETNE;
451 CCs[RTLIB::O_F32] = ISD::SETEQ;
452 CCs[RTLIB::O_F64] = ISD::SETEQ;
453 }
454
455 /// NOTE: The constructor takes ownership of TLOF.
456 TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof)
457 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
458 // All operations default to being supported.
459 memset(OpActions, 0, sizeof(OpActions));
460 memset(LoadExtActions, 0, sizeof(LoadExtActions));
461 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
462 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
463 memset(ConvertActions, 0, sizeof(ConvertActions));
464 memset(CondCodeActions, 0, sizeof(CondCodeActions));
465
466 // Set default actions for various operations.
467 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
468 // Default all indexed load / store to expand.
469 for (unsigned IM = (unsigned)ISD::PRE_INC;
470 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
471 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
472 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
473 }
474
475 // These operations default to expand.
476 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
477 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
478 }
479
480 // Most targets ignore the @llvm.prefetch intrinsic.
481 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
482
483 // ConstantFP nodes default to expand. Targets can either change this to
484 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
485 // to optimize expansions for certain constants.
486 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
487 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
488 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
489
490 // These library functions default to expand.
491 setOperationAction(ISD::FLOG , MVT::f64, Expand);
492 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
493 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
494 setOperationAction(ISD::FEXP , MVT::f64, Expand);
495 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
496 setOperationAction(ISD::FLOG , MVT::f32, Expand);
497 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
498 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
499 setOperationAction(ISD::FEXP , MVT::f32, Expand);
500 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
501
502 // Default ISD::TRAP to expand (which turns it into abort).
503 setOperationAction(ISD::TRAP, MVT::Other, Expand);
504
505 IsLittleEndian = TD->isLittleEndian();
506 UsesGlobalOffsetTable = false;
507 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
508 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
509 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
510 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
511 benefitFromCodePlacementOpt = false;
512 UseUnderscoreSetJmp = false;
513 UseUnderscoreLongJmp = false;
514 SelectIsExpensive = false;
515 IntDivIsCheap = false;
516 Pow2DivIsCheap = false;
517 StackPointerRegisterToSaveRestore = 0;
518 ExceptionPointerRegister = 0;
519 ExceptionSelectorRegister = 0;
520 BooleanContents = UndefinedBooleanContent;
521 SchedPreferenceInfo = SchedulingForLatency;
522 JumpBufSize = 0;
523 JumpBufAlignment = 0;
524 IfCvtBlockSizeLimit = 2;
525 IfCvtDupBlockSizeLimit = 0;
526 PrefLoopAlignment = 0;
527
528 InitLibcallNames(LibcallRoutineNames);
529 InitCmpLibcallCCs(CmpLibcallCCs);
530 InitLibcallCallingConvs(LibcallCallingConvs);
531
532 // Tell Legalize whether the assembler supports DEBUG_LOC.
533 const MCAsmInfo *TASM = TM.getMCAsmInfo();
534 if (!TASM || !TASM->hasDotLocAndDotFile())
535 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
536 }
537
538 TargetLowering::~TargetLowering() {
539 delete &TLOF;
540 }
541
542 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
543 unsigned &NumIntermediates,
544 EVT &RegisterVT,
545 TargetLowering* TLI) {
546 // Figure out the right, legal destination reg to copy into.
547 unsigned NumElts = VT.getVectorNumElements();
548 MVT EltTy = VT.getVectorElementType();
549
550 unsigned NumVectorRegs = 1;
551
552 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
553 // could break down into LHS/RHS like LegalizeDAG does.
554 if (!isPowerOf2_32(NumElts)) {
555 NumVectorRegs = NumElts;
556 NumElts = 1;
557 }
558
559 // Divide the input until we get to a supported size. This will always
560 // end with a scalar if the target doesn't support vectors.
561 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
562 NumElts >>= 1;
563 NumVectorRegs <<= 1;
564 }
565
566 NumIntermediates = NumVectorRegs;
567
568 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
569 if (!TLI->isTypeLegal(NewVT))
570 NewVT = EltTy;
571 IntermediateVT = NewVT;
572
573 EVT DestVT = TLI->getRegisterType(NewVT);
574 RegisterVT = DestVT;
575 if (EVT(DestVT).bitsLT(NewVT)) {
576 // Value is expanded, e.g. i64 -> i16.
577 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
578 } else {
579 // Otherwise, promotion or legal types use the same number of registers as
580 // the vector decimated to the appropriate level.
581 return NumVectorRegs;
582 }
583
584 return 1;
585 }
586
587 /// computeRegisterProperties - Once all of the register classes are added,
588 /// this allows us to compute derived properties we expose.
589 void TargetLowering::computeRegisterProperties() {
590 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
591 "Too many value types for ValueTypeActions to hold!");
592
593 // Everything defaults to needing one register.
594 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
595 NumRegistersForVT[i] = 1;
596 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
597 }
598 // ...except isVoid, which doesn't need any registers.
599 NumRegistersForVT[MVT::isVoid] = 0;
600
601 // Find the largest integer register class.
602 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
603 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
604 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
605
606 // Every integer value type larger than this largest register takes twice as
607 // many registers to represent as the previous ValueType.
608 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
609 EVT EVT = (MVT::SimpleValueType)ExpandedReg;
610 if (!EVT.isInteger())
611 break;
612 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
613 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
614 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
615 ValueTypeActions.setTypeAction(EVT, Expand);
616 }
617
618 // Inspect all of the ValueType's smaller than the largest integer
619 // register to see which ones need promotion.
620 unsigned LegalIntReg = LargestIntReg;
621 for (unsigned IntReg = LargestIntReg - 1;
622 IntReg >= (unsigned)MVT::i1; --IntReg) {
623 EVT IVT = (MVT::SimpleValueType)IntReg;
624 if (isTypeLegal(IVT)) {
625 LegalIntReg = IntReg;
626 } else {
627 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
628 (MVT::SimpleValueType)LegalIntReg;
629 ValueTypeActions.setTypeAction(IVT, Promote);
630 }
631 }
632
633 // ppcf128 type is really two f64's.
634 if (!isTypeLegal(MVT::ppcf128)) {
635 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
636 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
637 TransformToType[MVT::ppcf128] = MVT::f64;
638 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
639 }
640
641 // Decide how to handle f64. If the target does not have native f64 support,
642 // expand it to i64 and we will be generating soft float library calls.
643 if (!isTypeLegal(MVT::f64)) {
644 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
645 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
646 TransformToType[MVT::f64] = MVT::i64;
647 ValueTypeActions.setTypeAction(MVT::f64, Expand);
648 }
649
650 // Decide how to handle f32. If the target does not have native support for
651 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
652 if (!isTypeLegal(MVT::f32)) {
653 if (isTypeLegal(MVT::f64)) {
654 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
655 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
656 TransformToType[MVT::f32] = MVT::f64;
657 ValueTypeActions.setTypeAction(MVT::f32, Promote);
658 } else {
659 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
660 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
661 TransformToType[MVT::f32] = MVT::i32;
662 ValueTypeActions.setTypeAction(MVT::f32, Expand);
663 }
664 }
665
666 // Loop over all of the vector value types to see which need transformations.
667 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
668 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
669 MVT VT = (MVT::SimpleValueType)i;
670 if (!isTypeLegal(VT)) {
671 MVT IntermediateVT;
672 EVT RegisterVT;
673 unsigned NumIntermediates;
674 NumRegistersForVT[i] =
675 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
676 RegisterVT, this);
677 RegisterTypeForVT[i] = RegisterVT;
678
679 // Determine if there is a legal wider type.
680 bool IsLegalWiderType = false;
681 EVT EltVT = VT.getVectorElementType();
682 unsigned NElts = VT.getVectorNumElements();
683 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
684 EVT SVT = (MVT::SimpleValueType)nVT;
685 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
686 SVT.getVectorNumElements() > NElts) {
687 TransformToType[i] = SVT;
688 ValueTypeActions.setTypeAction(VT, Promote);
689 IsLegalWiderType = true;
690 break;
691 }
692 }
693 if (!IsLegalWiderType) {
694 EVT NVT = VT.getPow2VectorType();
695 if (NVT == VT) {
696 // Type is already a power of 2. The default action is to split.
697 TransformToType[i] = MVT::Other;
698 ValueTypeActions.setTypeAction(VT, Expand);
699 } else {
700 TransformToType[i] = NVT;
701 ValueTypeActions.setTypeAction(VT, Promote);
702 }
703 }
704 }
705 }
706 }
707
708 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
709 return NULL;
710 }
711
712
713 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
714 return PointerTy.SimpleTy;
715 }
716
717 /// getVectorTypeBreakdown - Vector types are broken down into some number of
718 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
719 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
720 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
721 ///
722 /// This method returns the number of registers needed, and the VT for each
723 /// register. It also returns the VT and quantity of the intermediate values
724 /// before they are promoted/expanded.
725 ///
726 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
727 EVT &IntermediateVT,
728 unsigned &NumIntermediates,
729 EVT &RegisterVT) const {
730 // Figure out the right, legal destination reg to copy into.
731 unsigned NumElts = VT.getVectorNumElements();
732 EVT EltTy = VT.getVectorElementType();
733
734 unsigned NumVectorRegs = 1;
735
736 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
737 // could break down into LHS/RHS like LegalizeDAG does.
738 if (!isPowerOf2_32(NumElts)) {
739 NumVectorRegs = NumElts;
740 NumElts = 1;
741 }
742
743 // Divide the input until we get to a supported size. This will always
744 // end with a scalar if the target doesn't support vectors.
745 while (NumElts > 1 && !isTypeLegal(
746 EVT::getVectorVT(Context, EltTy, NumElts))) {
747 NumElts >>= 1;
748 NumVectorRegs <<= 1;
749 }
750
751 NumIntermediates = NumVectorRegs;
752
753 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
754 if (!isTypeLegal(NewVT))
755 NewVT = EltTy;
756 IntermediateVT = NewVT;
757
758 EVT DestVT = getRegisterType(Context, NewVT);
759 RegisterVT = DestVT;
760 if (DestVT.bitsLT(NewVT)) {
761 // Value is expanded, e.g. i64 -> i16.
762 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
763 } else {
764 // Otherwise, promotion or legal types use the same number of registers as
765 // the vector decimated to the appropriate level.
766 return NumVectorRegs;
767 }
768
769 return 1;
770 }
771
772 /// getWidenVectorType: given a vector type, returns the type to widen to
773 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
774 /// If there is no vector type that we want to widen to, returns MVT::Other
775 /// When and where to widen is target dependent based on the cost of
776 /// scalarizing vs using the wider vector type.
777 EVT TargetLowering::getWidenVectorType(EVT VT) const {
778 assert(VT.isVector());
779 if (isTypeLegal(VT))
780 return VT;
781
782 // Default is not to widen until moved to LegalizeTypes
783 return MVT::Other;
784 }
785
786 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
787 /// function arguments in the caller parameter area. This is the actual
788 /// alignment, not its logarithm.
789 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
790 return TD->getCallFrameTypeAlignment(Ty);
791 }
792
793 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
794 SelectionDAG &DAG) const {
795 if (usesGlobalOffsetTable())
796 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
797 return Table;
798 }
799
800 bool
801 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
802 // Assume that everything is safe in static mode.
803 if (getTargetMachine().getRelocationModel() == Reloc::Static)
804 return true;
805
806 // In dynamic-no-pic mode, assume that known defined values are safe.
807 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
808 GA &&
809 !GA->getGlobal()->isDeclaration() &&
810 !GA->getGlobal()->isWeakForLinker())
811 return true;
812
813 // Otherwise assume nothing is safe.
814 return false;
815 }
816
817 //===----------------------------------------------------------------------===//
818 // Optimization Methods
819 //===----------------------------------------------------------------------===//
820
821 /// ShrinkDemandedConstant - Check to see if the specified operand of the
822 /// specified instruction is a constant integer. If so, check to see if there
823 /// are any bits set in the constant that are not demanded. If so, shrink the
824 /// constant and return true.
825 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
826 const APInt &Demanded) {
827 DebugLoc dl = Op.getDebugLoc();
828
829 // FIXME: ISD::SELECT, ISD::SELECT_CC
830 switch (Op.getOpcode()) {
831 default: break;
832 case ISD::XOR:
833 case ISD::AND:
834 case ISD::OR: {
835 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
836 if (!C) return false;
837
838 if (Op.getOpcode() == ISD::XOR &&
839 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
840 return false;
841
842 // if we can expand it to have all bits set, do it
843 if (C->getAPIntValue().intersects(~Demanded)) {
844 EVT VT = Op.getValueType();
845 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
846 DAG.getConstant(Demanded &
847 C->getAPIntValue(),
848 VT));
849 return CombineTo(Op, New);
850 }
851
852 break;
853 }
854 }
855
856 return false;
857 }
858
859 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
860 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
861 /// cast, but it could be generalized for targets with other types of
862 /// implicit widening casts.
863 bool
864 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
865 unsigned BitWidth,
866 const APInt &Demanded,
867 DebugLoc dl) {
868 assert(Op.getNumOperands() == 2 &&
869 "ShrinkDemandedOp only supports binary operators!");
870 assert(Op.getNode()->getNumValues() == 1 &&
871 "ShrinkDemandedOp only supports nodes with one result!");
872
873 // Don't do this if the node has another user, which may require the
874 // full value.
875 if (!Op.getNode()->hasOneUse())
876 return false;
877
878 // Search for the smallest integer type with free casts to and from
879 // Op's type. For expedience, just check power-of-2 integer types.
880 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
881 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
882 if (!isPowerOf2_32(SmallVTBits))
883 SmallVTBits = NextPowerOf2(SmallVTBits);
884 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
885 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
886 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
887 TLI.isZExtFree(SmallVT, Op.getValueType())) {
888 // We found a type with free casts.
889 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
890 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
891 Op.getNode()->getOperand(0)),
892 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
893 Op.getNode()->getOperand(1)));
894 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
895 return CombineTo(Op, Z);
896 }
897 }
898 return false;
899 }
900
901 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
902 /// DemandedMask bits of the result of Op are ever used downstream. If we can
903 /// use this information to simplify Op, create a new simplified DAG node and
904 /// return true, returning the original and new nodes in Old and New. Otherwise,
905 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
906 /// the expression (used to simplify the caller). The KnownZero/One bits may
907 /// only be accurate for those bits in the DemandedMask.
908 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
909 const APInt &DemandedMask,
910 APInt &KnownZero,
911 APInt &KnownOne,
912 TargetLoweringOpt &TLO,
913 unsigned Depth) const {
914 unsigned BitWidth = DemandedMask.getBitWidth();
915 assert(Op.getValueSizeInBits() == BitWidth &&
916 "Mask size mismatches value type size!");
917 APInt NewMask = DemandedMask;
918 DebugLoc dl = Op.getDebugLoc();
919
920 // Don't know anything.
921 KnownZero = KnownOne = APInt(BitWidth, 0);
922
923 // Other users may use these bits.
924 if (!Op.getNode()->hasOneUse()) {
925 if (Depth != 0) {
926 // If not at the root, Just compute the KnownZero/KnownOne bits to
927 // simplify things downstream.
928 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
929 return false;
930 }
931 // If this is the root being simplified, allow it to have multiple uses,
932 // just set the NewMask to all bits.
933 NewMask = APInt::getAllOnesValue(BitWidth);
934 } else if (DemandedMask == 0) {
935 // Not demanding any bits from Op.
936 if (Op.getOpcode() != ISD::UNDEF)
937 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
938 return false;
939 } else if (Depth == 6) { // Limit search depth.
940 return false;
941 }
942
943 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
944 switch (Op.getOpcode()) {
945 case ISD::Constant:
946 // We know all of the bits for a constant!
947 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
948 KnownZero = ~KnownOne & NewMask;
949 return false; // Don't fall through, will infinitely loop.
950 case ISD::AND:
951 // If the RHS is a constant, check to see if the LHS would be zero without
952 // using the bits from the RHS. Below, we use knowledge about the RHS to
953 // simplify the LHS, here we're using information from the LHS to simplify
954 // the RHS.
955 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
956 APInt LHSZero, LHSOne;
957 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
958 LHSZero, LHSOne, Depth+1);
959 // If the LHS already has zeros where RHSC does, this and is dead.
960 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
961 return TLO.CombineTo(Op, Op.getOperand(0));
962 // If any of the set bits in the RHS are known zero on the LHS, shrink
963 // the constant.
964 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
965 return true;
966 }
967
968 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
969 KnownOne, TLO, Depth+1))
970 return true;
971 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
972 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
973 KnownZero2, KnownOne2, TLO, Depth+1))
974 return true;
975 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
976
977 // If all of the demanded bits are known one on one side, return the other.
978 // These bits cannot contribute to the result of the 'and'.
979 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
980 return TLO.CombineTo(Op, Op.getOperand(0));
981 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
982 return TLO.CombineTo(Op, Op.getOperand(1));
983 // If all of the demanded bits in the inputs are known zeros, return zero.
984 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
985 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
986 // If the RHS is a constant, see if we can simplify it.
987 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
988 return true;
989 // If the operation can be done in a smaller type, do so.
990 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
991 return true;
992
993 // Output known-1 bits are only known if set in both the LHS & RHS.
994 KnownOne &= KnownOne2;
995 // Output known-0 are known to be clear if zero in either the LHS | RHS.
996 KnownZero |= KnownZero2;
997 break;
998 case ISD::OR:
999 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1000 KnownOne, TLO, Depth+1))
1001 return true;
1002 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1003 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1004 KnownZero2, KnownOne2, TLO, Depth+1))
1005 return true;
1006 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1007
1008 // If all of the demanded bits are known zero on one side, return the other.
1009 // These bits cannot contribute to the result of the 'or'.
1010 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1011 return TLO.CombineTo(Op, Op.getOperand(0));
1012 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1013 return TLO.CombineTo(Op, Op.getOperand(1));
1014 // If all of the potentially set bits on one side are known to be set on
1015 // the other side, just use the 'other' side.
1016 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1017 return TLO.CombineTo(Op, Op.getOperand(0));
1018 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1019 return TLO.CombineTo(Op, Op.getOperand(1));
1020 // If the RHS is a constant, see if we can simplify it.
1021 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1022 return true;
1023 // If the operation can be done in a smaller type, do so.
1024 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1025 return true;
1026
1027 // Output known-0 bits are only known if clear in both the LHS & RHS.
1028 KnownZero &= KnownZero2;
1029 // Output known-1 are known to be set if set in either the LHS | RHS.
1030 KnownOne |= KnownOne2;
1031 break;
1032 case ISD::XOR:
1033 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1034 KnownOne, TLO, Depth+1))
1035 return true;
1036 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1037 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1038 KnownOne2, TLO, Depth+1))
1039 return true;
1040 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1041
1042 // If all of the demanded bits are known zero on one side, return the other.
1043 // These bits cannot contribute to the result of the 'xor'.
1044 if ((KnownZero & NewMask) == NewMask)
1045 return TLO.CombineTo(Op, Op.getOperand(0));
1046 if ((KnownZero2 & NewMask) == NewMask)
1047 return TLO.CombineTo(Op, Op.getOperand(1));
1048 // If the operation can be done in a smaller type, do so.
1049 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1050 return true;
1051
1052 // If all of the unknown bits are known to be zero on one side or the other
1053 // (but not both) turn this into an *inclusive* or.
1054 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1055 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1056 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1057 Op.getOperand(0),
1058 Op.getOperand(1)));
1059
1060 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1061 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1062 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1063 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1064
1065 // If all of the demanded bits on one side are known, and all of the set
1066 // bits on that side are also known to be set on the other side, turn this
1067 // into an AND, as we know the bits will be cleared.
1068 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1069 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1070 if ((KnownOne & KnownOne2) == KnownOne) {
1071 EVT VT = Op.getValueType();
1072 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1073 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1074 Op.getOperand(0), ANDC));
1075 }
1076 }
1077
1078 // If the RHS is a constant, see if we can simplify it.
1079 // for XOR, we prefer to force bits to 1 if they will make a -1.
1080 // if we can't force bits, try to shrink constant
1081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1082 APInt Expanded = C->getAPIntValue() | (~NewMask);
1083 // if we can expand it to have all bits set, do it
1084 if (Expanded.isAllOnesValue()) {
1085 if (Expanded != C->getAPIntValue()) {
1086 EVT VT = Op.getValueType();
1087 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1088 TLO.DAG.getConstant(Expanded, VT));
1089 return TLO.CombineTo(Op, New);
1090 }
1091 // if it already has all the bits set, nothing to change
1092 // but don't shrink either!
1093 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1094 return true;
1095 }
1096 }
1097
1098 KnownZero = KnownZeroOut;
1099 KnownOne = KnownOneOut;
1100 break;
1101 case ISD::SELECT:
1102 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1103 KnownOne, TLO, Depth+1))
1104 return true;
1105 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1106 KnownOne2, TLO, Depth+1))
1107 return true;
1108 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1109 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1110
1111 // If the operands are constants, see if we can simplify them.
1112 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1113 return true;
1114
1115 // Only known if known in both the LHS and RHS.
1116 KnownOne &= KnownOne2;
1117 KnownZero &= KnownZero2;
1118 break;
1119 case ISD::SELECT_CC:
1120 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1121 KnownOne, TLO, Depth+1))
1122 return true;
1123 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1124 KnownOne2, TLO, Depth+1))
1125 return true;
1126 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1127 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1128
1129 // If the operands are constants, see if we can simplify them.
1130 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1131 return true;
1132
1133 // Only known if known in both the LHS and RHS.
1134 KnownOne &= KnownOne2;
1135 KnownZero &= KnownZero2;
1136 break;
1137 case ISD::SHL:
1138 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1139 unsigned ShAmt = SA->getZExtValue();
1140 SDValue InOp = Op.getOperand(0);
1141
1142 // If the shift count is an invalid immediate, don't do anything.
1143 if (ShAmt >= BitWidth)
1144 break;
1145
1146 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1147 // single shift. We can do this if the bottom bits (which are shifted
1148 // out) are never demanded.
1149 if (InOp.getOpcode() == ISD::SRL &&
1150 isa<ConstantSDNode>(InOp.getOperand(1))) {
1151 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1152 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1153 unsigned Opc = ISD::SHL;
1154 int Diff = ShAmt-C1;
1155 if (Diff < 0) {
1156 Diff = -Diff;
1157 Opc = ISD::SRL;
1158 }
1159
1160 SDValue NewSA =
1161 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1162 EVT VT = Op.getValueType();
1163 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1164 InOp.getOperand(0), NewSA));
1165 }
1166 }
1167
1168 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1169 KnownZero, KnownOne, TLO, Depth+1))
1170 return true;
1171 KnownZero <<= SA->getZExtValue();
1172 KnownOne <<= SA->getZExtValue();
1173 // low bits known zero.
1174 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1175 }
1176 break;
1177 case ISD::SRL:
1178 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1179 EVT VT = Op.getValueType();
1180 unsigned ShAmt = SA->getZExtValue();
1181 unsigned VTSize = VT.getSizeInBits();
1182 SDValue InOp = Op.getOperand(0);
1183
1184 // If the shift count is an invalid immediate, don't do anything.
1185 if (ShAmt >= BitWidth)
1186 break;
1187
1188 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1189 // single shift. We can do this if the top bits (which are shifted out)
1190 // are never demanded.
1191 if (InOp.getOpcode() == ISD::SHL &&
1192 isa<ConstantSDNode>(InOp.getOperand(1))) {
1193 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1194 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1195 unsigned Opc = ISD::SRL;
1196 int Diff = ShAmt-C1;
1197 if (Diff < 0) {
1198 Diff = -Diff;
1199 Opc = ISD::SHL;
1200 }
1201
1202 SDValue NewSA =
1203 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1204 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1205 InOp.getOperand(0), NewSA));
1206 }
1207 }
1208
1209 // Compute the new bits that are at the top now.
1210 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1211 KnownZero, KnownOne, TLO, Depth+1))
1212 return true;
1213 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1214 KnownZero = KnownZero.lshr(ShAmt);
1215 KnownOne = KnownOne.lshr(ShAmt);
1216
1217 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1218 KnownZero |= HighBits; // High bits known zero.
1219 }
1220 break;
1221 case ISD::SRA:
1222 // If this is an arithmetic shift right and only the low-bit is set, we can
1223 // always convert this into a logical shr, even if the shift amount is
1224 // variable. The low bit of the shift cannot be an input sign bit unless
1225 // the shift amount is >= the size of the datatype, which is undefined.
1226 if (DemandedMask == 1)
1227 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1228 Op.getOperand(0), Op.getOperand(1)));
1229
1230 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1231 EVT VT = Op.getValueType();
1232 unsigned ShAmt = SA->getZExtValue();
1233
1234 // If the shift count is an invalid immediate, don't do anything.
1235 if (ShAmt >= BitWidth)
1236 break;
1237
1238 APInt InDemandedMask = (NewMask << ShAmt);
1239
1240 // If any of the demanded bits are produced by the sign extension, we also
1241 // demand the input sign bit.
1242 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1243 if (HighBits.intersects(NewMask))
1244 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1245
1246 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1247 KnownZero, KnownOne, TLO, Depth+1))
1248 return true;
1249 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1250 KnownZero = KnownZero.lshr(ShAmt);
1251 KnownOne = KnownOne.lshr(ShAmt);
1252
1253 // Handle the sign bit, adjusted to where it is now in the mask.
1254 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1255
1256 // If the input sign bit is known to be zero, or if none of the top bits
1257 // are demanded, turn this into an unsigned shift right.
1258 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1259 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1260 Op.getOperand(0),
1261 Op.getOperand(1)));
1262 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1263 KnownOne |= HighBits;
1264 }
1265 }
1266 break;
1267 case ISD::SIGN_EXTEND_INREG: {
1268 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1269
1270 // Sign extension. Compute the demanded bits in the result that are not
1271 // present in the input.
1272 APInt NewBits = APInt::getHighBitsSet(BitWidth,
1273 BitWidth - EVT.getSizeInBits()) &
1274 NewMask;
1275
1276 // If none of the extended bits are demanded, eliminate the sextinreg.
1277 if (NewBits == 0)
1278 return TLO.CombineTo(Op, Op.getOperand(0));
1279
1280 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1281 InSignBit.zext(BitWidth);
1282 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1283 EVT.getSizeInBits()) &
1284 NewMask;
1285
1286 // Since the sign extended bits are demanded, we know that the sign
1287 // bit is demanded.
1288 InputDemandedBits |= InSignBit;
1289
1290 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1291 KnownZero, KnownOne, TLO, Depth+1))
1292 return true;
1293 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1294
1295 // If the sign bit of the input is known set or clear, then we know the
1296 // top bits of the result.
1297
1298 // If the input sign bit is known zero, convert this into a zero extension.
1299 if (KnownZero.intersects(InSignBit))
1300 return TLO.CombineTo(Op,
1301 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1302
1303 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1304 KnownOne |= NewBits;
1305 KnownZero &= ~NewBits;
1306 } else { // Input sign bit unknown
1307 KnownZero &= ~NewBits;
1308 KnownOne &= ~NewBits;
1309 }
1310 break;
1311 }
1312 case ISD::ZERO_EXTEND: {
1313 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1314 APInt InMask = NewMask;
1315 InMask.trunc(OperandBitWidth);
1316
1317 // If none of the top bits are demanded, convert this into an any_extend.
1318 APInt NewBits =
1319 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1320 if (!NewBits.intersects(NewMask))
1321 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1322 Op.getValueType(),
1323 Op.getOperand(0)));
1324
1325 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1326 KnownZero, KnownOne, TLO, Depth+1))
1327 return true;
1328 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1329 KnownZero.zext(BitWidth);
1330 KnownOne.zext(BitWidth);
1331 KnownZero |= NewBits;
1332 break;
1333 }
1334 case ISD::SIGN_EXTEND: {
1335 EVT InVT = Op.getOperand(0).getValueType();
1336 unsigned InBits = InVT.getSizeInBits();
1337 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1338 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1339 APInt NewBits = ~InMask & NewMask;
1340
1341 // If none of the top bits are demanded, convert this into an any_extend.
1342 if (NewBits == 0)
1343 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1344 Op.getValueType(),
1345 Op.getOperand(0)));
1346
1347 // Since some of the sign extended bits are demanded, we know that the sign
1348 // bit is demanded.
1349 APInt InDemandedBits = InMask & NewMask;
1350 InDemandedBits |= InSignBit;
1351 InDemandedBits.trunc(InBits);
1352
1353 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1354 KnownOne, TLO, Depth+1))
1355 return true;
1356 KnownZero.zext(BitWidth);
1357 KnownOne.zext(BitWidth);
1358
1359 // If the sign bit is known zero, convert this to a zero extend.
1360 if (KnownZero.intersects(InSignBit))
1361 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1362 Op.getValueType(),
1363 Op.getOperand(0)));
1364
1365 // If the sign bit is known one, the top bits match.
1366 if (KnownOne.intersects(InSignBit)) {
1367 KnownOne |= NewBits;
1368 KnownZero &= ~NewBits;
1369 } else { // Otherwise, top bits aren't known.
1370 KnownOne &= ~NewBits;
1371 KnownZero &= ~NewBits;
1372 }
1373 break;
1374 }
1375 case ISD::ANY_EXTEND: {
1376 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1377 APInt InMask = NewMask;
1378 InMask.trunc(OperandBitWidth);
1379 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1380 KnownZero, KnownOne, TLO, Depth+1))
1381 return true;
1382 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1383 KnownZero.zext(BitWidth);
1384 KnownOne.zext(BitWidth);
1385 break;
1386 }
1387 case ISD::TRUNCATE: {
1388 // Simplify the input, using demanded bit information, and compute the known
1389 // zero/one bits live out.
1390 APInt TruncMask = NewMask;
1391 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1392 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1393 KnownZero, KnownOne, TLO, Depth+1))
1394 return true;
1395 KnownZero.trunc(BitWidth);
1396 KnownOne.trunc(BitWidth);
1397
1398 // If the input is only used by this truncate, see if we can shrink it based
1399 // on the known demanded bits.
1400 if (Op.getOperand(0).getNode()->hasOneUse()) {
1401 SDValue In = Op.getOperand(0);
1402 unsigned InBitWidth = In.getValueSizeInBits();
1403 switch (In.getOpcode()) {
1404 default: break;
1405 case ISD::SRL:
1406 // Shrink SRL by a constant if none of the high bits shifted in are
1407 // demanded.
1408 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1409 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1410 InBitWidth - BitWidth);
1411 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1412 HighBits.trunc(BitWidth);
1413
1414 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1415 // None of the shifted in bits are needed. Add a truncate of the
1416 // shift input, then shift it.
1417 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1418 Op.getValueType(),
1419 In.getOperand(0));
1420 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1421 Op.getValueType(),
1422 NewTrunc,
1423 In.getOperand(1)));
1424 }
1425 }
1426 break;
1427 }
1428 }
1429
1430 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1431 break;
1432 }
1433 case ISD::AssertZext: {
1434 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1435 APInt InMask = APInt::getLowBitsSet(BitWidth,
1436 VT.getSizeInBits());
1437 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1438 KnownZero, KnownOne, TLO, Depth+1))
1439 return true;
1440 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1441 KnownZero |= ~InMask & NewMask;
1442 break;
1443 }
1444 case ISD::BIT_CONVERT:
1445 #if 0
1446 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1447 // is demanded, turn this into a FGETSIGN.
1448 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
1449 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1450 !MVT::isVector(Op.getOperand(0).getValueType())) {
1451 // Only do this xform if FGETSIGN is valid or if before legalize.
1452 if (!TLO.AfterLegalize ||
1453 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1454 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1455 // place. We expect the SHL to be eliminated by other optimizations.
1456 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1457 Op.getOperand(0));
1458 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1459 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1460 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1461 Sign, ShAmt));
1462 }
1463 }
1464 #endif
1465 break;
1466 case ISD::ADD:
1467 case ISD::MUL:
1468 case ISD::SUB: {
1469 // Add, Sub, and Mul don't demand any bits in positions beyond that
1470 // of the highest bit demanded of them.
1471 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1472 BitWidth - NewMask.countLeadingZeros());
1473 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1474 KnownOne2, TLO, Depth+1))
1475 return true;
1476 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1477 KnownOne2, TLO, Depth+1))
1478 return true;
1479 // See if the operation should be performed at a smaller bit width.
1480 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1481 return true;
1482 }
1483 // FALL THROUGH
1484 default:
1485 // Just use ComputeMaskedBits to compute output bits.
1486 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1487 break;
1488 }
1489
1490 // If we know the value of all of the demanded bits, return this as a
1491 // constant.
1492 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1493 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1494
1495 return false;
1496 }
1497
1498 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1499 /// in Mask are known to be either zero or one and return them in the
1500 /// KnownZero/KnownOne bitsets.
1501 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1502 const APInt &Mask,
1503 APInt &KnownZero,
1504 APInt &KnownOne,
1505 const SelectionDAG &DAG,
1506 unsigned Depth) const {
1507 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1508 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1509 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1510 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1511 "Should use MaskedValueIsZero if you don't know whether Op"
1512 " is a target node!");
1513 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1514 }
1515
1516 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1517 /// targets that want to expose additional information about sign bits to the
1518 /// DAG Combiner.
1519 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1520 unsigned Depth) const {
1521 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1522 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1523 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1524 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1525 "Should use ComputeNumSignBits if you don't know whether Op"
1526 " is a target node!");
1527 return 1;
1528 }
1529
1530 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1531 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1532 /// determine which bit is set.
1533 ///
1534 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1535 // A left-shift of a constant one will have exactly one bit set, because
1536 // shifting the bit off the end is undefined.
1537 if (Val.getOpcode() == ISD::SHL)
1538 if (ConstantSDNode *C =
1539 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1540 if (C->getAPIntValue() == 1)
1541 return true;
1542
1543 // Similarly, a right-shift of a constant sign-bit will have exactly
1544 // one bit set.
1545 if (Val.getOpcode() == ISD::SRL)
1546 if (ConstantSDNode *C =
1547 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1548 if (C->getAPIntValue().isSignBit())
1549 return true;
1550
1551 // More could be done here, though the above checks are enough
1552 // to handle some common cases.
1553
1554 // Fall back to ComputeMaskedBits to catch other known cases.
1555 EVT OpVT = Val.getValueType();
1556 unsigned BitWidth = OpVT.getSizeInBits();
1557 APInt Mask = APInt::getAllOnesValue(BitWidth);
1558 APInt KnownZero, KnownOne;
1559 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1560 return (KnownZero.countPopulation() == BitWidth - 1) &&
1561 (KnownOne.countPopulation() == 1);
1562 }
1563
1564 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1565 /// and cc. If it is unable to simplify it, return a null SDValue.
1566 SDValue
1567 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1568 ISD::CondCode Cond, bool foldBooleans,
1569 DAGCombinerInfo &DCI, DebugLoc dl) const {
1570 SelectionDAG &DAG = DCI.DAG;
1571 LLVMContext &Context = *DAG.getContext();
1572
1573 // These setcc operations always fold.
1574 switch (Cond) {
1575 default: break;
1576 case ISD::SETFALSE:
1577 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1578 case ISD::SETTRUE:
1579 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1580 }
1581
1582 if (isa<ConstantSDNode>(N0.getNode())) {
1583 // Ensure that the constant occurs on the RHS, and fold constant
1584 // comparisons.
1585 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1586 }
1587
1588 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1589 const APInt &C1 = N1C->getAPIntValue();
1590
1591 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1592 // equality comparison, then we're just comparing whether X itself is
1593 // zero.
1594 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1595 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1596 N0.getOperand(1).getOpcode() == ISD::Constant) {
1597 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1598 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1599 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1600 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1601 // (srl (ctlz x), 5) == 0 -> X != 0
1602 // (srl (ctlz x), 5) != 1 -> X != 0
1603 Cond = ISD::SETNE;
1604 } else {
1605 // (srl (ctlz x), 5) != 0 -> X == 0
1606 // (srl (ctlz x), 5) == 1 -> X == 0
1607 Cond = ISD::SETEQ;
1608 }
1609 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1610 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1611 Zero, Cond);
1612 }
1613 }
1614
1615 // If the LHS is '(and load, const)', the RHS is 0,
1616 // the test is for equality or unsigned, and all 1 bits of the const are
1617 // in the same partial word, see if we can shorten the load.
1618 if (DCI.isBeforeLegalize() &&
1619 N0.getOpcode() == ISD::AND && C1 == 0 &&
1620 N0.getNode()->hasOneUse() &&
1621 isa<LoadSDNode>(N0.getOperand(0)) &&
1622 N0.getOperand(0).getNode()->hasOneUse() &&
1623 isa<ConstantSDNode>(N0.getOperand(1))) {
1624 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1625 uint64_t bestMask = 0;
1626 unsigned bestWidth = 0, bestOffset = 0;
1627 if (!Lod->isVolatile() && Lod->isUnindexed() &&
1628 // FIXME: This uses getZExtValue() below so it only works on i64 and
1629 // below.
1630 N0.getValueType().getSizeInBits() <= 64) {
1631 unsigned origWidth = N0.getValueType().getSizeInBits();
1632 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1633 // 8 bits, but have to be careful...
1634 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1635 origWidth = Lod->getMemoryVT().getSizeInBits();
1636 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1637 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1638 uint64_t newMask = (1ULL << width) - 1;
1639 for (unsigned offset=0; offset<origWidth/width; offset++) {
1640 if ((newMask & Mask) == Mask) {
1641 if (!TD->isLittleEndian())
1642 bestOffset = (origWidth/width - offset - 1) * (width/8);
1643 else
1644 bestOffset = (uint64_t)offset * (width/8);
1645 bestMask = Mask >> (offset * (width/8) * 8);
1646 bestWidth = width;
1647 break;
1648 }
1649 newMask = newMask << width;
1650 }
1651 }
1652 }
1653 if (bestWidth) {
1654 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
1655 if (newVT.isRound()) {
1656 EVT PtrType = Lod->getOperand(1).getValueType();
1657 SDValue Ptr = Lod->getBasePtr();
1658 if (bestOffset != 0)
1659 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1660 DAG.getConstant(bestOffset, PtrType));
1661 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1662 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1663 Lod->getSrcValue(),
1664 Lod->getSrcValueOffset() + bestOffset,
1665 false, NewAlign);
1666 return DAG.getSetCC(dl, VT,
1667 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1668 DAG.getConstant(bestMask, newVT)),
1669 DAG.getConstant(0LL, newVT), Cond);
1670 }
1671 }
1672 }
1673
1674 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1675 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1676 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1677
1678 // If the comparison constant has bits in the upper part, the
1679 // zero-extended value could never match.
1680 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1681 C1.getBitWidth() - InSize))) {
1682 switch (Cond) {
1683 case ISD::SETUGT:
1684 case ISD::SETUGE:
1685 case ISD::SETEQ: return DAG.getConstant(0, VT);
1686 case ISD::SETULT:
1687 case ISD::SETULE:
1688 case ISD::SETNE: return DAG.getConstant(1, VT);
1689 case ISD::SETGT:
1690 case ISD::SETGE:
1691 // True if the sign bit of C1 is set.
1692 return DAG.getConstant(C1.isNegative(), VT);
1693 case ISD::SETLT:
1694 case ISD::SETLE:
1695 // True if the sign bit of C1 isn't set.
1696 return DAG.getConstant(C1.isNonNegative(), VT);
1697 default:
1698 break;
1699 }
1700 }
1701
1702 // Otherwise, we can perform the comparison with the low bits.
1703 switch (Cond) {
1704 case ISD::SETEQ:
1705 case ISD::SETNE:
1706 case ISD::SETUGT:
1707 case ISD::SETUGE:
1708 case ISD::SETULT:
1709 case ISD::SETULE: {
1710 EVT newVT = N0.getOperand(0).getValueType();
1711 if (DCI.isBeforeLegalizeOps() ||
1712 (isOperationLegal(ISD::SETCC, newVT) &&
1713 getCondCodeAction(Cond, newVT)==Legal))
1714 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1715 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1716 Cond);
1717 break;
1718 }
1719 default:
1720 break; // todo, be more careful with signed comparisons
1721 }
1722 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1723 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1724 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1725 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1726 EVT ExtDstTy = N0.getValueType();
1727 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1728
1729 // If the extended part has any inconsistent bits, it cannot ever
1730 // compare equal. In other words, they have to be all ones or all
1731 // zeros.
1732 APInt ExtBits =
1733 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1734 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1735 return DAG.getConstant(Cond == ISD::SETNE, VT);
1736
1737 SDValue ZextOp;
1738 EVT Op0Ty = N0.getOperand(0).getValueType();
1739 if (Op0Ty == ExtSrcTy) {
1740 ZextOp = N0.getOperand(0);
1741 } else {
1742 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1743 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1744 DAG.getConstant(Imm, Op0Ty));
1745 }
1746 if (!DCI.isCalledByLegalizer())
1747 DCI.AddToWorklist(ZextOp.getNode());
1748 // Otherwise, make this a use of a zext.
1749 return DAG.getSetCC(dl, VT, ZextOp,
1750 DAG.getConstant(C1 & APInt::getLowBitsSet(
1751 ExtDstTyBits,
1752 ExtSrcTyBits),
1753 ExtDstTy),
1754 Cond);
1755 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1756 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1757
1758 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1759 if (N0.getOpcode() == ISD::SETCC) {
1760 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1761 if (TrueWhenTrue)
1762 return N0;
1763
1764 // Invert the condition.
1765 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1766 CC = ISD::getSetCCInverse(CC,
1767 N0.getOperand(0).getValueType().isInteger());
1768 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1769 }
1770
1771 if ((N0.getOpcode() == ISD::XOR ||
1772 (N0.getOpcode() == ISD::AND &&
1773 N0.getOperand(0).getOpcode() == ISD::XOR &&
1774 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1775 isa<ConstantSDNode>(N0.getOperand(1)) &&
1776 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1777 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1778 // can only do this if the top bits are known zero.
1779 unsigned BitWidth = N0.getValueSizeInBits();
1780 if (DAG.MaskedValueIsZero(N0,
1781 APInt::getHighBitsSet(BitWidth,
1782 BitWidth-1))) {
1783 // Okay, get the un-inverted input value.
1784 SDValue Val;
1785 if (N0.getOpcode() == ISD::XOR)
1786 Val = N0.getOperand(0);
1787 else {
1788 assert(N0.getOpcode() == ISD::AND &&
1789 N0.getOperand(0).getOpcode() == ISD::XOR);
1790 // ((X^1)&1)^1 -> X & 1
1791 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1792 N0.getOperand(0).getOperand(0),
1793 N0.getOperand(1));
1794 }
1795 return DAG.getSetCC(dl, VT, Val, N1,
1796 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1797 }
1798 }
1799 }
1800
1801 APInt MinVal, MaxVal;
1802 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1803 if (ISD::isSignedIntSetCC(Cond)) {
1804 MinVal = APInt::getSignedMinValue(OperandBitSize);
1805 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1806 } else {
1807 MinVal = APInt::getMinValue(OperandBitSize);
1808 MaxVal = APInt::getMaxValue(OperandBitSize);
1809 }
1810
1811 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1812 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1813 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1814 // X >= C0 --> X > (C0-1)
1815 return DAG.getSetCC(dl, VT, N0,
1816 DAG.getConstant(C1-1, N1.getValueType()),
1817 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1818 }
1819
1820 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1821 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1822 // X <= C0 --> X < (C0+1)
1823 return DAG.getSetCC(dl, VT, N0,
1824 DAG.getConstant(C1+1, N1.getValueType()),
1825 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1826 }
1827
1828 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1829 return DAG.getConstant(0, VT); // X < MIN --> false
1830 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1831 return DAG.getConstant(1, VT); // X >= MIN --> true
1832 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1833 return DAG.getConstant(0, VT); // X > MAX --> false
1834 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1835 return DAG.getConstant(1, VT); // X <= MAX --> true
1836
1837 // Canonicalize setgt X, Min --> setne X, Min
1838 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1839 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1840 // Canonicalize setlt X, Max --> setne X, Max
1841 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1842 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1843
1844 // If we have setult X, 1, turn it into seteq X, 0
1845 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1846 return DAG.getSetCC(dl, VT, N0,
1847 DAG.getConstant(MinVal, N0.getValueType()),
1848 ISD::SETEQ);
1849 // If we have setugt X, Max-1, turn it into seteq X, Max
1850 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1851 return DAG.getSetCC(dl, VT, N0,
1852 DAG.getConstant(MaxVal, N0.getValueType()),
1853 ISD::SETEQ);
1854
1855 // If we have "setcc X, C0", check to see if we can shrink the immediate
1856 // by changing cc.
1857
1858 // SETUGT X, SINTMAX -> SETLT X, 0
1859 if (Cond == ISD::SETUGT &&
1860 C1 == APInt::getSignedMaxValue(OperandBitSize))
1861 return DAG.getSetCC(dl, VT, N0,
1862 DAG.getConstant(0, N1.getValueType()),
1863 ISD::SETLT);
1864
1865 // SETULT X, SINTMIN -> SETGT X, -1
1866 if (Cond == ISD::SETULT &&
1867 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1868 SDValue ConstMinusOne =
1869 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1870 N1.getValueType());
1871 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1872 }
1873
1874 // Fold bit comparisons when we can.
1875 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1876 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1877 if (ConstantSDNode *AndRHS =
1878 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1879 EVT ShiftTy = DCI.isBeforeLegalize() ?
1880 getPointerTy() : getShiftAmountTy();
1881 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1882 // Perform the xform if the AND RHS is a single bit.
1883 if (isPowerOf2_64(AndRHS->getZExtValue())) {
1884 return DAG.getNode(ISD::SRL, dl, VT, N0,
1885 DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1886 ShiftTy));
1887 }
1888 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1889 // (X & 8) == 8 --> (X & 8) >> 3
1890 // Perform the xform if C1 is a single bit.
1891 if (C1.isPowerOf2()) {
1892 return DAG.getNode(ISD::SRL, dl, VT, N0,
1893 DAG.getConstant(C1.logBase2(), ShiftTy));
1894 }
1895 }
1896 }
1897 }
1898
1899 if (isa<ConstantFPSDNode>(N0.getNode())) {
1900 // Constant fold or commute setcc.
1901 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1902 if (O.getNode()) return O;
1903 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1904 // If the RHS of an FP comparison is a constant, simplify it away in
1905 // some cases.
1906 if (CFP->getValueAPF().isNaN()) {
1907 // If an operand is known to be a nan, we can fold it.
1908 switch (ISD::getUnorderedFlavor(Cond)) {
1909 default: llvm_unreachable("Unknown flavor!");
1910 case 0: // Known false.
1911 return DAG.getConstant(0, VT);
1912 case 1: // Known true.
1913 return DAG.getConstant(1, VT);
1914 case 2: // Undefined.
1915 return DAG.getUNDEF(VT);
1916 }
1917 }
1918
1919 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1920 // constant if knowing that the operand is non-nan is enough. We prefer to
1921 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1922 // materialize 0.0.
1923 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1924 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1925 }
1926
1927 if (N0 == N1) {
1928 // We can always fold X == X for integer setcc's.
1929 if (N0.getValueType().isInteger())
1930 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1931 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1932 if (UOF == 2) // FP operators that are undefined on NaNs.
1933 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1934 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1935 return DAG.getConstant(UOF, VT);
1936 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1937 // if it is not already.
1938 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1939 if (NewCond != Cond)
1940 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1941 }
1942
1943 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1944 N0.getValueType().isInteger()) {
1945 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1946 N0.getOpcode() == ISD::XOR) {
1947 // Simplify (X+Y) == (X+Z) --> Y == Z
1948 if (N0.getOpcode() == N1.getOpcode()) {
1949 if (N0.getOperand(0) == N1.getOperand(0))
1950 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1951 if (N0.getOperand(1) == N1.getOperand(1))
1952 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1953 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1954 // If X op Y == Y op X, try other combinations.
1955 if (N0.getOperand(0) == N1.getOperand(1))
1956 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1957 Cond);
1958 if (N0.getOperand(1) == N1.getOperand(0))
1959 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1960 Cond);
1961 }
1962 }
1963
1964 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1965 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1966 // Turn (X+C1) == C2 --> X == C2-C1
1967 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1968 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1969 DAG.getConstant(RHSC->getAPIntValue()-
1970 LHSR->getAPIntValue(),
1971 N0.getValueType()), Cond);
1972 }
1973
1974 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1975 if (N0.getOpcode() == ISD::XOR)
1976 // If we know that all of the inverted bits are zero, don't bother
1977 // performing the inversion.
1978 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1979 return
1980 DAG.getSetCC(dl, VT, N0.getOperand(0),
1981 DAG.getConstant(LHSR->getAPIntValue() ^
1982 RHSC->getAPIntValue(),
1983 N0.getValueType()),
1984 Cond);
1985 }
1986
1987 // Turn (C1-X) == C2 --> X == C1-C2
1988 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1989 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1990 return
1991 DAG.getSetCC(dl, VT, N0.getOperand(1),
1992 DAG.getConstant(SUBC->getAPIntValue() -
1993 RHSC->getAPIntValue(),
1994 N0.getValueType()),
1995 Cond);
1996 }
1997 }
1998 }
1999
2000 // Simplify (X+Z) == X --> Z == 0
2001 if (N0.getOperand(0) == N1)
2002 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2003 DAG.getConstant(0, N0.getValueType()), Cond);
2004 if (N0.getOperand(1) == N1) {
2005 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2006 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2007 DAG.getConstant(0, N0.getValueType()), Cond);
2008 else if (N0.getNode()->hasOneUse()) {
2009 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2010 // (Z-X) == X --> Z == X<<1
2011 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
2012 N1,
2013 DAG.getConstant(1, getShiftAmountTy()));
2014 if (!DCI.isCalledByLegalizer())
2015 DCI.AddToWorklist(SH.getNode());
2016 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2017 }
2018 }
2019 }
2020
2021 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2022 N1.getOpcode() == ISD::XOR) {
2023 // Simplify X == (X+Z) --> Z == 0
2024 if (N1.getOperand(0) == N0) {
2025 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2026 DAG.getConstant(0, N1.getValueType()), Cond);
2027 } else if (N1.getOperand(1) == N0) {
2028 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2029 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2030 DAG.getConstant(0, N1.getValueType()), Cond);
2031 } else if (N1.getNode()->hasOneUse()) {
2032 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2033 // X == (Z-X) --> X<<1 == Z
2034 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2035 DAG.getConstant(1, getShiftAmountTy()));
2036 if (!DCI.isCalledByLegalizer())
2037 DCI.AddToWorklist(SH.getNode());
2038 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2039 }
2040 }
2041 }
2042
2043 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2044 // Note that where y is variable and is known to have at most
2045 // one bit set (for example, if it is z&1) we cannot do this;
2046 // the expressions are not equivalent when y==0.
2047 if (N0.getOpcode() == ISD::AND)
2048 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2049 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2050 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2051 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2052 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2053 }
2054 }
2055 if (N1.getOpcode() == ISD::AND)
2056 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2057 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2058 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2059 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2060 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2061 }
2062 }
2063 }
2064
2065 // Fold away ALL boolean setcc's.
2066 SDValue Temp;
2067 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2068 switch (Cond) {
2069 default: llvm_unreachable("Unknown integer setcc!");
2070 case ISD::SETEQ: // X == Y -> ~(X^Y)
2071 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2072 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2073 if (!DCI.isCalledByLegalizer())
2074 DCI.AddToWorklist(Temp.getNode());
2075 break;
2076 case ISD::SETNE: // X != Y --> (X^Y)
2077 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2078 break;
2079 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2080 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2081 Temp = DAG.getNOT(dl, N0, MVT::i1);
2082 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2083 if (!DCI.isCalledByLegalizer())
2084 DCI.AddToWorklist(Temp.getNode());
2085 break;
2086 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2087 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2088 Temp = DAG.getNOT(dl, N1, MVT::i1);
2089 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2090 if (!DCI.isCalledByLegalizer())
2091 DCI.AddToWorklist(Temp.getNode());
2092 break;
2093 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2094 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2095 Temp = DAG.getNOT(dl, N0, MVT::i1);
2096 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2097 if (!DCI.isCalledByLegalizer())
2098 DCI.AddToWorklist(Temp.getNode());
2099 break;
2100 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2101 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2102 Temp = DAG.getNOT(dl, N1, MVT::i1);
2103 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2104 break;
2105 }
2106 if (VT != MVT::i1) {
2107 if (!DCI.isCalledByLegalizer())
2108 DCI.AddToWorklist(N0.getNode());
2109 // FIXME: If running after legalize, we probably can't do this.
2110 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2111 }
2112 return N0;
2113 }
2114
2115 // Could not fold it.
2116 return SDValue();
2117 }
2118
2119 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2120 /// node is a GlobalAddress + offset.
2121 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2122 int64_t &Offset) const {
2123 if (isa<GlobalAddressSDNode>(N)) {
2124 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2125 GA = GASD->getGlobal();
2126 Offset += GASD->getOffset();
2127 return true;
2128 }
2129
2130 if (N->getOpcode() == ISD::ADD) {
2131 SDValue N1 = N->getOperand(0);
2132 SDValue N2 = N->getOperand(1);
2133 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2134 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2135 if (V) {
2136 Offset += V->getSExtValue();
2137 return true;
2138 }
2139 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2140 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2141 if (V) {
2142 Offset += V->getSExtValue();
2143 return true;
2144 }
2145 }
2146 }
2147 return false;
2148 }
2149
2150
2151 /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
2152 /// location that is 'Dist' units away from the location that the 'Base' load
2153 /// is loading from.
2154 bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
2155 unsigned Bytes, int Dist,
2156 const MachineFrameInfo *MFI) const {
2157 if (LD->getChain() != Base->getChain())
2158 return false;
2159 EVT VT = LD->getValueType(0);
2160 if (VT.getSizeInBits() / 8 != Bytes)
2161 return false;
2162
2163 SDValue Loc = LD->getOperand(1);
2164 SDValue BaseLoc = Base->getOperand(1);
2165 if (Loc.getOpcode() == ISD::FrameIndex) {
2166 if (BaseLoc.getOpcode() != ISD::FrameIndex)
2167 return false;
2168 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
2169 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
2170 int FS = MFI->getObjectSize(FI);
2171 int BFS = MFI->getObjectSize(BFI);
2172 if (FS != BFS || FS != (int)Bytes) return false;
2173 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
2174 }
2175 if (Loc.getOpcode() == ISD::ADD && Loc.getOperand(0) == BaseLoc) {
2176 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Loc.getOperand(1));
2177 if (V && (V->getSExtValue() == Dist*Bytes))
2178 return true;
2179 }
2180
2181 GlobalValue *GV1 = NULL;
2182 GlobalValue *GV2 = NULL;
2183 int64_t Offset1 = 0;
2184 int64_t Offset2 = 0;
2185 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
2186 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
2187 if (isGA1 && isGA2 && GV1 == GV2)
2188 return Offset1 == (Offset2 + Dist*Bytes);
2189 return false;
2190 }
2191
2192
2193 SDValue TargetLowering::
2194 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2195 // Default implementation: no optimization.
2196 return SDValue();
2197 }
2198
2199 //===----------------------------------------------------------------------===//
2200 // Inline Assembler Implementation Methods
2201 //===----------------------------------------------------------------------===//
2202
2203
2204 TargetLowering::ConstraintType
2205 TargetLowering::getConstraintType(const std::string &Constraint) const {
2206 // FIXME: lots more standard ones to handle.
2207 if (Constraint.size() == 1) {
2208 switch (Constraint[0]) {
2209 default: break;
2210 case 'r': return C_RegisterClass;
2211 case 'm': // memory
2212 case 'o': // offsetable
2213 case 'V': // not offsetable
2214 return C_Memory;
2215 case 'i': // Simple Integer or Relocatable Constant
2216 case 'n': // Simple Integer
2217 case 's': // Relocatable Constant
2218 case 'X': // Allow ANY value.
2219 case 'I': // Target registers.
2220 case 'J':
2221 case 'K':
2222 case 'L':
2223 case 'M':
2224 case 'N':
2225 case 'O':
2226 case 'P':
2227 return C_Other;
2228 }
2229 }
2230
2231 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2232 Constraint[Constraint.size()-1] == '}')
2233 return C_Register;
2234 return C_Unknown;
2235 }
2236
2237 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2238 /// with another that has more specific requirements based on the type of the
2239 /// corresponding operand.
2240 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2241 if (ConstraintVT.isInteger())
2242 return "r";
2243 if (ConstraintVT.isFloatingPoint())
2244 return "f"; // works for many targets
2245 return 0;
2246 }
2247
2248 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2249 /// vector. If it is invalid, don't add anything to Ops.
2250 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2251 char ConstraintLetter,
2252 bool hasMemory,
2253 std::vector<SDValue> &Ops,
2254 SelectionDAG &DAG) const {
2255 switch (ConstraintLetter) {
2256 default: break;
2257 case 'X': // Allows any operand; labels (basic block) use this.
2258 if (Op.getOpcode() == ISD::BasicBlock) {
2259 Ops.push_back(Op);
2260 return;
2261 }
2262 // fall through
2263 case 'i': // Simple Integer or Relocatable Constant
2264 case 'n': // Simple Integer
2265 case 's': { // Relocatable Constant
2266 // These operands are interested in values of the form (GV+C), where C may
2267 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2268 // is possible and fine if either GV or C are missing.
2269 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2270 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2271
2272 // If we have "(add GV, C)", pull out GV/C
2273 if (Op.getOpcode() == ISD::ADD) {
2274 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2275 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2276 if (C == 0 || GA == 0) {
2277 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2278 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2279 }
2280 if (C == 0 || GA == 0)
2281 C = 0, GA = 0;
2282 }
2283
2284 // If we find a valid operand, map to the TargetXXX version so that the
2285 // value itself doesn't get selected.
2286 if (GA) { // Either &GV or &GV+C
2287 if (ConstraintLetter != 'n') {
2288 int64_t Offs = GA->getOffset();
2289 if (C) Offs += C->getZExtValue();
2290 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2291 Op.getValueType(), Offs));
2292 return;
2293 }
2294 }
2295 if (C) { // just C, no GV.
2296 // Simple constants are not allowed for 's'.
2297 if (ConstraintLetter != 's') {
2298 // gcc prints these as sign extended. Sign extend value to 64 bits
2299 // now; without this it would get ZExt'd later in
2300 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2301 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2302 MVT::i64));
2303 return;
2304 }
2305 }
2306 break;
2307 }
2308 }
2309 }
2310
2311 std::vector<unsigned> TargetLowering::
2312 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2313 EVT VT) const {
2314 return std::vector<unsigned>();
2315 }
2316
2317
2318 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2319 getRegForInlineAsmConstraint(const std::string &Constraint,
2320 EVT VT) const {
2321 if (Constraint[0] != '{')
2322 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2323 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2324
2325 // Remove the braces from around the name.
2326 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
2327
2328 // Figure out which register class contains this reg.
2329 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2330 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2331 E = RI->regclass_end(); RCI != E; ++RCI) {
2332 const TargetRegisterClass *RC = *RCI;
2333
2334 // If none of the the value types for this register class are valid, we
2335 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2336 bool isLegal = false;
2337 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2338 I != E; ++I) {
2339 if (isTypeLegal(*I)) {
2340 isLegal = true;
2341 break;
2342 }
2343 }
2344
2345 if (!isLegal) continue;
2346
2347 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2348 I != E; ++I) {
2349 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
2350 return std::make_pair(*I, RC);
2351 }
2352 }
2353
2354 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2355 }
2356
2357 //===----------------------------------------------------------------------===//
2358 // Constraint Selection.
2359
2360 /// isMatchingInputConstraint - Return true of this is an input operand that is
2361 /// a matching constraint like "4".
2362 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2363 assert(!ConstraintCode.empty() && "No known constraint!");
2364 return isdigit(ConstraintCode[0]);
2365 }
2366
2367 /// getMatchedOperand - If this is an input matching constraint, this method
2368 /// returns the output operand it matches.
2369 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2370 assert(!ConstraintCode.empty() && "No known constraint!");
2371 return atoi(ConstraintCode.c_str());
2372 }
2373
2374
2375 /// getConstraintGenerality - Return an integer indicating how general CT
2376 /// is.
2377 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2378 switch (CT) {
2379 default: llvm_unreachable("Unknown constraint type!");
2380 case TargetLowering::C_Other:
2381 case TargetLowering::C_Unknown:
2382 return 0;
2383 case TargetLowering::C_Register:
2384 return 1;
2385 case TargetLowering::C_RegisterClass:
2386 return 2;
2387 case TargetLowering::C_Memory:
2388 return 3;
2389 }
2390 }
2391
2392 /// ChooseConstraint - If there are multiple different constraints that we
2393 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2394 /// This is somewhat tricky: constraints fall into four classes:
2395 /// Other -> immediates and magic values
2396 /// Register -> one specific register
2397 /// RegisterClass -> a group of regs
2398 /// Memory -> memory
2399 /// Ideally, we would pick the most specific constraint possible: if we have
2400 /// something that fits into a register, we would pick it. The problem here
2401 /// is that if we have something that could either be in a register or in
2402 /// memory that use of the register could cause selection of *other*
2403 /// operands to fail: they might only succeed if we pick memory. Because of
2404 /// this the heuristic we use is:
2405 ///
2406 /// 1) If there is an 'other' constraint, and if the operand is valid for
2407 /// that constraint, use it. This makes us take advantage of 'i'
2408 /// constraints when available.
2409 /// 2) Otherwise, pick the most general constraint present. This prefers
2410 /// 'm' over 'r', for example.
2411 ///
2412 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2413 bool hasMemory, const TargetLowering &TLI,
2414 SDValue Op, SelectionDAG *DAG) {
2415 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2416 unsigned BestIdx = 0;
2417 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2418 int BestGenerality = -1;
2419
2420 // Loop over the options, keeping track of the most general one.
2421 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2422 TargetLowering::ConstraintType CType =
2423 TLI.getConstraintType(OpInfo.Codes[i]);
2424
2425 // If this is an 'other' constraint, see if the operand is valid for it.
2426 // For example, on X86 we might have an 'rI' constraint. If the operand
2427 // is an integer in the range [0..31] we want to use I (saving a load
2428 // of a register), otherwise we must use 'r'.
2429 if (CType == TargetLowering::C_Other && Op.getNode()) {
2430 assert(OpInfo.Codes[i].size() == 1 &&
2431 "Unhandled multi-letter 'other' constraint");
2432 std::vector<SDValue> ResultOps;
2433 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2434 ResultOps, *DAG);
2435 if (!ResultOps.empty()) {
2436 BestType = CType;
2437 BestIdx = i;
2438 break;
2439 }
2440 }
2441
2442 // This constraint letter is more general than the previous one, use it.
2443 int Generality = getConstraintGenerality(CType);
2444 if (Generality > BestGenerality) {
2445 BestType = CType;
2446 BestIdx = i;
2447 BestGenerality = Generality;
2448 }
2449 }
2450
2451 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2452 OpInfo.ConstraintType = BestType;
2453 }
2454
2455 /// ComputeConstraintToUse - Determines the constraint code and constraint
2456 /// type to use for the specific AsmOperandInfo, setting
2457 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2458 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2459 SDValue Op,
2460 bool hasMemory,
2461 SelectionDAG *DAG) const {
2462 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2463
2464 // Single-letter constraints ('r') are very common.
2465 if (OpInfo.Codes.size() == 1) {
2466 OpInfo.ConstraintCode = OpInfo.Codes[0];
2467 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2468 } else {
2469 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2470 }
2471
2472 // 'X' matches anything.
2473 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2474 // Labels and constants are handled elsewhere ('X' is the only thing
2475 // that matches labels). For Functions, the type here is the type of
2476 // the result, which is not what we want to look at; leave them alone.
2477 Value *v = OpInfo.CallOperandVal;
2478 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2479 OpInfo.CallOperandVal = v;
2480 return;
2481 }
2482
2483 // Otherwise, try to resolve it to something we know about by looking at
2484 // the actual operand type.
2485 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2486 OpInfo.ConstraintCode = Repl;
2487 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2488 }
2489 }
2490 }
2491
2492 //===----------------------------------------------------------------------===//
2493 // Loop Strength Reduction hooks
2494 //===----------------------------------------------------------------------===//
2495
2496 /// isLegalAddressingMode - Return true if the addressing mode represented
2497 /// by AM is legal for this target, for a load/store of the specified type.
2498 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2499 const Type *Ty) const {
2500 // The default implementation of this implements a conservative RISCy, r+r and
2501 // r+i addr mode.
2502
2503 // Allows a sign-extended 16-bit immediate field.
2504 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2505 return false;
2506
2507 // No global is ever allowed as a base.
2508 if (AM.BaseGV)
2509 return false;
2510
2511 // Only support r+r,
2512 switch (AM.Scale) {
2513 case 0: // "r+i" or just "i", depending on HasBaseReg.
2514 break;
2515 case 1:
2516 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2517 return false;
2518 // Otherwise we have r+r or r+i.
2519 break;
2520 case 2:
2521 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2522 return false;
2523 // Allow 2*r as r+r.
2524 break;
2525 }
2526
2527 return true;
2528 }
2529
2530 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2531 /// return a DAG expression to select that will generate the same value by
2532 /// multiplying by a magic number. See:
2533 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2534 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2535 std::vector<SDNode*>* Created) const {
2536 EVT VT = N->getValueType(0);
2537 DebugLoc dl= N->getDebugLoc();
2538
2539 // Check to see if we can do this.
2540 // FIXME: We should be more aggressive here.
2541 if (!isTypeLegal(VT))
2542 return SDValue();
2543
2544 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2545 APInt::ms magics = d.magic();
2546
2547 // Multiply the numerator (operand 0) by the magic value
2548 // FIXME: We should support doing a MUL in a wider type
2549 SDValue Q;
2550 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2551 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2552 DAG.getConstant(magics.m, VT));
2553 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2554 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2555 N->getOperand(0),
2556 DAG.getConstant(magics.m, VT)).getNode(), 1);
2557 else
2558 return SDValue(); // No mulhs or equvialent
2559 // If d > 0 and m < 0, add the numerator
2560 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2561 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2562 if (Created)
2563 Created->push_back(Q.getNode());
2564 }
2565 // If d < 0 and m > 0, subtract the numerator.
2566 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2567 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2568 if (Created)
2569 Created->push_back(Q.getNode());
2570 }
2571 // Shift right algebraic if shift value is nonzero
2572 if (magics.s > 0) {
2573 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2574 DAG.getConstant(magics.s, getShiftAmountTy()));
2575 if (Created)
2576 Created->push_back(Q.getNode());
2577 }
2578 // Extract the sign bit and add it to the quotient
2579 SDValue T =
2580 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2581 getShiftAmountTy()));
2582 if (Created)
2583 Created->push_back(T.getNode());
2584 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2585 }
2586
2587 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2588 /// return a DAG expression to select that will generate the same value by
2589 /// multiplying by a magic number. See:
2590 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2591 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2592 std::vector<SDNode*>* Created) const {
2593 EVT VT = N->getValueType(0);
2594 DebugLoc dl = N->getDebugLoc();
2595
2596 // Check to see if we can do this.
2597 // FIXME: We should be more aggressive here.
2598 if (!isTypeLegal(VT))
2599 return SDValue();
2600
2601 // FIXME: We should use a narrower constant when the upper
2602 // bits are known to be zero.
2603 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2604 APInt::mu magics = N1C->getAPIntValue().magicu();
2605
2606 // Multiply the numerator (operand 0) by the magic value
2607 // FIXME: We should support doing a MUL in a wider type
2608 SDValue Q;
2609 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2610 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2611 DAG.getConstant(magics.m, VT));
2612 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2613 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2614 N->getOperand(0),
2615 DAG.getConstant(magics.m, VT)).getNode(), 1);
2616 else
2617 return SDValue(); // No mulhu or equvialent
2618 if (Created)
2619 Created->push_back(Q.getNode());
2620
2621 if (magics.a == 0) {
2622 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2623 "We shouldn't generate an undefined shift!");
2624 return DAG.getNode(ISD::SRL, dl, VT, Q,
2625 DAG.getConstant(magics.s, getShiftAmountTy()));
2626 } else {
2627 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2628 if (Created)
2629 Created->push_back(NPQ.getNode());
2630 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2631 DAG.getConstant(1, getShiftAmountTy()));
2632 if (Created)
2633 Created->push_back(NPQ.getNode());
2634 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2635 if (Created)
2636 Created->push_back(NPQ.getNode());
2637 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2638 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2639 }
2640 }
AVR Backend for LLVM