lib/CodeGen/TargetInstrInfoImpl.cpp

   1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetInstrInfoImpl class, it just provides default
  11 // implementations of various methods.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "llvm/Target/TargetInstrInfo.h"
  16 #include "llvm/ADT/SmallVector.h"
  17 #include "llvm/CodeGen/MachineFrameInfo.h"
  18 #include "llvm/CodeGen/MachineInstr.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/PseudoSourceValue.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 using namespace llvm;
  24
  25 // commuteInstruction - The default implementation of this method just exchanges
  26 // the two operands returned by findCommutedOpIndices.
  27 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
  28                                                       bool NewMI) const {
  29   const TargetInstrDesc &TID = MI->getDesc();
  30   bool HasDef = TID.getNumDefs();
  31   if (HasDef && !MI->getOperand(0).isReg())
  32     // No idea how to commute this instruction. Target should implement its own.
  33     return 0;
  34   unsigned Idx1, Idx2;
  35   if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
  36     std::string msg;
  37     raw_string_ostream Msg(msg);
  38     Msg << "Don't know how to commute: " << *MI;
  39     llvm_report_error(Msg.str());
  40   }
  41
  42   assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
  43          "This only knows how to commute register operands so far");
  44   unsigned Reg1 = MI->getOperand(Idx1).getReg();
  45   unsigned Reg2 = MI->getOperand(Idx2).getReg();
  46   bool Reg1IsKill = MI->getOperand(Idx1).isKill();
  47   bool Reg2IsKill = MI->getOperand(Idx2).isKill();
  48   bool ChangeReg0 = false;
  49   if (HasDef && MI->getOperand(0).getReg() == Reg1) {
  50     // Must be two address instruction!
  51     assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
  52            "Expecting a two-address instruction!");
  53     Reg2IsKill = false;
  54     ChangeReg0 = true;
  55   }
  56
  57   if (NewMI) {
  58     // Create a new instruction.
  59     unsigned Reg0 = HasDef
  60       ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
  61     bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
  62     MachineFunction &MF = *MI->getParent()->getParent();
  63     if (HasDef)
  64       return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
  65         .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
  66         .addReg(Reg2, getKillRegState(Reg2IsKill))
  67         .addReg(Reg1, getKillRegState(Reg2IsKill));
  68     else
  69       return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
  70         .addReg(Reg2, getKillRegState(Reg2IsKill))
  71         .addReg(Reg1, getKillRegState(Reg2IsKill));
  72   }
  73
  74   if (ChangeReg0)
  75     MI->getOperand(0).setReg(Reg2);
  76   MI->getOperand(Idx2).setReg(Reg1);
  77   MI->getOperand(Idx1).setReg(Reg2);
  78   MI->getOperand(Idx2).setIsKill(Reg1IsKill);
  79   MI->getOperand(Idx1).setIsKill(Reg2IsKill);
  80   return MI;
  81 }
  82
  83 /// findCommutedOpIndices - If specified MI is commutable, return the two
  84 /// operand indices that would swap value. Return true if the instruction
  85 /// is not in a form which this routine understands.
  86 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
  87                                                 unsigned &SrcOpIdx1,
  88                                                 unsigned &SrcOpIdx2) const {
  89   const TargetInstrDesc &TID = MI->getDesc();
  90   if (!TID.isCommutable())
  91     return false;
  92   // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
  93   // is not true, then the target must implement this.
  94   SrcOpIdx1 = TID.getNumDefs();
  95   SrcOpIdx2 = SrcOpIdx1 + 1;
  96   if (!MI->getOperand(SrcOpIdx1).isReg() ||
  97       !MI->getOperand(SrcOpIdx2).isReg())
  98     // No idea.
  99     return false;
 100   return true;
 101 }
 102
 103
 104 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
 105                             const SmallVectorImpl<MachineOperand> &Pred) const {
 106   bool MadeChange = false;
 107   const TargetInstrDesc &TID = MI->getDesc();
 108   if (!TID.isPredicable())
 109     return false;
 110
 111   for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
 112     if (TID.OpInfo[i].isPredicate()) {
 113       MachineOperand &MO = MI->getOperand(i);
 114       if (MO.isReg()) {
 115         MO.setReg(Pred[j].getReg());
 116         MadeChange = true;
 117       } else if (MO.isImm()) {
 118         MO.setImm(Pred[j].getImm());
 119         MadeChange = true;
 120       } else if (MO.isMBB()) {
 121         MO.setMBB(Pred[j].getMBB());
 122         MadeChange = true;
 123       }
 124       ++j;
 125     }
 126   }
 127   return MadeChange;
 128 }
 129
 130 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
 131                                         MachineBasicBlock::iterator I,
 132                                         unsigned DestReg,
 133                                         unsigned SubIdx,
 134                                         const MachineInstr *Orig) const {
 135   MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
 136   MachineOperand &MO = MI->getOperand(0);
 137   MO.setReg(DestReg);
 138   MO.setSubReg(SubIdx);
 139   MBB.insert(I, MI);
 140 }
 141
 142 bool TargetInstrInfoImpl::isDeadInstruction(const MachineInstr *MI) const {
 143   const TargetInstrDesc &TID = MI->getDesc();
 144   if (TID.mayLoad() || TID.mayStore() || TID.isCall() || TID.isTerminator() ||
 145       TID.isCall() || TID.isBarrier() || TID.isReturn() ||
 146       TID.hasUnmodeledSideEffects())
 147     return false;
 148   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 149     const MachineOperand &MO = MI->getOperand(i);
 150     if (!MO.isReg() || !MO.getReg())
 151       continue;
 152     if (MO.isDef() && !MO.isDead())
 153       return false;
 154     if (MO.isUse() && MO.isKill())
 155       // FIXME: We can't remove kill markers or else the scavenger will assert.
 156       // An alternative is to add a ADD pseudo instruction to replace kill
 157       // markers.
 158       return false;
 159   }
 160   return true;
 161 }
 162
 163 unsigned
 164 TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
 165   unsigned FnSize = 0;
 166   for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
 167        MBBI != E; ++MBBI) {
 168     const MachineBasicBlock &MBB = *MBBI;
 169     for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
 170          I != E; ++I)
 171       FnSize += GetInstSizeInBytes(I);
 172   }
 173   return FnSize;
 174 }
 175
 176 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
 177 /// slot into the specified machine instruction for the specified operand(s).
 178 /// If this is possible, a new instruction is returned with the specified
 179 /// operand folded, otherwise NULL is returned. The client is responsible for
 180 /// removing the old instruction and adding the new one in the instruction
 181 /// stream.
 182 MachineInstr*
 183 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
 184                                    MachineInstr* MI,
 185                                    const SmallVectorImpl<unsigned> &Ops,
 186                                    int FrameIndex) const {
 187   unsigned Flags = 0;
 188   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
 189     if (MI->getOperand(Ops[i]).isDef())
 190       Flags |= MachineMemOperand::MOStore;
 191     else
 192       Flags |= MachineMemOperand::MOLoad;
 193
 194   // Ask the target to do the actual folding.
 195   MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
 196   if (!NewMI) return 0;
 197
 198   assert((!(Flags & MachineMemOperand::MOStore) ||
 199           NewMI->getDesc().mayStore()) &&
 200          "Folded a def to a non-store!");
 201   assert((!(Flags & MachineMemOperand::MOLoad) ||
 202           NewMI->getDesc().mayLoad()) &&
 203          "Folded a use to a non-load!");
 204   const MachineFrameInfo &MFI = *MF.getFrameInfo();
 205   assert(MFI.getObjectOffset(FrameIndex) != -1);
 206   MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FrameIndex),
 207                         Flags,
 208                         MFI.getObjectOffset(FrameIndex),
 209                         MFI.getObjectSize(FrameIndex),
 210                         MFI.getObjectAlignment(FrameIndex));
 211   NewMI->addMemOperand(MF, MMO);
 212
 213   return NewMI;
 214 }
 215
 216 /// foldMemoryOperand - Same as the previous version except it allows folding
 217 /// of any load and store from / to any address, not just from a specific
 218 /// stack slot.
 219 MachineInstr*
 220 TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
 221                                    MachineInstr* MI,
 222                                    const SmallVectorImpl<unsigned> &Ops,
 223                                    MachineInstr* LoadMI) const {
 224   assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
 225 #ifndef NDEBUG
 226   for (unsigned i = 0, e = Ops.size(); i != e; ++i)
 227     assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
 228 #endif
 229
 230   // Ask the target to do the actual folding.
 231   MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
 232   if (!NewMI) return 0;
 233
 234   // Copy the memoperands from the load to the folded instruction.
 235   for (std::list<MachineMemOperand>::iterator I = LoadMI->memoperands_begin(),
 236        E = LoadMI->memoperands_end(); I != E; ++I)
 237     NewMI->addMemOperand(MF, *I);
 238
 239   return NewMI;
 240 }