lib/Target/Blackfin/Blackfin.td

   1 //===- Blackfin.td - Describe the Blackfin Target Machine --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // Blackfin Subtarget features.
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureSDRAM : SubtargetFeature<"sdram", "sdram", "true",
  24     "Build for SDRAM">;
  25
  26 def FeatureICPLB : SubtargetFeature<"icplb", "icplb", "true",
  27     "Assume instruction cache lookaside buffers are enabled at runtime">;
  28
  29 //===----------------------------------------------------------------------===//
  30 // Bugs in the silicon becomes workarounds in the compiler.
  31 // See http://www.analog.com/ for the full list of IC anomalies.
  32 //===----------------------------------------------------------------------===//
  33
  34 def WA_MI_SHIFT : SubtargetFeature<"mi-shift-anomaly","wa_mi_shift", "true",
  35     "Work around 05000074 - "
  36     "Multi-Issue Instruction with dsp32shiftimm and P-reg Store">;
  37
  38 def WA_CSYNC : SubtargetFeature<"csync-anomaly","wa_csync", "true",
  39     "Work around 05000244 - "
  40     "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control">;
  41
  42 def WA_SPECLD : SubtargetFeature<"specld-anomaly","wa_specld", "true",
  43     "Work around 05000245 - "
  44     "Access in the Shadow of a Conditional Branch">;
  45
  46 def WA_HWLOOP : SubtargetFeature<"hwloop-anomaly","wa_hwloop", "true",
  47     "Work around 05000257 - "
  48     "Interrupt/Exception During Short Hardware Loop">;
  49
  50 def WA_MMR_STALL : SubtargetFeature<"mmr-stall-anomaly","wa_mmr_stall", "true",
  51     "Work around 05000283 - "
  52     "System MMR Write Is Stalled Indefinitely when Killed">;
  53
  54 def WA_LCREGS : SubtargetFeature<"lcregs-anomaly","wa_lcregs", "true",
  55     "Work around 05000312 - "
  56     "SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted">;
  57
  58 def WA_KILLED_MMR : SubtargetFeature<"killed-mmr-anomaly",
  59                                      "wa_killed_mmr", "true",
  60     "Work around 05000315 - "
  61     "Killed System MMR Write Completes Erroneously on Next System MMR Access">;
  62
  63 def WA_RETS : SubtargetFeature<"rets-anomaly", "wa_rets", "true",
  64     "Work around 05000371 - "
  65     "Possible RETS Register Corruption when Subroutine Is under 5 Cycles">;
  66
  67 def WA_IND_CALL : SubtargetFeature<"ind-call-anomaly", "wa_ind_call", "true",
  68     "Work around 05000426 - "
  69     "Speculative Fetches of Indirect-Pointer Instructions">;
  70
  71 //===----------------------------------------------------------------------===//
  72 // Register File, Calling Conv, Instruction Descriptions
  73 //===----------------------------------------------------------------------===//
  74
  75 include "BlackfinRegisterInfo.td"
  76 include "BlackfinCallingConv.td"
  77 include "BlackfinInstrInfo.td"
  78
  79 def BlackfinInstrInfo : InstrInfo {}
  80
  81 //===----------------------------------------------------------------------===//
  82 // Blackfin processors supported.
  83 //===----------------------------------------------------------------------===//
  84
  85 class Proc<string Name, string Suffix, list<SubtargetFeature> Features>
  86  : Processor<!strconcat(Name, Suffix), NoItineraries, Features>;
  87
  88 def : Proc<"generic", "", []>;
  89
  90 multiclass Core<string Name,string Suffix,
  91                 list<SubtargetFeature> Features> {
  92   def : Proc<Name, Suffix, Features>;
  93   def : Proc<Name, "", Features>;
  94   def : Proc<Name, "-none", []>;
  95 }
  96
  97 multiclass CoreEdinburgh<string Name>
  98       : Core<Name, "-0.6", [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS]> {
  99   def : Proc<Name, "-0.5",
 100         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 101          WA_RETS]>;
 102   def : Proc<Name, "-0.4",
 103         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 104          WA_KILLED_MMR, WA_RETS]>;
 105   def : Proc<Name, "-0.3",
 106         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 107          WA_KILLED_MMR, WA_RETS]>;
 108   def : Proc<Name, "-any",
 109         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 110          WA_KILLED_MMR, WA_RETS]>;
 111 }
 112 multiclass CoreBraemar<string Name>
 113        : Core<Name, "-0.3",
 114          [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]> {
 115   def  : Proc<Name, "-0.2",
 116          [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 117           WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 118   def  : Proc<Name, "-any",
 119          [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 120           WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 121 }
 122 multiclass CoreStirling<string Name>
 123       : Core<Name, "-0.5", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 124   def : Proc<Name, "-0.4",
 125         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
 126   def : Proc<Name, "-0.3",
 127         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 128          WA_RETS, WA_IND_CALL]>;
 129   def : Proc<Name, "-any",
 130         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 131          WA_RETS, WA_IND_CALL]>;
 132 }
 133 multiclass CoreMoab<string Name>
 134       : Core<Name, "-0.3", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 135   def : Proc<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 136   def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 137   def : Proc<Name, "-0.0",
 138         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
 139   def : Proc<Name, "-any",
 140         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
 141 }
 142 multiclass CoreTeton<string Name>
 143       : Core<Name, "-0.5",
 144         [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
 145          WA_RETS, WA_IND_CALL]> {
 146   def : Proc<Name, "-0.3",
 147         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 148          WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 149   def : Proc<Name, "-any",
 150         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
 151          WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
 152 }
 153 multiclass CoreKookaburra<string Name>
 154       : Core<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 155   def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 156   def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 157   def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
 158 }
 159 multiclass CoreMockingbird<string Name>
 160       : Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 161   def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 162   def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 163 }
 164 multiclass CoreBrodie<string Name>
 165       : Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
 166   def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 167   def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
 168 }
 169
 170 defm BF512 : CoreBrodie<"bf512">;
 171 defm BF514 : CoreBrodie<"bf514">;
 172 defm BF516 : CoreBrodie<"bf516">;
 173 defm BF518 : CoreBrodie<"bf518">;
 174 defm BF522 : CoreMockingbird<"bf522">;
 175 defm BF523 : CoreKookaburra<"bf523">;
 176 defm BF524 : CoreMockingbird<"bf524">;
 177 defm BF525 : CoreKookaburra<"bf525">;
 178 defm BF526 : CoreMockingbird<"bf526">;
 179 defm BF527 : CoreKookaburra<"bf527">;
 180 defm BF531 : CoreEdinburgh<"bf531">;
 181 defm BF532 : CoreEdinburgh<"bf532">;
 182 defm BF533 : CoreEdinburgh<"bf533">;
 183 defm BF534 : CoreBraemar<"bf534">;
 184 defm BF536 : CoreBraemar<"bf536">;
 185 defm BF537 : CoreBraemar<"bf537">;
 186 defm BF538 : CoreStirling<"bf538">;
 187 defm BF539 : CoreStirling<"bf539">;
 188 defm BF542 : CoreMoab<"bf542">;
 189 defm BF544 : CoreMoab<"bf544">;
 190 defm BF548 : CoreMoab<"bf548">;
 191 defm BF549 : CoreMoab<"bf549">;
 192 defm BF561 : CoreTeton<"bf561">;
 193
 194 //===----------------------------------------------------------------------===//
 195 // Declare the target which we are implementing
 196 //===----------------------------------------------------------------------===//
 197
 198 def Blackfin : Target {
 199   // Pull in Instruction Info:
 200   let InstructionSet = BlackfinInstrInfo;
 201 }